diff options
Diffstat (limited to 'Documentation/devicetree/bindings/soc/fsl')
25 files changed, 1495 insertions, 893 deletions
diff --git a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt deleted file mode 100644 index 2a00e14e11e0..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt +++ /dev/null @@ -1,56 +0,0 @@ -QorIQ DPAA Buffer Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Portal - - Example - -BMan Portal Node - -Portals are memory mapped interfaces to BMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the BMan - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,bman-portal-<hardware revision>" - May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property - -EXAMPLE - -The example below shows a (P4080) BMan portals container/bus node with two portals - - bman-portals@ff4000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4000000 0x200000>; - - bman-portal@0 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x100000 0x1000>; - interrupts = <105 2 0 0>; - }; - bman-portal@4000 { - compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <107 2 0 0>; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt b/Documentation/devicetree/bindings/soc/fsl/bman.txt deleted file mode 100644 index 48eed140765b..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/bman.txt +++ /dev/null @@ -1,137 +0,0 @@ -QorIQ DPAA Buffer Manager Device Tree Bindings - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - BMan Node - - BMan Private Memory Node - - Example - -BMan Node - -The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). -BMan supports hardware allocation and deallocation of buffers belonging to pools -originally created by software with configurable depletion thresholds. This -binding covers the CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,bman" - May include "fsl,<SoC>-bman" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Registers region within the CCSR address space - -The BMan revision information is located in the BMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property. The error interrupt - -- fsl,bman-portals - Usage: Required - Value type: <phandle> - Definition: Phandle to this BMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -Devices connected to a BMan instance via Direct Connect Portals (DCP) must link -to the respective BMan instance - -- fsl,bman - Usage: Required - Value type: <prop-encoded-array> - Description: List of phandle and DCP index pairs, to the BMan instance - to which this device is connected via the DCP - -BMan Private Memory Node - -BMan requires a contiguous range of physical memory used for the backing store -for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as -a node under the /reserved-memory node. - -The BMan FBPR memory node must be named "bman-fbpr" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,bman-fbpr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FBPR private memory: - - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to - 16 GiB - - The alignment must be a muliptle of the memory size - -The size of the FBPR must be chosen by observing the hardware features configured -via the Reset Configuration Word (RCW) and that are relevant to a specific board -(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports, -etc.). The size configured in the DT must reflect the hardware capabilities and -not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a BMan FBPR dynamic allocation memory node - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bman_fbpr: bman-fbpr { - compatible = "shared-mem-pool"; - size = <0 0x1000000>; - alignment = <0 0x1000000>; - no-map; - }; - }; - -The example below shows a (P4080) BMan CCSR-space node - - bportals: bman-portals@ff4000000 { - ... - }; - - crypto@300000 { - ... - fsl,bman = <&bman, 2>; - ... - }; - - bman: bman@31a000 { - compatible = "fsl,bman"; - reg = <0x31a000 0x1000>; - interrupts = <16 2 1 2>; - fsl,liodn = <0x17>; - fsl,bman-portals = <&bportals>; - memory-region = <&bman_fbpr>; - }; - - fman@400000 { - ... - fsl,bman = <&bman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml new file mode 100644 index 000000000000..53b07d4edc77 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-firmware.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-firmware.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Firmware Node + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + This node defines a firmware binary that is embedded in the device tree, for + the purpose of passing the firmware from bootloader to the kernel, or from + the hypervisor to the guest. + + The firmware node itself contains the firmware binary contents, a compatible + property, and any firmware-specific properties. The node should be placed + inside a QE node that needs it. Doing so eliminates the need for a + fsl,firmware-phandle property. Other QE nodes that need the same firmware + should define an fsl,firmware-phandle property that points to the firmware node + in the first QE node. + + The fsl,firmware property can be specified in the DTS (possibly using incbin) + or can be inserted by the boot loader at boot time. + +properties: + compatible: + enum: + - fsl,qe-firmware + + fsl,firmware: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + A standard property. This property contains the firmware binary "blob". + +required: + - compatible + - fsl,firmware + +additionalProperties: false + +examples: + - | + qe-firmware { + compatible = "fsl,qe-firmware"; + fsl,firmware = <0x70 0xcd 0x00 0x00 0x01 0x46 0x45>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml new file mode 100644 index 000000000000..8267ad00727b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ic.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Interrupt Controller (IC) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,qe-ic + + reg: + maxItems: 1 + + interrupts: + items: + - description: QE interrupt + - description: QE critical + - description: QE error + minItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <95 2 0 0 94 2 0 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml new file mode 100644 index 000000000000..cf0f38dbbe0d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-muram.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine Multi-User RAM (MURAM) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: Multi-User RAM (MURAM) + +properties: + compatible: + items: + - const: fsl,qe-muram + - const: fsl,cpm-muram + + ranges: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, slave] + + +patternProperties: + '^data\-only@[a-f0-9]+$': + type: object + properties: + compatible: + items: + - const: fsl,qe-muram-data + - const: fsl,cpm-muram-data + + reg: + maxItems: 1 + + required: + - compatible + - reg + + additionalProperties: false + +required: + - compatible + - ranges + +additionalProperties: false + +examples: + - | + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + #address-cells = <1>; + #size-cells = <1>; + + data-only@0{ + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml new file mode 100644 index 000000000000..8e58ab58c063 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-si.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-si.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Serial Interface Block (SI) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The SI manages the routing of eight TDM lines to the QE block serial drivers, + the MCC and the UCCs, for receive and transmit. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,ls1043-qe-si + - const: fsl,t1040-qe-si + - enum: + - fsl,t1040-qe-si + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml new file mode 100644 index 000000000000..cc4ed48d786c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-siram.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-siram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module Serial Interface Block RAM(SIRAM) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + store the routing entries of SI + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,ls1043-qe-siram + - const: fsl,t1040-qe-siram + - const: fsl,t1040-qe-siram + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml new file mode 100644 index 000000000000..3b50e0a003ca --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-tsa.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC QE Time-slot assigner (TSA) controller + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. + Its purpose is to route some TDM time-slots to other internal serial + controllers. + +properties: + compatible: + items: + - enum: + - fsl,mpc8321-tsa + - const: fsl,qe-tsa + + reg: + items: + - description: SI (Serial Interface) register base + - description: SI RAM base + + reg-names: + items: + - const: si_regs + - const: si_ram + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^tdm@[0-3]$': + description: + The TDM managed by this controller + type: object + + additionalProperties: false + + properties: + reg: + minimum: 0 + maximum: 3 + description: + The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3 + for TDMd. + + fsl,common-rxtx-pins: + $ref: /schemas/types.yaml#/definitions/flag + description: + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. + Without the 'fsl,common-rxtx-pins' property, the four pins are used. + With the 'fsl,common-rxtx-pins' property, two pins are used. + + clocks: + minItems: 2 + items: + - description: Receive sync clock + - description: Receive data clock + - description: Transmit sync clock + - description: Transmit data clock + + clock-names: + minItems: 2 + items: + - const: rsync + - const: rclk + - const: tsync + - const: tclk + + fsl,rx-frame-sync-delay-bits: + enum: [0, 1, 2, 3] + default: 0 + description: | + Receive frame sync delay in number of bits. + Indicates the delay between the Rx sync and the first bit of the Rx + frame. + + fsl,tx-frame-sync-delay-bits: + enum: [0, 1, 2, 3] + default: 0 + description: | + Transmit frame sync delay in number of bits. + Indicates the delay between the Tx sync and the first bit of the Tx + frame. + + fsl,clock-falling-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Data is sent on falling edge of the clock (and received on the rising + edge). If not present, data is sent on the rising edge (and received + on the falling edge). + + fsl,fsync-rising-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Frame sync pulses are sampled with the rising edge of the channel + clock. If not present, pulses are sampled with the falling edge. + + fsl,fsync-active-low: + $ref: /schemas/types.yaml#/definitions/flag + description: + Frame sync signals are active on low logic level. + If not present, sync signals are active on high level. + + fsl,double-speed-clock: + $ref: /schemas/types.yaml#/definitions/flag + description: + The channel clock is twice the data rate. + + patternProperties: + '^fsl,[rt]x-ts-routes$': + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of tuple that indicates the Tx or Rx time-slots routes. + items: + items: + - description: + The number of time-slots + minimum: 1 + maximum: 64 + - description: | + The source (Tx) or destination (Rx) serial interface + (dt-bindings/soc/qe-fsl,tsa.h defines these values) + - 0: No destination + - 1: UCC1 + - 2: UCC2 + - 3: UCC3 + - 4: UCC4 + - 5: UCC5 + enum: [0, 1, 2, 3, 4, 5] + minItems: 1 + maxItems: 64 + + allOf: + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. + # Else, the 4 clocks must be present. + - if: + required: + - fsl,common-rxtx-pins + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + + required: + - reg + - clocks + - clock-names + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/qe-fsl,tsa.h> + + tsa@ae0 { + compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa"; + reg = <0xae0 0x10>, + <0xc00 0x200>; + reg-names = "si_regs", "si_ram"; + + #address-cells = <1>; + #size-cells = <0>; + + tdm@0 { + /* TDMa */ + reg = <0>; + + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; + clock-names = "rsync", "rclk"; + + fsl,common-rxtx-pins; + fsl,fsync-rising-edge; + + fsl,tx-ts-routes = <2 0>, /* TS 0..1 */ + <24 FSL_QE_TSA_UCC4>, /* TS 2..25 */ + <1 0>, /* TS 26 */ + <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ + + fsl,rx-ts-routes = <2 0>, /* TS 0..1 */ + <24 FSL_QE_TSA_UCC4>, /* 2..25 */ + <1 0>, /* TS 26 */ + <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml new file mode 100644 index 000000000000..71ae64cb8a4f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PowerQUICC QE QUICC Multichannel Controller (QMC) + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: + The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one + serial controller using the same TDM physical interface routed from TSA. + +properties: + compatible: + items: + - enum: + - fsl,mpc8321-ucc-qmc + - const: fsl,qe-ucc-qmc + + reg: + items: + - description: UCC (Unified communication controller) register base + - description: Dual port ram base + + reg-names: + items: + - const: ucc_regs + - const: dpram + + interrupts: + maxItems: 1 + description: UCC interrupt line in the QE interrupt controller + + fsl,tsa-serial: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TSA node + - enum: [1, 2, 3, 4, 5] + description: | + TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these + values) + - 1: UCC1 + - 2: UCC2 + - 3: UCC3 + - 4: UCC4 + - 5: UCC5 + description: + Should be a phandle/number pair. The phandle to TSA node and the TSA + serial interface to use. + + fsl,soft-qmc: + $ref: /schemas/types.yaml#/definitions/string + description: + Soft QMC firmware name to load. If this property is omitted, no firmware + are used. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^channel@([0-9]|[1-5][0-9]|6[0-3])$': + description: + A channel managed by this controller + type: object + additionalProperties: false + + properties: + compatible: + items: + - enum: + - fsl,mpc8321-ucc-qmc-hdlc + - const: fsl,qe-ucc-qmc-hdlc + - const: fsl,qmc-hdlc + + reg: + minimum: 0 + maximum: 63 + description: + The channel number + + fsl,operational-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [transparent, hdlc] + default: transparent + description: | + The channel operational mode + - hdlc: The channel handles HDLC frames + - transparent: The channel handles raw data without any processing + + fsl,reverse-data: + $ref: /schemas/types.yaml#/definitions/flag + description: + The bit order as seen on the channels is reversed, + transmitting/receiving the MSB of each octet first. + This flag is used only in 'transparent' mode. + + fsl,tx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Tx time-slots within the Tx time-slots routed by the + TSA to this cell. + + fsl,rx-ts-mask: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + Channel assigned Rx time-slots within the Rx time-slots routed by the + TSA to this cell. + + fsl,framer: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the framer node. The framer is in charge of an E1/T1 line + interface connected to the TDM bus. It can be used to get the E1/T1 line + status such as link up/down. + + allOf: + - if: + properties: + compatible: + not: + contains: + const: fsl,qmc-hdlc + then: + properties: + fsl,framer: false + + required: + - reg + - fsl,tx-ts-mask + - fsl,rx-ts-mask + +required: + - compatible + - reg + - reg-names + - interrupts + - fsl,tsa-serial + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/soc/qe-fsl,tsa.h> + + qmc@a60 { + compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc"; + reg = <0x3200 0x200>, + <0x10000 0x1000>; + reg-names = "ucc_regs", "dpram"; + interrupts = <35>; + interrupt-parent = <&qeic>; + fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin"; + + #address-cells = <1>; + #size-cells = <0>; + + fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>; + + channel@16 { + /* Ch16 : First 4 even TS from all routed from TSA */ + reg = <16>; + fsl,operational-mode = "transparent"; + fsl,reverse-data; + fsl,tx-ts-mask = <0x00000000 0x000000aa>; + fsl,rx-ts-mask = <0x00000000 0x000000aa>; + }; + + channel@17 { + /* Ch17 : First 4 odd TS from all routed from TSA */ + reg = <17>; + fsl,operational-mode = "transparent"; + fsl,reverse-data; + fsl,tx-ts-mask = <0x00000000 0x00000055>; + fsl,rx-ts-mask = <0x00000000 0x00000055>; + }; + + channel@19 { + /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ + compatible = "fsl,mpc8321-ucc-qmc-hdlc", + "fsl,qe-ucc-qmc-hdlc", + "fsl,qmc-hdlc"; + reg = <19>; + fsl,operational-mode = "hdlc"; + fsl,tx-ts-mask = <0x00000000 0x0000ff00>; + fsl,rx-ts-mask = <0x00000000 0x0000ff00>; + fsl,framer = <&framer>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml new file mode 100644 index 000000000000..89cdf5e1d0a8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine module (QE) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + This represents qe module that is installed on PowerQUICC II Pro. + + NOTE: This is an interim binding; it should be updated to fit + in with the CPM binding later in this document. + + Basically, it is a bus of devices, that could act more or less + as a complete entity (UCC, USB etc ). All of them should be siblings on + the "root" qe node, using the common properties from there. + The description below applies to the qe of MPC8360 and + more nodes and properties would be extended in the future. + +properties: + compatible: + items: + - const: fsl,qe + - const: simple-bus + + reg: + maxItems: 1 + + ranges: + maxItems: 1 + + model: + $ref: /schemas/types.yaml#/definitions/string + enum: [QE, CPM, CPM2] + + bus-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: the clock frequency for QUICC Engine. + + fsl,qe-num-riscs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: define how many RISC engines the QE has. + + fsl,qe-snums: + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 28 + description: + defining the array of serial number (SNUM) values for the virtual + threads. + + fsl,firmware-phandle: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + required only if there is no fsl,qe-firmware child node + + Points to a firmware node (see "QE Firmware Node" below) + that contains the firmware that should be uploaded for this QE. + The compatible property for the firmware node should say, + "fsl,qe-firmware". + + brg-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + the internal clock source frequency for baud-rate + generators in Hz. + + fsl,qe-num-snums: + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + description: | + define how many serial number(SNUM) the QE can use + for the threads. Use fsl,qe-snums instead to not only specify the + number of snums, but also their values. + +patternProperties: + '^muram@[a-f0-9]+$': + $ref: fsl,qe-muram.yaml + + '^interrupt-controller@[a-f0-9]+$': + $ref: fsl,qe-ic.yaml + + '^si@[a-f0-9]+$': + $ref: fsl,qe-si.yaml + + '^siram@[a-f0-9]+$': + $ref: fsl,qe-siram.yaml + +required: + - compatible + - reg + - bus-frequency + +allOf: + - $ref: /schemas/simple-bus.yaml# + +unevaluatedProperties: false + +examples: + - | + qe-bus@e0100000 { + compatible = "fsl,qe", "simple-bus"; + reg = <0xe0100000 0x480>; + ranges = <0 0xe0100000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + brg-frequency = <0>; + bus-frequency = <0x179a7b00>; + fsl,qe-snums = /bits/ 8 < + 0x04 0x05 0x0c 0x0d 0x14 0x15 0x1c 0x1d + 0x24 0x25 0x2c 0x2d 0x34 0x35 0x88 0x89 + 0x98 0x99 0xa8 0xa9 0xb8 0xb9 0xc8 0xc9 + 0xd8 0xd9 0xe8 0xe9>; + + interrupt-controller@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = <95 2 0 0 94 2 0 0>; + }; + + si@700 { + compatible = "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram@1000 { + compatible = "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + muram@10000 { + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0 0x00010000 0x0000c000>; + #address-cells = <1>; + #size-cells = <1>; + + data-only@0{ + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0 0xc000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml new file mode 100644 index 000000000000..64ffbf75dd9d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: High-Level Data Link Control(HDLC) + +description: HDLC part in Universal communication controllers (UCCs) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,ucc-hdlc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + + rx-clock-name: + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - pattern: "^brg([0-9]|1[0-6])$" + - pattern: "^clk([0-9]|1[0-9]|2[0-4])$" + + tx-clock-name: + $ref: /schemas/types.yaml#/definitions/string + oneOf: + - pattern: "^brg([0-9]|1[0-6])$" + - pattern: "^clk([0-9]|1[0-9]|2[0-4])$" + + fsl,tdm-interface: + $ref: /schemas/types.yaml#/definitions/flag + description: Specify that hdlc is based on tdm-interface + + fsl,rx-sync-clock: + $ref: /schemas/types.yaml#/definitions/string + description: rx-sync + enum: + - none + - rsync_pin + - brg9 + - brg10 + - brg11 + - brg13 + - brg14 + - brg15 + + fsl,tx-sync-clock: + $ref: /schemas/types.yaml#/definitions/string + description: tx-sync + enum: + - none + - tsync_pin + - brg9 + - brg10 + - brg11 + - brg13 + - brg14 + - brg15 + + fsl,tdm-framer-type: + $ref: /schemas/types.yaml#/definitions/string + description: required for tdm interface + enum: [e1, t1] + + fsl,tdm-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of TDM ID + + fsl,tx-timeslot-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + required for tdm interface. + time slot mask for TDM operation. Indicates which time + slots used for transmitting and receiving. + + fsl,rx-timeslot-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + required for tdm interface. + time slot mask for TDM operation. Indicates which time + slots used for transmitting and receiving. + + fsl,siram-entry-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + required for tdm interface + Must be 0,2,4...64. the number of TDM entry. + + fsl,tdm-internal-loopback: + $ref: /schemas/types.yaml#/definitions/flag + description: + optional for tdm interface + Internal loopback connecting on TDM layer. + + fsl,hmask: + $ref: /schemas/types.yaml#/definitions/uint16 + description: | + HDLC address recognition. Set to zero to disable + address filtering of packets: + fsl,hmask = /bits/ 16 <0x0000>; + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + communication@2000 { + compatible = "fsl,ucc-hdlc"; + reg = <0x2000 0x200>; + rx-clock-name = "clk8"; + tx-clock-name = "clk9"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot-mask = <0xfffffffe>; + fsl,rx-timeslot-mask = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + fsl,tdm-interface; + }; + + - | + communication@2000 { + compatible = "fsl,ucc-hdlc"; + reg = <0x2000 0x200>; + rx-clock-name = "brg1"; + tx-clock-name = "brg1"; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt deleted file mode 100644 index 6d2dd8a31482..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/network.txt +++ /dev/null @@ -1,130 +0,0 @@ -* Network - -Currently defined compatibles: -- fsl,cpm1-scc-enet -- fsl,cpm2-scc-enet -- fsl,cpm1-fec-enet -- fsl,cpm2-fcc-enet (third resource is GFEMR) -- fsl,qe-enet - -Example: - - ethernet@11300 { - compatible = "fsl,mpc8272-fcc-enet", - "fsl,cpm2-fcc-enet"; - reg = <11300 20 8400 100 11390 1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <20 8>; - interrupt-parent = <&PIC>; - phy-handle = <&PHY0>; - fsl,cpm-command = <12000300>; - }; - -* MDIO - -Currently defined compatibles: -fsl,pq1-fec-mdio (reg is same as first resource of FEC device) -fsl,cpm2-mdio-bitbang (reg is port C registers) - -Properties for fsl,cpm2-mdio-bitbang: -fsl,mdio-pin : pin of port C controlling mdio data -fsl,mdc-pin : pin of port C controlling mdio clock - -Example: - mdio@10d40 { - compatible = "fsl,mpc8272ads-mdio-bitbang", - "fsl,mpc8272-mdio-bitbang", - "fsl,cpm2-mdio-bitbang"; - reg = <10d40 14>; - #address-cells = <1>; - #size-cells = <0>; - fsl,mdio-pin = <12>; - fsl,mdc-pin = <13>; - }; - -* HDLC - -Currently defined compatibles: -- fsl,ucc-hdlc - -Properties for fsl,ucc-hdlc: -- rx-clock-name -- tx-clock-name - Usage: required - Value type: <string> - Definition : Must be "brg1"-"brg16" for internal clock source, - Must be "clk1"-"clk24" for external clock source. - -- fsl,tdm-interface - Usage: optional - Value type: <empty> - Definition : Specify that hdlc is based on tdm-interface - -The property below is dependent on fsl,tdm-interface: -- fsl,rx-sync-clock - Usage: required - Value type: <string> - Definition : Must be "none", "rsync_pin", "brg9-11" and "brg13-15". - -- fsl,tx-sync-clock - Usage: required - Value type: <string> - Definition : Must be "none", "tsync_pin", "brg9-11" and "brg13-15". - -- fsl,tdm-framer-type - Usage: required for tdm interface - Value type: <string> - Definition : "e1" or "t1".Now e1 and t1 are used, other framer types - are not supported. - -- fsl,tdm-id - Usage: required for tdm interface - Value type: <u32> - Definition : number of TDM ID - -- fsl,tx-timeslot-mask -- fsl,rx-timeslot-mask - Usage: required for tdm interface - Value type: <u32> - Definition : time slot mask for TDM operation. Indicates which time - slots used for transmitting and receiving. - -- fsl,siram-entry-id - Usage: required for tdm interface - Value type: <u32> - Definition : Must be 0,2,4...64. the number of TDM entry. - -- fsl,tdm-internal-loopback - usage: optional for tdm interface - value type: <empty> - Definition : Internal loopback connecting on TDM layer. -- fsl,hmask - usage: optional - Value type: <u16> - Definition: HDLC address recognition. Set to zero to disable - address filtering of packets: - fsl,hmask = /bits/ 16 <0x0000>; - -Example for tdm interface: - - ucc@2000 { - compatible = "fsl,ucc-hdlc"; - rx-clock-name = "clk8"; - tx-clock-name = "clk9"; - fsl,rx-sync-clock = "rsync_pin"; - fsl,tx-sync-clock = "tsync_pin"; - fsl,tx-timeslot-mask = <0xfffffffe>; - fsl,rx-timeslot-mask = <0xfffffffe>; - fsl,tdm-framer-type = "e1"; - fsl,tdm-id = <0>; - fsl,siram-entry-id = <0>; - fsl,tdm-interface; - }; - -Example for hdlc without tdm interface: - - ucc@2000 { - compatible = "fsl,ucc-hdlc"; - rx-clock-name = "brg1"; - tx-clock-name = "brg1"; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt deleted file mode 100644 index 05ec2a838c54..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe.txt +++ /dev/null @@ -1,178 +0,0 @@ -* Freescale QUICC Engine module (QE) -This represents qe module that is installed on PowerQUICC II Pro. - -NOTE: This is an interim binding; it should be updated to fit -in with the CPM binding later in this document. - -Basically, it is a bus of devices, that could act more or less -as a complete entity (UCC, USB etc ). All of them should be siblings on -the "root" qe node, using the common properties from there. -The description below applies to the qe of MPC8360 and -more nodes and properties would be extended in the future. - -i) Root QE device - -Required properties: -- compatible : should be "fsl,qe"; -- model : precise model of the QE, Can be "QE", "CPM", or "CPM2" -- reg : offset and length of the device registers. -- bus-frequency : the clock frequency for QUICC Engine. -- fsl,qe-num-riscs: define how many RISC engines the QE has. -- fsl,qe-snums: This property has to be specified as '/bits/ 8' value, - defining the array of serial number (SNUM) values for the virtual - threads. - -Optional properties: -- fsl,firmware-phandle: - Usage: required only if there is no fsl,qe-firmware child node - Value type: <phandle> - Definition: Points to a firmware node (see "QE Firmware Node" below) - that contains the firmware that should be uploaded for this QE. - The compatible property for the firmware node should say, - "fsl,qe-firmware". - -Recommended properties -- brg-frequency : the internal clock source frequency for baud-rate - generators in Hz. - -Deprecated properties -- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use - for the threads. Use fsl,qe-snums instead to not only specify the - number of snums, but also their values. - -Example: - qe@e0100000 { - #address-cells = <1>; - #size-cells = <1>; - #interrupt-cells = <2>; - compatible = "fsl,qe"; - ranges = <0 e0100000 00100000>; - reg = <e0100000 480>; - brg-frequency = <0>; - bus-frequency = <179A7B00>; - fsl,qe-snums = /bits/ 8 < - 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D - 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89 - 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9 - 0xD8 0xD9 0xE8 0xE9>; - } - -* Multi-User RAM (MURAM) - -Required properties: -- compatible : should be "fsl,qe-muram", "fsl,cpm-muram". -- mode : the could be "host" or "slave". -- ranges : Should be defined as specified in 1) to describe the - translation of MURAM addresses. -- data-only : sub-node which defines the address area under MURAM - bus that can be allocated as data/parameter - -Example: - - muram@10000 { - compatible = "fsl,qe-muram", "fsl,cpm-muram"; - ranges = <0 00010000 0000c000>; - - data-only@0{ - compatible = "fsl,qe-muram-data", - "fsl,cpm-muram-data"; - reg = <0 c000>; - }; - }; - -* Interrupt Controller (IC) - -Required properties: -- compatible : should be "fsl,qe-ic". -- reg : Address range of IC register set. -- interrupts : interrupts generated by the device. -- interrupt-controller : this device is a interrupt controller. - -Example: - - qeic: interrupt-controller@80 { - interrupt-controller; - compatible = "fsl,qe-ic"; - #address-cells = <0>; - #interrupt-cells = <1>; - reg = <0x80 0x80>; - interrupts = <95 2 0 0 94 2 0 0>; - }; - -* Serial Interface Block (SI) - -The SI manages the routing of eight TDM lines to the QE block serial drivers -, the MCC and the UCCs, for receive and transmit. - -Required properties: -- compatible : must be "fsl,<chip>-qe-si". For t1040, must contain - "fsl,t1040-qe-si". -- reg : Address range of SI register set. - -Example: - - si1: si@700 { - compatible = "fsl,t1040-qe-si"; - reg = <0x700 0x80>; - }; - -* Serial Interface Block RAM(SIRAM) - -store the routing entries of SI - -Required properties: -- compatible : should be "fsl,<chip>-qe-siram". For t1040, must contain - "fsl,t1040-qe-siram". -- reg : Address range of SI RAM. - -Example: - - siram1: siram@1000 { - compatible = "fsl,t1040-qe-siram"; - reg = <0x1000 0x800>; - }; - -* QE Firmware Node - -This node defines a firmware binary that is embedded in the device tree, for -the purpose of passing the firmware from bootloader to the kernel, or from -the hypervisor to the guest. - -The firmware node itself contains the firmware binary contents, a compatible -property, and any firmware-specific properties. The node should be placed -inside a QE node that needs it. Doing so eliminates the need for a -fsl,firmware-phandle property. Other QE nodes that need the same firmware -should define an fsl,firmware-phandle property that points to the firmware node -in the first QE node. - -The fsl,firmware property can be specified in the DTS (possibly using incbin) -or can be inserted by the boot loader at boot time. - -Required properties: - - compatible - Usage: required - Value type: <string> - Definition: A standard property. Specify a string that indicates what - kind of firmware it is. For QE, this should be "fsl,qe-firmware". - - - fsl,firmware - Usage: required - Value type: <prop-encoded-array>, encoded as an array of bytes - Definition: A standard property. This property contains the firmware - binary "blob". - -Example: - qe1@e0080000 { - compatible = "fsl,qe"; - qe_firmware:qe-firmware { - compatible = "fsl,qe-firmware"; - fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...]; - }; - ... - }; - - qe2@e0090000 { - compatible = "fsl,qe"; - fsl,firmware-phandle = <&qe_firmware>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml new file mode 100644 index 000000000000..8dce75bebff9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,bman-portal.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,bman-portal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager Portals + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + QorIQ DPAA Buffer Manager Portal + + Portals are memory mapped interfaces to BMan that allow low-latency, lock-less + interaction by software running on processor cores, accelerators and network + interfaces with the BMan + +properties: + compatible: + oneOf: + - const: fsl,bman-portal + - items: + - enum: + - fsl,bman-portal-1.0.0 + - fsl,ls1043a-bmap-portal + - fsl,ls1046a-bmap-portal + - const: fsl,bman-portal + reg: + items: + - description: the cache-enabled region of the portal + - description: the cache-inhibited region of the portal + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bman-portal@0 { + compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; + reg = <0x0 0x4000>, <0x100000 0x1000>; + interrupts = <105 IRQ_TYPE_EDGE_FALLING 0 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml new file mode 100644 index 000000000000..e6f468264b8d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,bman.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,bman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Buffer Manager + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). + BMan supports hardware allocation and deallocation of buffers belonging to + pools originally created by software with configurable depletion thresholds. + This binding covers the CCSR space programming model + +properties: + compatible: + oneOf: + - const: fsl,bman + - items: + - enum: + - fsl,ls1043a-bman + - fsl,ls1046a-bman + - const: fsl,bman + + reg: + items: + - description: | + Registers region within the CCSR address space + + The BMan revision information is located in the BMAN_IP_REV_1/2 + registers which are located at offsets 0xbf8 and 0xbfc + + interrupts: + items: + - description: The error interrupt + + memory-region: + minItems: 1 + maxItems: 2 + description: + List of phandles referencing the BMan private memory + nodes (described below). The bman-fqd node must be + first followed by bman-pfdr node. Only used on ARM + + Devices connected to a BMan instance via Direct Connect Portals (DCP) must link + to the respective BMan instance + + fsl,bman-portals: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref fsl,bman-port.yaml + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + See pamu.txt, PAMU property used for dynamic LIODN assignment + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + bman@31a000 { + compatible = "fsl,bman"; + reg = <0x31a000 0x1000>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 2>; + fsl,liodn = <0x17>; + fsl,bman-portals = <&bportals>; + memory-region = <&bman_fbpr>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml index ce1a6505eb51..3fb0534ea597 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape Device Configuration Unit maintainers: - Shawn Guo <shawnguo@kernel.org> - - Li Yang <leoyang.li@nxp.com> description: | DCFG is the device configuration unit, that provides general purpose diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml index a6a511b00a12..2958ef45b3e9 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-scfg.yaml @@ -8,7 +8,6 @@ title: Freescale Layerscape Supplemental Configuration Unit maintainers: - Shawn Guo <shawnguo@kernel.org> - - Li Yang <leoyang.li@nxp.com> description: | SCFG is the supplemental configuration unit, that provides SoC specific @@ -24,6 +23,9 @@ properties: - fsl,ls1028a-scfg - fsl,ls1043a-scfg - fsl,ls1046a-scfg + - fsl,ls1088a-isc + - fsl,ls2080a-isc + - fsl,lx2160a-isc - const: syscon reg: diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml new file mode 100644 index 000000000000..31295be91013 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas//soc/fsl/fsl,ls1028a-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape Reset Registers Module + +maintainers: + - Frank Li + +description: + Reset Module includes chip reset, service processor control and Reset Control + Word (RCW) status. + +properties: + $nodename: + pattern: "^syscon@[0-9a-f]+$" + + compatible: + items: + - enum: + - fsl,ls1028a-reset + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + little-endian: true + + reboot: + $ref: /schemas/power/reset/syscon-reboot.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - reboot + +additionalProperties: false + +examples: + - | + syscon@1e60000 { + compatible = "fsl,ls1028a-reset", "syscon", "simple-mfd"; + reg = <0x1e60000 0x10000>; + little-endian; + + reboot { + compatible = "syscon-reboot"; + offset = <0>; + mask = <0x02>; + }; + }; + diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml new file mode 100644 index 000000000000..de0b4ae740ff --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-fqd.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-fqd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QMan Private Memory Nodes + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + QMan requires two contiguous range of physical memory used for the backing store + for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). + This memory is reserved/allocated as a node under the /reserved-memory node. + + BMan requires a contiguous range of physical memory used for the backing store + for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as + a node under the /reserved-memory node. + + The QMan FQD memory node must be named "qman-fqd" + The QMan PFDR memory node must be named "qman-pfdr" + The BMan FBPR memory node must be named "bman-fbpr" + + The following constraints are relevant to the FQD and PFDR private memory: + - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to + 1 GiB + - The alignment must be a muliptle of the memory size + + The size of the FQD and PFDP must be chosen by observing the hardware features + configured via the Reset Configuration Word (RCW) and that are relevant to a + specific board (e.g. number of MAC(s) pinned-out, number of offline/host command + FMan ports, etc.). The size configured in the DT must reflect the hardware + capabilities and not the specific needs of an application + + For additional details about reserved memory regions see + reserved-memory/reserved-memory.yaml in dtschema project. + +properties: + $nodename: + pattern: '^(qman-fqd|qman-pfdr|bman-fbpr)+$' + + compatible: + enum: + - fsl,qman-fqd + - fsl,qman-pfdr + - fsl,bman-fbpr + +required: + - compatible + +allOf: + - $ref: reserved-memory.yaml + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + qman-fqd { + compatible = "shared-dma-pool"; + size = <0 0x400000>; + alignment = <0 0x400000>; + no-map; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml new file mode 100644 index 000000000000..e459fec02ba8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman-portal.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman-portal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager Portals + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + Portals are memory mapped interfaces to QMan that allow low-latency, lock-less + interaction by software running on processor cores, accelerators and network + interfaces with the QMan + +properties: + compatible: + oneOf: + - const: fsl,qman-portal + - items: + - enum: + - fsl,ls1043-qman-portal + - fsl,ls1046-qman-portal + - fsl,qman-portal-1.2.0 + - const: fsl,qman-portal + + reg: + items: + - description: the cache-enabled region of the portal + - description: the cache-inhibited region of the portal + + interrupts: + maxItems: 1 + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + description: See pamu.txt. Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN + (FLIODN) + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: See pamu.txt. + + fsl,qman-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: qman channel id. + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The hardware index of the channel. This can also be + determined by dividing any of the channel's 8 work queue + IDs by 8 + + In addition to these properties the qman-portals should have sub-nodes to + represent the HW devices/portals that are connected to the software portal + described here + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +patternProperties: + '^(fman0|fman1|pme|crypto)+$': + type: object + properties: + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + description: See pamu.txt, PAMU property used for dynamic LIODN assignment + + dev-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the particular hardware device that this + portal is connected to. + + additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + qman-portal@0 { + compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; + reg = <0 0x4000>, <0x100000 0x1000>; + interrupts = <104 IRQ_TYPE_EDGE_FALLING 0 0>; + fsl,liodn = <1 2>; + fsl,qman-channel-id = <0>; + + fman0 { + fsl,liodn = <0x21>; + dev-handle = <&fman0>; + }; + + fman1 { + fsl,liodn = <0xa1>; + dev-handle = <&fman1>; + }; + + crypto { + fsl,liodn = <0x41 0x66>; + dev-handle = <&crypto>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml new file mode 100644 index 000000000000..501f06e190c4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,qman.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,qman.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QorIQ DPAA Queue Manager + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan + supports queuing and QoS scheduling of frames to CPUs, network interfaces and + DPAA logic modules, maintains packet ordering within flows. Besides providing + flow-level queuing, is also responsible for congestion management functions such + as RED/WRED, congestion notifications and tail discards. This binding covers the + CCSR space programming model + +properties: + compatible: + oneOf: + - const: fsl,qman + - items: + - enum: + - fsl,ls1043a-qman + - fsl,ls1046a-qman + - const: fsl,qman + reg: + items: + - description: | + Registers region within the CCSR address space + + The QMan revision information is located in the QMAN_IP_REV_1/2 + registers which are located at offsets 0xbf8 and 0xbfc + + interrupts: + items: + - description: The error interrupt + + fsl,qman-portals: + $ref: /schemas/types.yaml#/definitions/phandle + description: ref fsl,qman-port.yaml + + fsl,liodn: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + See pamu.txt, PAMU property used for static LIODN assignment + + fsl,iommu-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + See pamu.txt, PAMU property used for dynamic LIODN assignment + + clocks: + maxItems: 1 + description: + Reference input clock. Its frequency is half of the platform clock + + memory-region: + maxItems: 2 + description: + List of phandles referencing the QMan private memory nodes (described + below). The qman-fqd node must be first followed by qman-pfdr node. + Only used on ARM Devices connected to a QMan instance via Direct Connect + Portals (DCP) must link to the respective QMan instance. + + fsl,qman: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of phandle and DCP index pairs, to the QMan instance + to which this device is connected via the DCP + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + qman: qman@318000 { + compatible = "fsl,qman"; + reg = <0x318000 0x1000>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING 1 3>; + fsl,liodn = <0x16>; + fsl,qman-portals = <&qportals>; + memory-region = <&qman_fqd &qman_pfdr>; + clocks = <&platform_pll 1>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,rcpm.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,rcpm.yaml new file mode 100644 index 000000000000..03d71ab930d7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,rcpm.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,rcpm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Run Control and Power Management + +description: + The RCPM performs all device-level tasks associated with device run control + and power management. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,p2041-rcpm + - fsl,p3041-rcpm + - fsl,p4080-rcpm + - fsl,p5020-rcpm + - fsl,p5040-rcpm + - const: fsl,qoriq-rcpm-1.0 + - items: + - enum: + - fsl,b4420-rcpm + - fsl,b4860-rcpm + - fsl,t4240-rcpm + - const: fsl,qoriq-rcpm-2.0 + - items: + - enum: + - fsl,t1040-rcpm + - const: fsl,qoriq-rcpm-2.1 + - items: + - enum: + - fsl,ls1012a-rcpm + - fsl,ls1021a-rcpm + - fsl,ls1028a-rcpm + - fsl,ls1043a-rcpm + - fsl,ls1046a-rcpm + - fsl,ls1088a-rcpm + - fsl,ls208xa-rcpm + - fsl,lx2160a-rcpm + - const: fsl,qoriq-rcpm-2.1+ + + reg: + maxItems: 1 + + "#fsl,rcpm-wakeup-cells": + description: | + The number of IPPDEXPCR register cells in the + fsl,rcpm-wakeup property. + + Freescale RCPM Wakeup Source Device Tree Bindings + + Required fsl,rcpm-wakeup property should be added to a device node if + the device can be used as a wakeup source. + + fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR + register cells. The number of IPPDEXPCR register cells is defined in + "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is + the bit mask that should be set in IPPDEXPCR0, and the second register + cell is for IPPDEXPCR1, and so on. + + Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a + mechanism for keeping certain blocks awake during STANDBY and MEM, in + order to use them as wake-up sources. + + little-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: + RCPM register block is Little Endian. Without it RCPM + will be Big Endian (default case). + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + global-utilities@e2000 { + compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; + reg = <0xe2000 0x1000>; + #fsl,rcpm-wakeup-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt deleted file mode 100644 index 5a34f3ab7bea..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt +++ /dev/null @@ -1,134 +0,0 @@ -QorIQ DPAA Queue Manager Portals Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Portal - - Example - -QMan Portal Node - -Portals are memory mapped interfaces to QMan that allow low-latency, lock-less -interaction by software running on processor cores, accelerators and network -interfaces with the QMan - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,qman-portal-<hardware revision>" - May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Two regions. The first is the cache-enabled region of - the portal. The second is the cache-inhibited region of - the portal - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN - (FLIODN) - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- cell-index - Usage: Required - Value type: <u32> - Definition: The hardware index of the channel. This can also be - determined by dividing any of the channel's 8 work queue - IDs by 8 - -In addition to these properties the qman-portals should have sub-nodes to -represent the HW devices/portals that are connected to the software portal -described here - -The currently supported sub-nodes are: - * fman0 - * fman1 - * pme - * crypto - -These subnodes should have the following properties: - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - -- dev-handle - Usage: Required - Value type: <phandle> - Definition: The phandle to the particular hardware device that this - portal is connected to. - -EXAMPLE - -The example below shows a (P4080) QMan portals container/bus node with two portals - - qman-portals@ff4200000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0xf 0xf4200000 0x200000>; - - qman-portal@0 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0 0x4000>, <0x100000 0x1000>; - interrupts = <104 2 0 0>; - fsl,liodn = <1 2>; - fsl,qman-channel-id = <0>; - - fman0 { - fsl,liodn = <0x21>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa1>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x41 0x66>; - dev-handle = <&crypto>; - }; - }; - qman-portal@4000 { - compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <106 2 0 0>; - fsl,liodn = <3 4>; - cell-index = <1>; - - fman0 { - fsl,liodn = <0x22>; - dev-handle = <&fman0>; - }; - fman1 { - fsl,liodn = <0xa2>; - dev-handle = <&fman1>; - }; - crypto { - fsl,liodn = <0x42 0x67>; - dev-handle = <&crypto>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt b/Documentation/devicetree/bindings/soc/fsl/qman.txt deleted file mode 100644 index ee96afd2af72..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/qman.txt +++ /dev/null @@ -1,187 +0,0 @@ -QorIQ DPAA Queue Manager Device Tree Binding - -Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. - -CONTENTS - - - QMan Node - - QMan Private Memory Nodes - - Example - -QMan Node - -The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan -supports queuing and QoS scheduling of frames to CPUs, network interfaces and -DPAA logic modules, maintains packet ordering within flows. Besides providing -flow-level queuing, is also responsible for congestion management functions such -as RED/WRED, congestion notifications and tail discards. This binding covers the -CCSR space programming model - -PROPERTIES - -- compatible - Usage: Required - Value type: <stringlist> - Definition: Must include "fsl,qman" - May include "fsl,<SoC>-qman" - -- reg - Usage: Required - Value type: <prop-encoded-array> - Definition: Registers region within the CCSR address space - -The QMan revision information is located in the QMAN_IP_REV_1/2 registers which -are located at offsets 0xbf8 and 0xbfc - -- interrupts - Usage: Required - Value type: <prop-encoded-array> - Definition: Standard property. The error interrupt - -- fsl,qman-portals - Usage: Required - Value type: <phandle> - Definition: Phandle to this QMan instance's portals - -- fsl,liodn - Usage: See pamu.txt - Value type: <prop-encoded-array> - Definition: PAMU property used for static LIODN assignment - -- fsl,iommu-parent - Usage: See pamu.txt - Value type: <phandle> - Definition: PAMU property used for dynamic LIODN assignment - - For additional details about the PAMU/LIODN binding(s) see pamu.txt - -- clocks - Usage: See clock-bindings.txt and qoriq-clock.txt - Value type: <prop-encoded-array> - Definition: Reference input clock. Its frequency is half of the - platform clock -- memory-regions - Usage: Required for ARM - Value type: <phandle array> - Definition: List of phandles referencing the QMan private memory - nodes (described below). The qman-fqd node must be - first followed by qman-pfdr node. Only used on ARM - -Devices connected to a QMan instance via Direct Connect Portals (DCP) must link -to the respective QMan instance - -- fsl,qman - Usage: Required - Value type: <prop-encoded-array> - Description: List of phandle and DCP index pairs, to the QMan instance - to which this device is connected via the DCP - -QMan Private Memory Nodes - -QMan requires two contiguous range of physical memory used for the backing store -for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). -This memory is reserved/allocated as a node under the /reserved-memory node. - -For additional details about reserved memory regions see reserved-memory.txt - -The QMan FQD memory node must be named "qman-fqd" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,qman-fqd" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The QMan PFDR memory node must be named "qman-pfdr" - -PROPERTIES - -- compatible - Usage: required - Value type: <stringlist> - Definition: PPC platforms: Must include "fsl,qman-pfdr" - ARM platforms: Must include "shared-dma-pool" - as well as the "no-map" property - -The following constraints are relevant to the FQD and PFDR private memory: - - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to - 1 GiB - - The alignment must be a muliptle of the memory size - -The size of the FQD and PFDP must be chosen by observing the hardware features -configured via the Reset Configuration Word (RCW) and that are relevant to a -specific board (e.g. number of MAC(s) pinned-out, number of offline/host command -FMan ports, etc.). The size configured in the DT must reflect the hardware -capabilities and not the specific needs of an application - -For additional details about reserved memory regions see reserved-memory.txt - -EXAMPLE - -The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - qman_fqd: qman-fqd { - compatible = "shared-dma-pool"; - size = <0 0x400000>; - alignment = <0 0x400000>; - no-map; - }; - qman_pfdr: qman-pfdr { - compatible = "shared-dma-pool"; - size = <0 0x2000000>; - alignment = <0 0x2000000>; - no-map; - }; - }; - -The example below shows a (P4080) QMan CCSR-space node - - qportals: qman-portals@ff4200000 { - ... - }; - - clockgen: global-utilities@e1000 { - ... - sysclk: sysclk { - ... - }; - ... - platform_pll: platform-pll@c00 { - #clock-cells = <1>; - reg = <0xc00 0x4>; - compatible = "fsl,qoriq-platform-pll-1.0"; - clocks = <&sysclk>; - clock-output-names = "platform-pll", "platform-pll-div2"; - }; - ... - }; - - crypto@300000 { - ... - fsl,qman = <&qman, 2>; - ... - }; - - qman: qman@318000 { - compatible = "fsl,qman"; - reg = <0x318000 0x1000>; - interrupts = <16 2 1 3> - fsl,liodn = <0x16>; - fsl,qman-portals = <&qportals>; - memory-region = <&qman_fqd &qman_pfdr>; - clocks = <&platform_pll 1>; - }; - - fman@400000 { - ... - fsl,qman = <&qman, 0>; - ... - }; diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt deleted file mode 100644 index 5a33619d881d..000000000000 --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt +++ /dev/null @@ -1,69 +0,0 @@ -* Run Control and Power Management -------------------------------------------- -The RCPM performs all device-level tasks associated with device run control -and power management. - -Required properites: - - reg : Offset and length of the register set of the RCPM block. - - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the - fsl,rcpm-wakeup property. - - compatible : Must contain a chip-specific RCPM block compatible string - and (if applicable) may contain a chassis-version RCPM compatible - string. Chip-specific strings are of the form "fsl,<chip>-rcpm", - such as: - * "fsl,p2041-rcpm" - * "fsl,p5020-rcpm" - * "fsl,t4240-rcpm" - - Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>", - such as: - * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm - * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm - * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm - * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm - -All references to "1.0" and "2.0" refer to the QorIQ chassis version to -which the chip complies. -Chassis Version Example Chips ---------------- ------------------------------- -1.0 p4080, p5020, p5040, p2041, p3041 -2.0 t4240, b4860, b4420 -2.1 t1040, -2.1+ ls1021a, ls1012a, ls1043a, ls1046a - -Optional properties: - - little-endian : RCPM register block is Little Endian. Without it RCPM - will be Big Endian (default case). - -Example: -The RCPM node for T4240: - rcpm: global-utilities@e2000 { - compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; - reg = <0xe2000 0x1000>; - #fsl,rcpm-wakeup-cells = <2>; - }; - -* Freescale RCPM Wakeup Source Device Tree Bindings -------------------------------------------- -Required fsl,rcpm-wakeup property should be added to a device node if the device -can be used as a wakeup source. - - - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR - register cells. The number of IPPDEXPCR register cells is defined in - "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is - the bit mask that should be set in IPPDEXPCR0, and the second register - cell is for IPPDEXPCR1, and so on. - - Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a - mechanism for keeping certain blocks awake during STANDBY and MEM, in - order to use them as wake-up sources. - -Example: - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sysclk>; - clock-names = "ipg"; - fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>; - }; |