diff options
Diffstat (limited to 'Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml | 90 |
1 files changed, 66 insertions, 24 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 5dd209206e88..8b6e8fc009db 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -8,41 +8,28 @@ title: Peripheral-specific properties for a SPI bus. description: Many SPI controllers need to add properties to peripheral devices. They could - be common properties like spi-max-frequency, spi-cpha, etc. or they could be - controller specific like delay in clock or data lines, etc. These properties - need to be defined in the peripheral node because they are per-peripheral and - there can be multiple peripherals attached to a controller. All those - properties are listed here. The controller specific properties should go in - their own separate schema that should be referenced from here. + be common properties like spi-max-frequency, spi-cs-high, etc. or they could + be controller specific like delay in clock or data lines, etc. These + properties need to be defined in the peripheral node because they are + per-peripheral and there can be multiple peripherals attached to a + controller. All those properties are listed here. The controller specific + properties should go in their own separate schema that should be referenced + from here. maintainers: - - Pratyush Yadav <p.yadav@ti.com> + - Mark Brown <broonie@kernel.org> properties: reg: minItems: 1 maxItems: 256 items: - minimum: 0 - maximum: 256 + items: + - minimum: 0 + maximum: 256 description: Chip select used by the device. - spi-3wire: - $ref: /schemas/types.yaml#/definitions/flag - description: - The device requires 3-wire mode. - - spi-cpha: - $ref: /schemas/types.yaml#/definitions/flag - description: - The device requires shifted clock phase (CPHA) mode. - - spi-cpol: - $ref: /schemas/types.yaml#/definitions/flag - description: - The device requires inverse clock polarity (CPOL) mode. - spi-cs-high: $ref: /schemas/types.yaml#/definitions/flag description: @@ -58,6 +45,21 @@ properties: description: Maximum SPI clocking speed of the device in Hz. + spi-cs-setup-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller after CS is + asserted. + + spi-cs-hold-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller before CS is + de-asserted. + + spi-cs-inactive-delay-ns: + description: + Delay in nanoseconds to be introduced by the controller after CS is + de-asserted. + spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. @@ -70,6 +72,11 @@ properties: description: Delay, in microseconds, after a read transfer. + rx-sample-delay-ns: + description: SPI Rx sample delay offset, unit is nanoseconds. + The delay from the default sample time before the actual + sample of the rxd input signal occurs. + spi-tx-bus-width: description: Bus width to the SPI bus used for write transfers. @@ -82,8 +89,43 @@ properties: description: Delay, in microseconds, after a write transfer. + stacked-memories: + description: Several SPI memories can be wired in stacked mode. + This basically means that either a device features several chip + selects, or that different devices must be seen as a single + bigger chip. This basically doubles (or more) the total address + space with only a single additional wire, while still needing + to repeat the commands when crossing a chip boundary. The size of + each chip should be provided as members of the array. + $ref: /schemas/types.yaml#/definitions/uint64-array + minItems: 2 + maxItems: 4 + + parallel-memories: + description: Several SPI memories can be wired in parallel mode. + The devices are physically on a different buses but will always + act synchronously as each data word is spread across the + different memories (eg. even bits are stored in one memory, odd + bits in the other). This basically doubles the address space and + the throughput while greatly complexifying the wiring because as + many busses as devices must be wired. The size of each chip should + be provided as members of the array. + $ref: /schemas/types.yaml#/definitions/uint64-array + minItems: 2 + maxItems: 4 + + st,spi-midi-ns: + deprecated: true + description: | + Only for STM32H7, (Master Inter-Data Idleness) minimum time + delay in nanoseconds inserted between two consecutive data frames. + # The controller specific properties go here. allOf: + - $ref: arm,pl022-peripheral-props.yaml# - $ref: cdns,qspi-nor-peripheral-props.yaml# + - $ref: fsl,dspi-peripheral-props.yaml# + - $ref: samsung,spi-peripheral-props.yaml# + - $ref: nvidia,tegra210-quad-peripheral-props.yaml# additionalProperties: true |