diff options
Diffstat (limited to 'arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts')
| -rw-r--r-- | arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 126 |
1 files changed, 126 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts new file mode 100644 index 000000000000..a351a97d257e --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for Netgear WG302v2 based on IXP422BB + * Derived from boardfiles written by Imre Kaloz + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Netgear WG302 v1"; + compatible = "netgear,wg302v1", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB SDRAM according to boot arguments */ + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + /* The RedBoot comes up in 9600 baud so let's keep this */ + bootargs = "console=ttyS0,9600n8"; + stdout-path = "uart1:9600n8"; + }; + + aliases { + /* These are switched around */ + serial0 = &uart1; + }; + + leds { + compatible = "gpio-leds"; + test_led: led-test { + color = <LED_COLOR_ID_AMBER>; + function = "test"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + wlan_led: led-wlan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "phy0tx"; + }; + }; + + gpio_keys { + /* RESET is on GPIO13 which can't fire interrupts */ + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-reset { + linux,code = <KEY_RESTART>; + label = "reset"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 64 0x20000 sized blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + fis-index-block = <0x3f>; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + /* + * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c) + * We have slots (IDSEL) 1 and 2 with one assigned IRQ + * each handling all IRQs. + */ + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 8 */ + <0x0800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 8 */ + <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ + <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ + /* IDSEL 2 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ + }; + + ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy30>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy30: ethernet-phy@30 { + reg = <30>; + }; + }; + }; + }; +}; |