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Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-ipq4019.dtsi273
1 files changed, 0 insertions, 273 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
deleted file mode 100644
index 4b7d97275c62..000000000000
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/dts-v1/;
-
-#include "skeleton.dtsi"
-#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- model = "Qualcomm Technologies, Inc. IPQ4019";
- compatible = "qcom,ipq4019";
- interrupt-parent = <&intc>;
-
- aliases {
- spi0 = &spi_0;
- i2c0 = &i2c_0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- enable-method = "qcom,kpss-acc-v1";
- qcom,acc = <&acc0>;
- qcom,saw = <&saw0>;
- reg = <0x0>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
- operating-points = <
- /* kHz uV (fixed) */
- 48000 1100000
- 200000 1100000
- 500000 1100000
- 666000 1100000
- >;
- clock-latency = <256000>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- enable-method = "qcom,kpss-acc-v1";
- qcom,acc = <&acc1>;
- qcom,saw = <&saw1>;
- reg = <0x1>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
- };
-
- cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- enable-method = "qcom,kpss-acc-v1";
- qcom,acc = <&acc2>;
- qcom,saw = <&saw2>;
- reg = <0x2>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
- };
-
- cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- enable-method = "qcom,kpss-acc-v1";
- qcom,acc = <&acc3>;
- qcom,saw = <&saw3>;
- reg = <0x3>;
- clocks = <&gcc GCC_APPS_CLK_SRC>;
- clock-frequency = <0>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- clocks {
- sleep_clk: sleep_clk {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- #clock-cells = <0>;
- };
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- compatible = "simple-bus";
-
- intc: interrupt-controller@b000000 {
- compatible = "qcom,msm-qgic2";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0x0b000000 0x1000>,
- <0x0b002000 0x1000>;
- };
-
- gcc: clock-controller@1800000 {
- compatible = "qcom,gcc-ipq4019";
- #clock-cells = <1>;
- #reset-cells = <1>;
- reg = <0x1800000 0x60000>;
- };
-
- tlmm: pinctrl@0x01000000 {
- compatible = "qcom,ipq4019-pinctrl";
- reg = <0x01000000 0x300000>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <0 208 0>;
- };
-
- blsp_dma: dma@7884000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x07884000 0x23000>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <0>;
- status = "disabled";
- };
-
- spi_0: spi@78b5000 {
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x78b5000 0x600>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c_0: i2c@78b7000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x78b7000 0x600>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
-
- cryptobam: dma@8e04000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x08e04000 0x20000>;
- interrupts = <GIC_SPI 207 0>;
- clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
- clock-names = "bam_clk";
- #dma-cells = <1>;
- qcom,ee = <1>;
- qcom,controlled-remotely;
- status = "disabled";
- };
-
- crypto@8e3a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0x08e3a000 0x6000>;
- clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
- <&gcc GCC_CRYPTO_AXI_CLK>,
- <&gcc GCC_CRYPTO_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- acc0: clock-controller@b088000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
- };
-
- acc1: clock-controller@b098000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
- };
-
- acc2: clock-controller@b0a8000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
- };
-
- acc3: clock-controller@b0b8000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
- };
-
- saw0: regulator@b089000 {
- compatible = "qcom,saw2";
- reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
- regulator;
- };
-
- saw1: regulator@b099000 {
- compatible = "qcom,saw2";
- reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
- regulator;
- };
-
- saw2: regulator@b0a9000 {
- compatible = "qcom,saw2";
- reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
- regulator;
- };
-
- saw3: regulator@b0b9000 {
- compatible = "qcom,saw2";
- reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
- regulator;
- };
-
- serial@78af000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x78af000 0x200>;
- interrupts = <0 107 0>;
- status = "disabled";
- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- dmas = <&blsp_dma 1>, <&blsp_dma 0>;
- dma-names = "rx", "tx";
- };
-
- serial@78b0000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0x78b0000 0x200>;
- interrupts = <0 108 0>;
- status = "disabled";
- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- dmas = <&blsp_dma 3>, <&blsp_dma 2>;
- dma-names = "rx", "tx";
- };
-
- watchdog@b017000 {
- compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
- reg = <0xb017000 0x40>;
- clocks = <&sleep_clk>;
- timeout-sec = <10>;
- status = "disabled";
- };
-
- restart@4ab000 {
- compatible = "qcom,pshold";
- reg = <0x4ab000 0x4>;
- };
- };
-};
generated by cgit (git 2.34.1) at 2025-12-27 13:22:54 +0000