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Diffstat (limited to 'arch/arm/boot/dts/qcom/qcom-apq8064.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom/qcom-apq8064.dtsi475
1 files changed, 154 insertions, 321 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 516f0d2495e2..09062b2ad8ba 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -36,58 +36,58 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <2>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <3>;
- next-level-cache = <&L2>;
+ next-level-cache = <&l2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
- cpu-idle-states = <&CPU_SPC>;
+ cpu-idle-states = <&cpu_spc>;
};
- L2: l2-cache {
+ l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
- CPU_SPC: spc {
+ cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <400>;
@@ -190,7 +190,7 @@
cpu-pmu {
compatible = "qcom,krait-pmu";
- interrupts = <1 10 0x304>;
+ interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
@@ -213,12 +213,6 @@
};
};
- sfpb_mutex: hwmutex {
- compatible = "qcom,sfpb-mutex";
- syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
- #hwlock-cells = <1>;
- };
-
smem {
compatible = "qcom,smem";
memory-region = <&smem_region>;
@@ -244,7 +238,7 @@
modem_smsm: modem@1 {
reg = <1>;
- interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -252,7 +246,7 @@
q6_smsm: q6@2 {
reg = <2>;
- interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -260,7 +254,7 @@
wcnss_smsm: wcnss@3 {
reg = <3>;
- interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -268,7 +262,7 @@
dsps_smsm: dsps@4 {
reg = <4>;
- interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -284,21 +278,38 @@
};
};
+ replicator {
+ compatible = "arm,coresight-static-replicator";
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
- /*
- * These channels from the ADC are simply hardware monitors.
- * That is why the ADC is referred to as "HKADC" - HouseKeeping
- * ADC.
- */
- iio-hwmon {
- compatible = "iio-hwmon";
- io-channels = <&xoadc 0x00 0x01>, /* Battery */
- <&xoadc 0x00 0x02>, /* DC in (charger) */
- <&xoadc 0x00 0x04>, /* VPH the main system voltage */
- <&xoadc 0x00 0x0b>, /* Die temperature */
- <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
- <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
- <&xoadc 0x00 0x0e>; /* Charger temperature */
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint = <&tpiu_in>;
+ };
+ };
+ };
};
soc: soc {
@@ -316,20 +327,22 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&ps_hold>;
+ pinctrl-0 = <&ps_hold_default_state>;
};
- sfpb_wrapper_mutex: syscon@1200000 {
- compatible = "syscon";
- reg = <0x01200000 0x8000>;
+ sfpb_mutex: hwmutex@1200600 {
+ compatible = "qcom,sfpb-mutex";
+ reg = <0x01200600 0x100>;
+ #hwlock-cells = <1>;
};
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
@@ -338,11 +351,13 @@
timer@200a000 {
compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
"qcom,msm-timer";
- interrupts = <1 1 0x301>,
- <1 2 0x301>,
- <1 3 0x301>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <27000000>;
+ clocks = <&sleep_clk>;
+ clock-names = "sleep";
cpu-offset = <0x80000>;
};
@@ -382,32 +397,48 @@
#clock-cells = <0>;
};
- saw0: power-controller@2089000 {
+ saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw0_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw1: power-controller@2099000 {
+ saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw1_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw2: power-controller@20a9000 {
+ saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw2_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- saw3: power-controller@20b9000 {
+ saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw3_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
- sps_sic_non_secure: sps-sic-non-secure@12100000 {
- compatible = "syscon";
+ sps_sic_non_secure: interrupt-controller@12100000 {
+ compatible = "qcom,apq8064-sps-sic", "syscon";
reg = <0x12100000 0x10000>;
};
@@ -428,7 +459,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12450000 0x100>,
<0x12400000 0x03>;
- interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -436,11 +467,11 @@
gsbi1_i2c: i2c@12460000 {
compatible = "qcom,i2c-qup-v1.1.1";
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-1 = <&i2c1_pins_sleep>;
+ pinctrl-0 = <&i2c1_default_state>;
+ pinctrl-1 = <&i2c1_sleep_state>;
pinctrl-names = "default", "sleep";
reg = <0x12460000 0x1000>;
- interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@@ -466,10 +497,10 @@
gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-1 = <&i2c2_pins_sleep>;
+ pinctrl-0 = <&i2c2_default_state>;
+ pinctrl-1 = <&i2c2_sleep_state>;
pinctrl-names = "default", "sleep";
- interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
@@ -490,8 +521,8 @@
ranges;
gsbi3_i2c: i2c@16280000 {
compatible = "qcom,i2c-qup-v1.1.1";
- pinctrl-0 = <&i2c3_pins>;
- pinctrl-1 = <&i2c3_pins_sleep>;
+ pinctrl-0 = <&i2c3_default_state>;
+ pinctrl-1 = <&i2c3_sleep_state>;
pinctrl-names = "default", "sleep";
reg = <0x16280000 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
@@ -529,8 +560,8 @@
gsbi4_i2c: i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1";
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-1 = <&i2c4_pins_sleep>;
+ pinctrl-0 = <&i2c4_default_state>;
+ pinctrl-1 = <&i2c4_sleep_state>;
pinctrl-names = "default", "sleep";
reg = <0x16380000 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
@@ -556,7 +587,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x100>,
<0x1a200000 0x03>;
- interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -565,9 +596,9 @@
gsbi5_spi: spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
- interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-0 = <&spi5_default>;
- pinctrl-1 = <&spi5_sleep>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&spi5_default_state>;
+ pinctrl-1 = <&spi5_sleep_state>;
pinctrl-names = "default", "sleep";
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
@@ -592,7 +623,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16540000 0x100>,
<0x16500000 0x03>;
- interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -600,8 +631,8 @@
gsbi6_i2c: i2c@16580000 {
compatible = "qcom,i2c-qup-v1.1.1";
- pinctrl-0 = <&i2c6_pins>;
- pinctrl-1 = <&i2c6_pins_sleep>;
+ pinctrl-0 = <&i2c6_default_state>;
+ pinctrl-1 = <&i2c6_sleep_state>;
pinctrl-names = "default", "sleep";
reg = <0x16580000 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
@@ -628,7 +659,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>,
<0x16600000 0x1000>;
- interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -636,8 +667,8 @@
gsbi7_i2c: i2c@16680000 {
compatible = "qcom,i2c-qup-v1.1.1";
- pinctrl-0 = <&i2c7_pins>;
- pinctrl-1 = <&i2c7_pins_sleep>;
+ pinctrl-0 = <&i2c7_default_state>;
+ pinctrl-1 = <&i2c7_sleep_state>;
pinctrl-names = "default", "sleep";
reg = <0x16680000 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -655,145 +686,28 @@
clock-names = "core";
};
- ssbi@c00000 {
+ ssbi2: ssbi@c00000 {
compatible = "qcom,ssbi";
reg = <0x00c00000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pm8821: pmic {
- compatible = "qcom,pm8821";
- interrupt-parent = <&tlmm_pinmux>;
- interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8821_mpps: mpps@50 {
- compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
- reg = <0x50>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pm8821_mpps 0 0 4>;
- };
- };
};
- ssbi@500000 {
+ ssbi: ssbi@500000 {
compatible = "qcom,ssbi";
reg = <0x00500000 0x1000>;
qcom,controller-type = "pmic-arbiter";
-
- pmicintc: pmic {
- compatible = "qcom,pm8921";
- interrupt-parent = <&tlmm_pinmux>;
- interrupts = <74 8>;
- #interrupt-cells = <2>;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pm8921_gpio: gpio@150 {
-
- compatible = "qcom,pm8921-gpio",
- "qcom,ssbi-gpio";
- reg = <0x150>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- gpio-ranges = <&pm8921_gpio 0 0 44>;
- #gpio-cells = <2>;
-
- };
-
- pm8921_mpps: mpps@50 {
- compatible = "qcom,pm8921-mpp",
- "qcom,ssbi-mpp";
- reg = <0x50>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pm8921_mpps 0 0 12>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- rtc@11d {
- compatible = "qcom,pm8921-rtc";
- interrupt-parent = <&pmicintc>;
- interrupts = <39 1>;
- reg = <0x11d>;
- allow-set-time;
- };
-
- pwrkey@1c {
- compatible = "qcom,pm8921-pwrkey";
- reg = <0x1c>;
- interrupt-parent = <&pmicintc>;
- interrupts = <50 1>, <51 1>;
- debounce = <15625>;
- pull-up;
- };
-
- xoadc: xoadc@197 {
- compatible = "qcom,pm8921-adc";
- reg = <197>;
- interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <2>;
- #size-cells = <0>;
- #io-channel-cells = <2>;
-
- vcoin: adc-channel@0 {
- reg = <0x00 0x00>;
- };
- vbat: adc-channel@1 {
- reg = <0x00 0x01>;
- };
- dcin: adc-channel@2 {
- reg = <0x00 0x02>;
- };
- vph_pwr: adc-channel@4 {
- reg = <0x00 0x04>;
- };
- batt_therm: adc-channel@8 {
- reg = <0x00 0x08>;
- };
- batt_id: adc-channel@9 {
- reg = <0x00 0x09>;
- };
- usb_vbus: adc-channel@a {
- reg = <0x00 0x0a>;
- };
- die_temp: adc-channel@b {
- reg = <0x00 0x0b>;
- };
- ref_625mv: adc-channel@c {
- reg = <0x00 0x0c>;
- };
- ref_1250mv: adc-channel@d {
- reg = <0x00 0x0d>;
- };
- chg_temp: adc-channel@e {
- reg = <0x00 0x0e>;
- };
- ref_muxoff: adc-channel@f {
- reg = <0x00 0x0f>;
- };
- };
- };
};
- qfprom: qfprom@700000 {
+ qfprom: efuse@700000 {
compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+
tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
- tsens_backup: backup_calib@414 {
+ tsens_backup: backup-calib@414 {
reg = <0x414 0x10>;
};
};
@@ -802,7 +716,6 @@
compatible = "qcom,gcc-apq8064", "syscon";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
- #power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&cxo_board>,
<&pxo_board>,
@@ -856,7 +769,8 @@
<&dsi0_phy 0>,
<&dsi1_phy 1>,
<&dsi1_phy 0>,
- <&hdmi_phy>;
+ <&hdmi_phy>,
+ <&mdp>;
clock-names = "pxo",
"pll3",
"pll8_vote",
@@ -864,7 +778,8 @@
"dsi1pllbyte",
"dsi2pll",
"dsi2pllbyte",
- "hdmipll";
+ "hdmipll",
+ "lvdspll";
};
l2cc: clock-controller@2011000 {
@@ -891,60 +806,6 @@
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
};
-
- regulators {
- compatible = "qcom,rpm-pm8921-regulators";
-
- pm8921_s1: s1 {};
- pm8921_s2: s2 {};
- pm8921_s3: s3 {};
- pm8921_s4: s4 {};
- pm8921_s7: s7 {};
- pm8921_s8: s8 {};
-
- pm8921_l1: l1 {};
- pm8921_l2: l2 {};
- pm8921_l3: l3 {};
- pm8921_l4: l4 {};
- pm8921_l5: l5 {};
- pm8921_l6: l6 {};
- pm8921_l7: l7 {};
- pm8921_l8: l8 {};
- pm8921_l9: l9 {};
- pm8921_l10: l10 {};
- pm8921_l11: l11 {};
- pm8921_l12: l12 {};
- pm8921_l14: l14 {};
- pm8921_l15: l15 {};
- pm8921_l16: l16 {};
- pm8921_l17: l17 {};
- pm8921_l18: l18 {};
- pm8921_l21: l21 {};
- pm8921_l22: l22 {};
- pm8921_l23: l23 {};
- pm8921_l24: l24 {};
- pm8921_l25: l25 {};
- pm8921_l26: l26 {};
- pm8921_l27: l27 {};
- pm8921_l28: l28 {};
- pm8921_l29: l29 {};
-
- pm8921_lvs1: lvs1 {};
- pm8921_lvs2: lvs2 {};
- pm8921_lvs3: lvs3 {};
- pm8921_lvs4: lvs4 {};
- pm8921_lvs5: lvs5 {};
- pm8921_lvs6: lvs6 {};
- pm8921_lvs7: lvs7 {};
-
- pm8921_usb_switch: usb-switch {};
-
- pm8921_hdmi_switch: hdmi-switch {
- bias-pull-down;
- };
-
- pm8921_ncp: ncp {};
- };
};
usb1: usb@12500000 {
@@ -1044,7 +905,6 @@
compatible = "qcom,apq8064-sata-phy";
status = "disabled";
reg = <0x1b400000 0x200>;
- reg-names = "phy_mem";
clocks = <&gcc SATA_PHY_CFG_CLK>;
clock-names = "cfg";
#phy-cells = <0>;
@@ -1063,9 +923,9 @@
<&gcc SATA_PMALIVE_CLK>;
clock-names = "slave_iface",
"iface",
- "bus",
+ "core",
"rxoob",
- "core_pmalive";
+ "pmalive";
assigned-clocks = <&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
@@ -1096,7 +956,7 @@
sdcc3bam: dma-controller@12182000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
- interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1118,13 +978,13 @@
dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";
- pinctrl-0 = <&sdc4_gpios>;
+ pinctrl-0 = <&sdc4_default_state>;
};
sdcc4bam: dma-controller@121c2000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x121c2000 0x8000>;
- interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC4_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1135,7 +995,7 @@
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
pinctrl-names = "default";
- pinctrl-0 = <&sdcc1_pins>;
+ pinctrl-0 = <&sdcc1_default_state>;
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
@@ -1153,7 +1013,7 @@
sdcc1bam: dma-controller@12402000 {
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
- interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1165,7 +1025,7 @@
reg = <0x1a400000 0x100>;
};
- gpu: adreno-3xx@4300000 {
+ gpu: gpu@4300000 {
compatible = "qcom,adreno-320.2", "qcom,adreno";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
@@ -1263,14 +1123,13 @@
};
mmss_sfpb: syscon@5700000 {
- compatible = "syscon";
+ compatible = "qcom,apq8064-mmss-sfpb", "syscon";
reg = <0x5700000 0x70>;
};
dsi0: dsi@4700000 {
compatible = "qcom,apq8064-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
- label = "MDSS DSI CTRL->0";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -1473,7 +1332,7 @@
qcom,ncb = <3>;
};
- pcie: pci@1b500000 {
+ pcie: pcie@1b500000 {
compatible = "qcom,pcie-apq8064";
reg = <0x1b500000 0x1000>,
<0x1b502000 0x80>,
@@ -1492,10 +1351,10 @@
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
<&gcc PCIE_PHY_REF_CLK>;
@@ -1507,6 +1366,16 @@
<&gcc PCIE_PHY_RESET>;
reset-names = "axi", "ahb", "por", "pci", "phy";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
hdmi: hdmi-tx@4a00000 {
@@ -1569,13 +1438,19 @@
<&mmcc MDP_AXI_CLK>,
<&mmcc MDP_LUT_CLK>,
<&mmcc HDMI_TV_CLK>,
- <&mmcc MDP_TV_CLK>;
+ <&mmcc MDP_TV_CLK>,
+ <&mmcc LVDS_CLK>,
+ <&rpmcc RPM_PXO_CLK>;
clock-names = "core_clk",
"iface_clk",
"bus_clk",
"lut_clk",
"hdmi_clk",
- "tv_clk";
+ "tv_clk",
+ "lcdc_clk",
+ "pxo";
+
+ #clock-cells = <0>;
iommus = <&mdp_port0 0
&mdp_port0 2
@@ -1624,10 +1499,6 @@
memory-region = <&wcnss_mem>;
- vddcx-supply = <&pm8921_s3>;
- vddmx-supply = <&pm8921_l24>;
- vddpx-supply = <&pm8921_s4>;
-
status = "disabled";
iris {
@@ -1635,11 +1506,6 @@
clocks = <&cxo_board>;
clock-names = "xo";
-
- vddxo-supply = <&pm8921_l4>;
- vddrfa-supply = <&pm8921_s2>;
- vddpa-supply = <&pm8921_l10>;
- vdddig-supply = <&pm8921_lvs2>;
};
smd-edge {
@@ -1706,39 +1572,6 @@
};
};
- replicator {
- compatible = "arm,coresight-static-replicator";
-
- clocks = <&rpmcc RPM_QDSS_CLK>;
- clock-names = "apb_pclk";
-
- out-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- replicator_out0: endpoint {
- remote-endpoint = <&etb_in>;
- };
- };
- port@1 {
- reg = <1>;
- replicator_out1: endpoint {
- remote-endpoint = <&tpiu_in>;
- };
- };
- };
-
- in-ports {
- port {
- replicator_in: endpoint {
- remote-endpoint = <&funnel_out>;
- };
- };
- };
- };
-
funnel@1a04000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x1a04000 0x1000>;
@@ -1799,7 +1632,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
out-ports {
port {
@@ -1817,7 +1650,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
out-ports {
port {
@@ -1835,7 +1668,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
out-ports {
port {
@@ -1853,7 +1686,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
out-ports {
port {
generated by cgit (git 2.34.1) at 2025-12-26 08:54:18 +0000