diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 26 |
1 files changed, 11 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 0fb65f2bbcdf..8eeaab1c0be1 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -47,13 +47,12 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -61,13 +60,12 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -75,13 +73,12 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -89,17 +86,16 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -126,7 +122,7 @@ opp-716000000 { opp-hz = /bits/ 64 <716000000>; clock-latency-ns = <256000>; - }; + }; }; memory { @@ -179,6 +175,7 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; @@ -187,7 +184,6 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; clocks = <&xo>, <&sleep_clk>; @@ -433,10 +429,10 @@ interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_AHB_CLK>, <&gcc GCC_PCIE_AXI_M_CLK>, <&gcc GCC_PCIE_AXI_S_CLK>; |