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Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi528
1 files changed, 0 insertions, 528 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
deleted file mode 100644
index bee62a2cf6d6..000000000000
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ /dev/null
@@ -1,528 +0,0 @@
-/*
- * Copyright (C) 2012 Altera <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/include/ "skeleton.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- serial0 = &uart0;
- serial1 = &uart1;
- timer0 = &timer0;
- timer1 = &timer1;
- timer2 = &timer2;
- timer3 = &timer3;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <0>;
- next-level-cache = <&L2>;
- };
- cpu@1 {
- compatible = "arm,cortex-a9";
- device_type = "cpu";
- reg = <1>;
- next-level-cache = <&L2>;
- };
- };
-
- intc: intc@fffed000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0xfffed000 0x1000>,
- <0xfffec100 0x100>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- device_type = "soc";
- interrupt-parent = <&intc>;
- ranges;
-
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pdma: pdma@ffe01000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0xffe01000 0x1000>;
- interrupts = <0 180 4>;
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- };
- };
-
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
-
- clocks {
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: osc1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- };
-
- f2s_periph_ref_clk: f2s_periph_ref_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <10000000>;
- };
-
- main_pll: main_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc>;
- reg = <0x40>;
-
- mpuclk: mpuclk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- fixed-divider = <2>;
- reg = <0x48>;
- };
-
- mainclk: mainclk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- fixed-divider = <4>;
- reg = <0x4C>;
- };
-
- dbg_base_clk: dbg_base_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- fixed-divider = <4>;
- reg = <0x50>;
- };
-
- main_qspi_clk: main_qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x54>;
- };
-
- main_nand_sdmmc_clk: main_nand_sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x58>;
- };
-
- cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&main_pll>;
- reg = <0x5C>;
- };
- };
-
- periph_pll: periph_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc>;
- reg = <0x80>;
-
- emac0_clk: emac0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x88>;
- };
-
- emac1_clk: emac1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x8C>;
- };
-
- per_qspi_clk: per_qsi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x90>;
- };
-
- per_nand_mmc_clk: per_nand_mmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x94>;
- };
-
- per_base_clk: per_base_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x98>;
- };
-
- s2f_usr1_clk: s2f_usr1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&periph_pll>;
- reg = <0x9C>;
- };
- };
-
- sdram_pll: sdram_pll {
- #address-cells = <1>;
- #size-cells = <0>;
- #clock-cells = <0>;
- compatible = "altr,socfpga-pll-clock";
- clocks = <&osc>;
- reg = <0xC0>;
-
- ddr_dqs_clk: ddr_dqs_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xC8>;
- };
-
- ddr_2x_dqs_clk: ddr_2x_dqs_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xCC>;
- };
-
- ddr_dq_clk: ddr_dq_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xD0>;
- };
-
- s2f_usr2_clk: s2f_usr2_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-perip-clk";
- clocks = <&sdram_pll>;
- reg = <0xD4>;
- };
- };
-
- mpu_periph_clk: mpu_periph_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mpuclk>;
- fixed-divider = <4>;
- };
-
- mpu_l2_ram_clk: mpu_l2_ram_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mpuclk>;
- fixed-divider = <2>;
- };
-
- l4_main_clk: l4_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- clk-gate = <0x60 0>;
- };
-
- l3_main_clk: l3_main_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- };
-
- l3_mp_clk: l3_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- div-reg = <0x64 0 2>;
- clk-gate = <0x60 1>;
- };
-
- l3_sp_clk: l3_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>;
- div-reg = <0x64 2 2>;
- };
-
- l4_mp_clk: l4_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>, <&per_base_clk>;
- div-reg = <0x64 4 3>;
- clk-gate = <0x60 2>;
- };
-
- l4_sp_clk: l4_sp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&mainclk>, <&per_base_clk>;
- div-reg = <0x64 7 3>;
- clk-gate = <0x60 3>;
- };
-
- dbg_at_clk: dbg_at_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x68 0 2>;
- clk-gate = <0x60 4>;
- };
-
- dbg_clk: dbg_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x68 2 2>;
- clk-gate = <0x60 5>;
- };
-
- dbg_trace_clk: dbg_trace_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- div-reg = <0x6C 0 3>;
- clk-gate = <0x60 6>;
- };
-
- dbg_timer_clk: dbg_timer_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&dbg_base_clk>;
- clk-gate = <0x60 7>;
- };
-
- cfg_clk: cfg_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&cfg_s2f_usr0_clk>;
- clk-gate = <0x60 8>;
- };
-
- s2f_user0_clk: s2f_user0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&cfg_s2f_usr0_clk>;
- clk-gate = <0x60 9>;
- };
-
- emac_0_clk: emac_0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&emac0_clk>;
- clk-gate = <0xa0 0>;
- };
-
- emac_1_clk: emac_1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&emac1_clk>;
- clk-gate = <0xa0 1>;
- };
-
- usb_mp_clk: usb_mp_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 2>;
- div-reg = <0xa4 0 3>;
- };
-
- spi_m_clk: spi_m_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 3>;
- div-reg = <0xa4 3 3>;
- };
-
- can0_clk: can0_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 4>;
- div-reg = <0xa4 6 3>;
- };
-
- can1_clk: can1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 5>;
- div-reg = <0xa4 9 3>;
- };
-
- gpio_db_clk: gpio_db_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&per_base_clk>;
- clk-gate = <0xa0 6>;
- div-reg = <0xa8 0 24>;
- };
-
- s2f_user1_clk: s2f_user1_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&s2f_usr1_clk>;
- clk-gate = <0xa0 7>;
- };
-
- sdmmc_clk: sdmmc_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 8>;
- };
-
- nand_x_clk: nand_x_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 9>;
- };
-
- nand_clk: nand_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
- clk-gate = <0xa0 10>;
- fixed-divider = <4>;
- };
-
- qspi_clk: qspi_clk {
- #clock-cells = <0>;
- compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
- clk-gate = <0xa0 11>;
- };
- };
- };
-
- gmac0: ethernet@ff700000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- reg = <0xff700000 0x2000>;
- interrupts = <0 115 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac0_clk>;
- clock-names = "stmmaceth";
- status = "disabled";
- };
-
- gmac1: ethernet@ff702000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
- reg = <0xff702000 0x2000>;
- interrupts = <0 120 4>;
- interrupt-names = "macirq";
- mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac1_clk>;
- clock-names = "stmmaceth";
- status = "disabled";
- };
-
- L2: l2-cache@fffef000 {
- compatible = "arm,pl310-cache";
- reg = <0xfffef000 0x1000>;
- interrupts = <0 38 0x04>;
- cache-unified;
- cache-level = <2>;
- };
-
- /* Local timer */
- timer@fffec600 {
- compatible = "arm,cortex-a9-twd-timer";
- reg = <0xfffec600 0x100>;
- interrupts = <1 13 0xf04>;
- };
-
- timer0: timer0@ffc08000 {
- compatible = "snps,dw-apb-timer-sp";
- interrupts = <0 167 4>;
- reg = <0xffc08000 0x1000>;
- };
-
- timer1: timer1@ffc09000 {
- compatible = "snps,dw-apb-timer-sp";
- interrupts = <0 168 4>;
- reg = <0xffc09000 0x1000>;
- };
-
- timer2: timer2@ffd00000 {
- compatible = "snps,dw-apb-timer-osc";
- interrupts = <0 169 4>;
- reg = <0xffd00000 0x1000>;
- };
-
- timer3: timer3@ffd01000 {
- compatible = "snps,dw-apb-timer-osc";
- interrupts = <0 170 4>;
- reg = <0xffd01000 0x1000>;
- };
-
- uart0: serial0@ffc02000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc02000 0x1000>;
- interrupts = <0 162 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-
- uart1: serial1@ffc03000 {
- compatible = "snps,dw-apb-uart";
- reg = <0xffc03000 0x1000>;
- interrupts = <0 163 4>;
- reg-shift = <2>;
- reg-io-width = <4>;
- };
-
- rstmgr@ffd05000 {
- compatible = "altr,rst-mgr";
- reg = <0xffd05000 0x1000>;
- };
-
- sysmgr@ffd08000 {
- compatible = "altr,sys-mgr";
- reg = <0xffd08000 0x4000>;
- };
- };
-};
generated by cgit (git 2.34.1) at 2025-12-26 02:02:07 +0000