diff options
Diffstat (limited to 'arch/arm/boot/dts/st/stm32mp131.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/st/stm32mp131.dtsi | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6704ceef284d..b9657ff91c23 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -29,6 +29,12 @@ interrupt-parent = <&intc>; }; + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + firmware { optee { method = "smc"; @@ -100,6 +106,31 @@ always-on; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -261,6 +292,11 @@ dma-names = "up"; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + timer@5 { compatible = "st,stm32h7-timer-trigger"; reg = <5>; @@ -281,6 +317,11 @@ dma-names = "up"; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + timer@6 { compatible = "st,stm32h7-timer-trigger"; reg = <6>; @@ -909,6 +950,23 @@ }; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DTS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp131-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -948,6 +1006,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; @@ -973,12 +1032,21 @@ reg = <0x4 0x2>; bits = <0 12>; }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; etzpc: bus@5c007000 { @@ -1012,6 +1080,8 @@ interrupts = <0>; dmas = <&dmamux1 10 0x400 0x80000001>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@13 { @@ -1190,6 +1260,11 @@ access-controllers = <&etzpc 23>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1215,6 +1290,11 @@ access-controllers = <&etzpc 24>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1240,6 +1320,11 @@ access-controllers = <&etzpc 25>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1270,6 +1355,11 @@ access-controllers = <&etzpc 26>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1298,6 +1388,11 @@ access-controllers = <&etzpc 27>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1326,6 +1421,11 @@ access-controllers = <&etzpc 28>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1505,6 +1605,42 @@ status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "ptp_ref", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1PTP_K>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + access-controllers = <&etzpc 48>; + nvmem-cells = <ðernet_mac1_address>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; @@ -1528,6 +1664,16 @@ reg = <1>; }; }; + + iwdg1: watchdog@5c003000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5c003000 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc IWDG1>, <&scmi_clk CK_SCMI_LSI>; + clock-names = "pclk", "lsi"; + access-controllers = <&etzpc 12>; + status = "disabled"; + }; }; /* |