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Diffstat (limited to 'arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi64
1 files changed, 32 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
index e0799966bc25..52dba2e39c71 100644
--- a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
@@ -16,31 +16,31 @@
uart0 {
uart0_default_mux: uart0_mux {
default_mux {
- ste,function = "u0";
- ste,pins = "u0_a_1";
+ function = "u0";
+ groups = "u0_a_1";
};
};
uart0_default_mode: uart0_default {
default_cfg1 {
- ste,pins = "GPIO0", "GPIO2";
+ pins = "GPIO0", "GPIO2";
ste,config = <&in_pu>;
};
default_cfg2 {
- ste,pins = "GPIO1", "GPIO3";
+ pins = "GPIO1", "GPIO3";
ste,config = <&out_hi>;
};
};
uart0_sleep_mode: uart0_sleep {
sleep_cfg1 {
- ste,pins = "GPIO0", "GPIO2";
+ pins = "GPIO0", "GPIO2";
ste,config = <&slpm_in_pu>;
};
sleep_cfg2 {
- ste,pins = "GPIO1", "GPIO3";
+ pins = "GPIO1", "GPIO3";
ste,config = <&slpm_out_hi>;
};
};
@@ -49,29 +49,29 @@
uart2 {
uart2_default_mode: uart2_default {
default_mux {
- ste,function = "u2";
- ste,pins = "u2txrx_a_1";
+ function = "u2";
+ groups = "u2txrx_a_1";
};
default_cfg1 {
- ste,pins = "GPIO120";
+ pins = "GPIO120";
ste,config = <&in_pu>;
};
default_cfg2 {
- ste,pins = "GPIO121";
+ pins = "GPIO121";
ste,config = <&out_hi>;
};
};
uart2_sleep_mode: uart2_sleep {
sleep_cfg1 {
- ste,pins = "GPIO120";
+ pins = "GPIO120";
ste,config = <&slpm_in_pu>;
};
sleep_cfg2 {
- ste,pins = "GPIO121";
+ pins = "GPIO121";
ste,config = <&slpm_out_hi>;
};
};
@@ -80,21 +80,21 @@
i2c0 {
i2c0_default_mux: i2c_mux {
default_mux {
- ste,function = "i2c0";
- ste,pins = "i2c0_a_1";
+ function = "i2c0";
+ groups = "i2c0_a_1";
};
};
i2c0_default_mode: i2c_default {
default_cfg1 {
- ste,pins = "GPIO147", "GPIO148";
+ pins = "GPIO147", "GPIO148";
ste,config = <&in_pu>;
};
};
i2c0_sleep_mode: i2c_sleep {
sleep_cfg1 {
- ste,pins = "GPIO147", "GPIO148";
+ pins = "GPIO147", "GPIO148";
ste,config = <&slpm_in_pu>;
};
};
@@ -103,21 +103,21 @@
i2c1 {
i2c1_default_mux: i2c_mux {
default_mux {
- ste,function = "i2c1";
- ste,pins = "i2c1_b_2";
+ function = "i2c1";
+ groups = "i2c1_b_2";
};
};
i2c1_default_mode: i2c_default {
default_cfg1 {
- ste,pins = "GPIO16", "GPIO17";
+ pins = "GPIO16", "GPIO17";
ste,config = <&in_pu>;
};
};
i2c1_sleep_mode: i2c_sleep {
sleep_cfg1 {
- ste,pins = "GPIO16", "GPIO17";
+ pins = "GPIO16", "GPIO17";
ste,config = <&slpm_in_pu>;
};
};
@@ -126,21 +126,21 @@
i2c2 {
i2c2_default_mux: i2c_mux {
default_mux {
- ste,function = "i2c2";
- ste,pins = "i2c2_b_2";
+ function = "i2c2";
+ groups = "i2c2_b_2";
};
};
i2c2_default_mode: i2c_default {
default_cfg1 {
- ste,pins = "GPIO10", "GPIO11";
+ pins = "GPIO10", "GPIO11";
ste,config = <&in_pu>;
};
};
i2c2_sleep_mode: i2c_sleep {
sleep_cfg1 {
- ste,pins = "GPIO11", "GPIO11";
+ pins = "GPIO11", "GPIO11";
ste,config = <&slpm_in_pu>;
};
};
@@ -149,21 +149,21 @@
i2c4 {
i2c4_default_mux: i2c_mux {
default_mux {
- ste,function = "i2c4";
- ste,pins = "i2c4_b_2";
+ function = "i2c4";
+ groups = "i2c4_b_2";
};
};
i2c4_default_mode: i2c_default {
default_cfg1 {
- ste,pins = "GPIO122", "GPIO123";
+ pins = "GPIO122", "GPIO123";
ste,config = <&in_pu>;
};
};
i2c4_sleep_mode: i2c_sleep {
sleep_cfg1 {
- ste,pins = "GPIO122", "GPIO123";
+ pins = "GPIO122", "GPIO123";
ste,config = <&slpm_in_pu>;
};
};
@@ -172,21 +172,21 @@
i2c5 {
i2c5_default_mux: i2c_mux {
default_mux {
- ste,function = "i2c5";
- ste,pins = "i2c5_c_2";
+ function = "i2c5";
+ groups = "i2c5_c_2";
};
};
i2c5_default_mode: i2c_default {
default_cfg1 {
- ste,pins = "GPIO118", "GPIO119";
+ pins = "GPIO118", "GPIO119";
ste,config = <&in_pu>;
};
};
i2c5_sleep_mode: i2c_sleep {
sleep_cfg1 {
- ste,pins = "GPIO118", "GPIO119";
+ pins = "GPIO118", "GPIO119";
ste,config = <&slpm_in_pu>;
};
};