diff options
Diffstat (limited to 'arch/arm/boot/dts')
297 files changed, 10084 insertions, 828 deletions
diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 48666f73e638..d799ad153b37 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -199,6 +199,7 @@ DTC_FLAGS_sun8i-h3-nanopi-r1 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@ +DTC_FLAGS_sun8i-v3s-netcube-kumquat := -@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ sun8i-a23-gt90h-v4.dtb \ @@ -261,6 +262,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-v3s-anbernic-rg-nano.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v3s-netcube-kumquat.dtb \ sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts index 46ecf9db2324..d8b362c9661a 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi.dts @@ -48,6 +48,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> / { model = "LeMaker Banana Pi"; @@ -169,6 +170,32 @@ &gmac_mdio { phy1: ethernet-phy@1 { reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi index addf0cb0f465..6f88d8764e6a 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -1225,7 +1225,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu0_hot>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -1255,7 +1255,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu1_hot>; cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts index 6d85370e04f1..9a2742363cd0 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts @@ -94,7 +94,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi index eac2349a2380..cfd039840b43 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi @@ -262,7 +262,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi index a5b1f1e3900d..fa162f7fa9f0 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi @@ -146,7 +146,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s-netcube-kumquat.dts b/arch/arm/boot/dts/allwinner/sun8i-v3s-netcube-kumquat.dts new file mode 100644 index 000000000000..5143cb4e7b78 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s-netcube-kumquat.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li> + */ + +/dts-v1/; +#include "sun8i-v3s.dtsi" + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/gpio.h> + +/{ + model = "NetCube Systems Kumquat"; + compatible = "netcube,kumquat", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + rtc0 = &ds3232; + rtc1 = &rtc; /* not battery backed */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 40 MHz Crystal Oscillator on PCB */ + clk_can0: clock-can0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-user { + label = "GPIO Key User"; + linux,code = <KEY_PROG1>; + gpios = <&pio 1 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PB2 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-heartbeat { + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + }; + + led-mmc0-act { + gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + linux,default-trigger = "mmc0"; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DISK; + }; + }; + + /* EA3036C Switching 3 Channel Regulator - Channel 2 */ + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v0>; + }; + + /* K7805-1000R3 Switching Regulator supplied from main 12/24V terminal block */ + reg_vcc5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "MIC1", "Mic", + "Mic", "HBIAS"; + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&emac { + allwinner,leds-active-low; + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */ + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc3v3>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@fa { + reg = <0xfa 0x06>; + }; + }; + + tusb320: typec@60 { + compatible = "ti,tusb320"; + reg = <0x60>; + interrupts-extended = <&pio 1 5 IRQ_TYPE_LEVEL_LOW>; /* PB5 */ + }; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; +}; + +/* Exposed as the Flash/SD Header on the board */ +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +/* Connected to the on-board ESP32 */ +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +/* Disable external 32k osc as it is broken on current revision */ +&osc32k { + status = "disabled"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "CAN_nCS", "CAN_nINT", "USER_SW", "PB3", // PB + "USB_ID", "USBC_nINT", "I2C0_SCL", "I2C0_SDA", + "UART0_TX", "UART0_RX", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SPI_MISO", "SPI_SCK", "FLASH_nCS", "SPI_MOSI", // PC + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "Q12", "Q11", "Q10", "Q9", // PE + "LED_SYS0", "I1", "Q1", "Q2", + "I2", "I3", "Q3", "Q4", + "I4", "I5", "Q5", "Q6", + "I6", "I7", "Q7", "Q8", + "I8", "UART1_TXD", "UART1_RXD", "ESP_nRST", + "ESP_nBOOT", "", "", "", + "", "", "", "", + "SD_D1", "SD_D0", "SD_CLK", "SD_CMD", // PF + "SD_D3", "SD_D2", "LED_SYS1", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* Disable external 32k osc as it is broken on current revision */ +&rtc { + /delete-property/ clocks; +}; + +/* Exposed as a USB-C connector with USB-Serial converter */ +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Connected to the Bootloader/Console of the ESP32 */ +&uart1 { + pinctrl-0 = <&uart1_pe_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + extcon = <&tusb320 0>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + status = "okay"; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <0>, <&pio 1 0 GPIO_ACTIVE_LOW>; /* PB0 */ + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + label = "firmware"; + spi-max-frequency = <40000000>; + }; + + can@1 { + compatible = "microchip,mcp2518fd"; + reg = <1>; + clocks = <&clk_can0>; + interrupts-extended = <&pio 1 1 IRQ_TYPE_LEVEL_LOW>; /* PB1 */ + spi-max-frequency = <20000000>; + vdd-supply = <®_vcc3v3>; + xceiver-supply = <®_vcc3v3>; + }; +}; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index 9e13c2aa8911..f909b1d4dbca 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -416,6 +416,12 @@ function = "uart0"; }; + /omit-if-no-ref/ + uart1_pe_pins: uart1-pe-pins { + pins = "PE21", "PE22"; + function = "uart1"; + }; + uart2_pins: uart2-pins { pins = "PB0", "PB1"; function = "uart2"; diff --git a/arch/arm/boot/dts/amlogic/Makefile b/arch/arm/boot/dts/amlogic/Makefile index 504c533b1173..3c8a1e88b386 100644 --- a/arch/arm/boot/dts/amlogic/Makefile +++ b/arch/arm/boot/dts/amlogic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_MACH_MESON8) += \ meson8-minix-neo-x8.dtb \ + meson8-fernsehfee3.dtb \ meson8b-ec100.dtb \ meson8b-mxq.dtb \ meson8b-odroidc1.dtb \ diff --git a/arch/arm/boot/dts/amlogic/meson8-fernsehfee3.dts b/arch/arm/boot/dts/amlogic/meson8-fernsehfee3.dts new file mode 100644 index 000000000000..4e52447d51bd --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson8-fernsehfee3.dts @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +// Copyright (C) 2025 J. Neuschäfer <j.ne@posteo.net> + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +#include "meson8.dtsi" + +/ { + model = "Fernsehfee 3.0"; + compatible = "tcu,fernsehfee3", "amlogic,meson8"; + + aliases { + serial0 = &uart_AO; + gpiochip0 = &gpio; + gpiochip1 = &gpio_ao; + i2c0 = &i2c_AO; + i2c1 = &i2c_B; + mmc0 = &sdhc; + mmc1 = &sdio; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1 GiB */ + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + power-button { + label = "Power button"; + linux,code = <KEY_POWER>; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* + * The power LED can be turned red, otherwise it is green. + */ + gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + }; + }; + + vcc_5v: regulator-5v { + /* 5V rail, always on as long as the system is running */ + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc_3v3: regulator-3v3 { + /* Chipown AP2420 step-down converter */ + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v>; + }; + + wifi_3v3: regulator-wifi { + compatible = "regulator-fixed"; + regulator-name = "3.3V-WIFI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + gpio = <&gpio GPIOX_11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + cpu-supply = <&vcck>; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* IC Plus IP101A (0x02430c54) */ + reg = <0>; + + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_pins>; + pinctrl-names = "default"; + + pmic@32 { + compatible = "ricoh,rn5t618"; + reg = <0x32>; + system-power-controller; + + regulators { + vcck: DCDC1 { + regulator-name = "VCCK"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vddee: DCDC2 { + /* the output is also used as VDDAO */ + regulator-name = "VDD_EE"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + DCDC3 { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "VDDIO_AO28"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO2 { + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc1v8_usb: LDO3 { + regulator-name = "VCC1V8_USB"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + LDO4 { + /* This one appears to be unused */ + regulator-name = "VCC2V8"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + LDO5 { + regulator-name = "AVDD1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDORTC1 { + regulator-name = "VDD_LDO"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-boot-on; + regulator-always-on; + }; + + LDORTC2 { + regulator-name = "RTC_0V9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + /* Fairchild FM24C08A */ + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + wp-gpios = <&gpio GPIOH_3 GPIO_ACTIVE_HIGH>; + num-addresses = <4>; + }; +}; + +&i2c_B { + status = "okay"; + pinctrl-0 = <&i2c_b_pins>; + pinctrl-names = "default"; + + /* TODO: SiI9293 HDMI receiver @ 0x39 */ +}; + +&mali { + mali-supply = <&vddee>; +}; + +&sdhc { + status = "okay"; + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + /* eMMC */ + bus-width = <8>; + max-frequency = <100000000>; + + disable-wp; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + +&sdio { + status = "okay"; + pinctrl-0 = <&sd_b_pins>; + + /* SD card */ + slot@1 { + compatible = "mmc-slot"; + reg = <1>; + status = "okay"; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vcc_3v3>; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; + phy-supply = <&vcc1v8_usb>; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + wifi: wifi@1 { + /* Realtek RTL8188 2.4GHz WiFi module */ + compatible = "usbbda,179"; + reg = <1>; + vdd-supply = <&wifi_3v3>; + }; +}; + +&usb1_phy { + status = "okay"; + phy-supply = <&vcc1v8_usb>; +}; + +&ir_receiver { + status = "okay"; + pinctrl-0 = <&ir_recv_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi index 9ff142d9fe3f..a609b5a0fda4 100644 --- a/arch/arm/boot/dts/amlogic/meson8.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8.dtsi @@ -398,7 +398,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; - bias-disable; + bias-pull-up; }; }; @@ -449,7 +449,11 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -477,6 +481,14 @@ gpio-ranges = <&pinctrl_cbus 0 0 120>; }; + i2c_b_pins: i2c-b { + mux { + groups = "i2c_sda_b", "i2c_sck_b"; + function = "i2c_b"; + bias-disable; + }; + }; + sd_a_pins: sd-a { mux { groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", @@ -522,6 +534,16 @@ }; }; + sdxc_c_pins: sdxc-c { + mux { + groups = "sdxc_d0_c", "sdxc_d13_c", + "sdxc_clk_c", "sdxc_cmd_c", + "sdxc_d47_c"; + function = "sdxc_c"; + bias-pull-up; + }; + }; + spdif_out_pins: spdif-out { mux { groups = "spdif_out"; @@ -563,7 +585,7 @@ groups = "uart_tx_a1", "uart_rx_a1"; function = "uart_a"; - bias-disable; + bias-pull-up; }; }; @@ -699,11 +721,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts index 18ea6592b7d7..236999548094 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-ec100.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-ec100.dts @@ -443,8 +443,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts index fb28cb330f17..0bca0b33eea2 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-mxq.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-mxq.dts @@ -162,8 +162,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &uart_AO { diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts index 2aa012f38a3b..1cd2093202ca 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts @@ -347,8 +347,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi index 9e02a97f86a0..2d77b9876bf4 100644 --- a/arch/arm/boot/dts/amlogic/meson8b.dtsi +++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi @@ -368,7 +368,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; - bias-disable; + bias-pull-up; }; }; @@ -403,8 +403,12 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x86c0 0x10>; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; @@ -517,7 +521,7 @@ groups = "uart_tx_b0", "uart_rx_b0"; function = "uart_b"; - bias-disable; + bias-pull-up; }; }; @@ -674,11 +678,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile index d23cf466127b..71062ff9adbe 100644 --- a/arch/arm/boot/dts/broadcom/Makefile +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -7,6 +7,7 @@ DTC_FLAGS_bcm2835-rpi-b-plus := -@ DTC_FLAGS_bcm2835-rpi-a-plus := -@ DTC_FLAGS_bcm2835-rpi-cm1-io1 := -@ DTC_FLAGS_bcm2836-rpi-2-b := -@ +DTC_FLAGS_bcm2837-rpi-2-b := -@ DTC_FLAGS_bcm2837-rpi-3-a-plus := -@ DTC_FLAGS_bcm2837-rpi-3-b := -@ DTC_FLAGS_bcm2837-rpi-3-b-plus := -@ @@ -25,6 +26,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-a-plus.dtb \ bcm2835-rpi-cm1-io1.dtb \ bcm2836-rpi-2-b.dtb \ + bcm2837-rpi-2-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi index 87180b7fd695..f535212cb52f 100644 --- a/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2166x-common.dtsi @@ -46,6 +46,11 @@ interrupt-controller; }; + pinctrl: pinctrl@1004800 { + compatible = "brcm,bcm21664-pinctrl"; + reg = <0x01004800 0x7f4>; + }; + timer@1006000 { compatible = "brcm,kona-timer"; reg = <0x01006000 0x1c>; @@ -332,3 +337,5 @@ }; }; }; + +#include "bcm2166x-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi b/arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi new file mode 100644 index 000000000000..51b8730c8fee --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2166x-pinctrl.dtsi @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Common pinmux configrations for BCM2166x (BCM21664/BCM23550). + * + * Copyright (C) 2025 Artur Weber <aweber.kernel@gmail.com> + */ + +&pinctrl { + /* BSC1 */ + bsc1_pins: bsc1-pins { + bsc1clk-grp0 { + pins = "bsc1clk"; + function = "alt1"; /* BSC1CLK */ + }; + + bsc1dat-grp0 { + pins = "bsc1dat"; + function = "alt1"; /* BSC1DAT */ + }; + }; + + /* BSC2 */ + bsc2_pins: bsc2-pins { + bsc2clk-grp0 { + pins = "gpio16"; + function = "alt2"; /* BSC2CLK */ + }; + + bsc2dat-grp0 { + pins = "gpio17"; + function = "alt2"; /* BSC2DAT */ + }; + }; + + /* BSC3 */ + bsc3_pins: bsc3-pins { + bsc3clk-grp0 { + pins = "lcdscl"; + function = "alt1"; /* BSC3_CLK */ + }; + + bsc3dat-grp0 { + pins = "lcdsda"; + function = "alt1"; /* BSC3_SDA */ + }; + }; + + /* BSC4 */ + bsc4_pins: bsc4-pins { + bsc4clk-grp0 { + pins = "lcdres"; + function = "alt1"; /* BSC4_CLK */ + }; + + bsc4dat-grp0 { + pins = "lcdte"; + function = "alt1"; /* BSC4_SDA */ + }; + }; + + /* PMBSC */ + pmbsc_pins: pmbsc-pins { + pmbscclk-grp0 { + pins = "pmbscclk"; + function = "alt1"; /* PMBSCCLK */ + }; + + pmbscdat-grp0 { + pins = "pmbscdat"; + function = "alt1"; /* PMBSCDAT */ + }; + }; + + /* SD */ + sd_width1_pins: sd-width1-pins { + sdck-grp0 { + pins = "sdck"; + function = "alt1"; /* SDCK */ + bias-disable; + }; + + sdcmd-grp0 { + pins = "sdcmd"; + function = "alt1"; /* SDCMD */ + bias-pull-up; + }; + + sddat-grp0 { + pins = "sddat0"; + function = "alt1"; /* SDDATx */ + bias-pull-up; + }; + }; + + sd_width4_pins: sd-width4-pins { + sdck-grp0 { + pins = "sdck"; + function = "alt1"; /* SDCK */ + bias-disable; + }; + + sdcmd-grp0 { + pins = "sdcmd"; + function = "alt1"; /* SDCMD */ + bias-pull-up; + }; + + sddat-grp0 { + pins = "sddat0", "sddat1", "sddat2", "sddat3"; + function = "alt1"; /* SDDATx */ + bias-pull-up; + }; + }; + + /* SD1 */ + sd1_width1_pins: sd1-width1-pins { + sd1ck-grp0 { + pins = "mmc1dat7"; + function = "alt6"; /* SD1CK */ + bias-disable; + }; + + sd1cmd-grp0 { + pins = "spi0txd"; + function = "alt2"; /* SD1CMD */ + bias-pull-up; + }; + + sd1dat0-grp0 { + pins = "mmc1dat5"; + function = "alt6"; /* SD1DAT0 */ + bias-pull-up; + }; + }; + + sd1_width4_pins: sd1-width4-pins { + sd1ck-grp0 { + pins = "mmc1dat7"; + function = "alt6"; /* SD1CK */ + bias-disable; + }; + + sd1cmd-grp0 { + pins = "spi0txd"; + function = "alt2"; /* SD1CMD */ + bias-pull-up; + }; + + sd1dat0-grp0 { + pins = "mmc1dat5"; + function = "alt6"; /* SD1DAT0 */ + bias-pull-up; + }; + + sd1dat1-grp0 { + pins = "gpio93"; + function = "alt1"; /* SD1DAT1 */ + bias-pull-up; + }; + + sd1dat2-grp0 { + pins = "gpio94"; + function = "alt1"; /* SD1DAT2 */ + bias-pull-up; + }; + + sd1dat3-grp0 { + pins = "mmc1dat3"; + function = "alt6"; /* SD1DAT3 */ + bias-pull-up; + }; + }; + + /* MMC0 */ + mmc0_width1_pins: mmc0-width1-pins { + mmc0ck-grp0 { + pins = "mmc0ck"; + function = "alt1"; /* MMC0CK */ + bias-disable; + }; + + mmc0cmd-grp0 { + pins = "mmc0cmd"; + function = "alt1"; /* MMC0CMD */ + bias-pull-up; + }; + + mmc0dat-grp0 { + pins = "mmc0dat0"; + function = "alt1"; /* MMC0DATx */ + bias-pull-up; + }; + }; + + mmc0_width4_pins: mmc0-width4-pins { + mmc0ck-grp0 { + pins = "mmc0ck"; + function = "alt1"; /* MMC0CK */ + bias-disable; + }; + + mmc0cmd-grp0 { + pins = "mmc0cmd"; + function = "alt1"; /* MMC0CMD */ + bias-pull-up; + }; + + mmc0dat-grp0 { + pins = "mmc0dat0", "mmc0dat1", "mmc0dat2", "mmc0dat3"; + function = "alt1"; /* MMC0DATx */ + bias-pull-up; + }; + }; + + mmc0_width8_pins: mmc0-width8-pins { + mmc0ck-grp0 { + pins = "mmc0ck"; + function = "alt1"; /* MMC0CK */ + bias-disable; + }; + + mmc0cmd-grp0 { + pins = "mmc0cmd"; + function = "alt1"; /* MMC0CMD */ + bias-pull-up; + }; + + mmc0dat-grp0 { + pins = "mmc0dat0", "mmc0dat1", "mmc0dat2", "mmc0dat3", + "mmc0dat4", "mmc0dat5", "mmc0dat6", "mmc0dat7"; + function = "alt1"; /* MMC0DATx */ + bias-pull-up; + }; + }; + + /* MMC1 */ + mmc1_width1_pins: mmc1-width1-pins { + mmc1ck-grp0 { + pins = "mmc1ck"; + function = "alt1"; /* MMC1CK */ + bias-disable; + }; + + mmc1cmd-grp0 { + pins = "mmc1cmd"; + function = "alt1"; /* MMC1CMD */ + bias-pull-up; + }; + + mmc1dat-grp0 { + pins = "mmc1dat0"; + function = "alt1"; /* MMC1DATx */ + bias-pull-up; + }; + }; + + mmc1_width4_pins: mmc1-width4-pins { + mmc1ck-grp0 { + pins = "mmc1ck"; + function = "alt1"; /* MMC1CK */ + bias-disable; + }; + + mmc1cmd-grp0 { + pins = "mmc1cmd"; + function = "alt1"; /* MMC1CMD */ + bias-pull-up; + }; + + mmc1dat-grp0 { + pins = "mmc1dat0", "mmc1dat1", "mmc1dat2", "mmc1dat3"; + function = "alt1"; /* MMC1DATx */ + bias-pull-up; + }; + }; + + mmc1_width8_pins: mmc1-width8-pins { + mmc1ck-grp0 { + pins = "mmc1ck"; + function = "alt1"; /* MMC1CK */ + bias-disable; + }; + + mmc1cmd-grp0 { + pins = "mmc1cmd"; + function = "alt1"; /* MMC1CMD */ + bias-pull-up; + }; + + mmc1dat-grp0 { + pins = "mmc1dat0", "mmc1dat1", "mmc1dat2", "mmc1dat3", + "mmc1dat4", "mmc1dat5", "mmc1dat6", "mmc1dat7"; + function = "alt1"; /* MMC1DATx */ + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi index 6bf4241fe3b7..c78ed064d166 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm2835-rpi.dtsi" -#include <dt-bindings/power/raspberrypi-power.h> #include <dt-bindings/reset/raspberrypi,firmware-reset.h> / { @@ -101,7 +100,3 @@ &vchiq { interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; - -&xhci { - power-domains = <&power RPI_POWER_DOMAIN_USB>; -}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index e4e42af21ef3..c06d9f5e53c8 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -134,7 +134,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -145,7 +145,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -156,7 +156,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -167,7 +167,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -451,8 +451,6 @@ IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - /* This only applies to the ARMv7 stub */ - arm,cpu-registers-not-fw-configured; }; cpus: cpus { @@ -610,6 +608,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pm BCM2835_POWER_DOMAIN_USB>; /* DWC2 and this IP block share the same USB PHY, * enabling both at the same time results in lockups. * So keep this node disabled and let the bootloader @@ -1177,6 +1176,7 @@ }; &uart0 { + arm,primecell-periphid = <0x00341011>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm28155-ap.dts b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts index 2f3634545e64..cefaa9a3c45c 100644 --- a/arch/arm/boot/dts/broadcom/bcm28155-ap.dts +++ b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts @@ -37,7 +37,39 @@ status = "okay"; pmu: pmu@8 { + compatible = "brcm,bcm59056"; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; reg = <0x08>; + + regulators { + camldo1_reg: camldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdldo_reg: sdldo { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + sdxldo_reg: sdxldo { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + }; + + usbldo_reg: usbldo { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + iosr1_reg: iosr1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; }; }; @@ -74,39 +106,3 @@ &usbphy { status = "okay"; }; - -#include "bcm59056.dtsi" - -&pmu { - compatible = "brcm,bcm59056"; - interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; - regulators { - camldo1_reg: camldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - sdldo_reg: sdldo { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - sdxldo_reg: sdxldo { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - }; - - usbldo_reg: usbldo { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - iosr1_reg: iosr1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; -}; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-2-b.dts new file mode 100644 index 000000000000..1868cee05853 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-2-b.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,2-model-b-rev2", "brcm,bcm2837"; + model = "Raspberry Pi 2 Model B rev 1.2"; + + memory@0 { + device_type = "memory"; + reg = <0 0x40000000>; + }; +}; + +&gpio { + /* + * Taken from rpi_SCH_2b_1p2_reduced.pdf and + * the official GPU firmware DT blob. + * + * Legend: + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "", /* GPIO30 */ + "LAN_RUN", + "CAM_GPIO1", + "", /* GPIO33 */ + "", /* GPIO34 */ + "PWR_LOW_N", + "", /* GPIO36 */ + "", /* GPIO37 */ + "USB_LIMIT", + "", /* GPIO39 */ + "PWM0_OUT", + "CAM_GPIO0", + "SMPS_SCL", + "SMPS_SDA", + "ETH_CLK", + "PWM1_OUT", + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = <BCM2835_FSEL_ALT0>; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio14>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts index 53cb0c58f6d0..3da2daee0c84 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts @@ -124,19 +124,19 @@ }; port@1 { - label = "lan1"; + label = "lan4"; }; port@2 { - label = "lan2"; + label = "lan3"; }; port@3 { - label = "lan3"; + label = "lan2"; }; port@4 { - label = "lan4"; + label = "lan1"; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts index 6c666dc7ad23..01ec8c03686a 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts @@ -126,11 +126,11 @@ ports { port@0 { - label = "lan4"; + label = "wan"; }; port@1 { - label = "lan3"; + label = "lan1"; }; port@2 { @@ -138,11 +138,11 @@ }; port@3 { - label = "lan1"; + label = "lan3"; }; port@4 { - label = "wan"; + label = "lan4"; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm59056.dtsi b/arch/arm/boot/dts/broadcom/bcm59056.dtsi deleted file mode 100644 index a9bb7ad81378..000000000000 --- a/arch/arm/boot/dts/broadcom/bcm59056.dtsi +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* -* Copyright 2014 Linaro Limited -* Author: Matt Porter <mporter@linaro.org> -*/ - -&pmu { - compatible = "brcm,bcm59056"; - regulators { - rfldo_reg: rfldo { - }; - - camldo1_reg: camldo1 { - }; - - camldo2_reg: camldo2 { - }; - - simldo1_reg: simldo1 { - }; - - simldo2_reg: simldo2 { - }; - - sdldo_reg: sdldo { - }; - - sdxldo_reg: sdxldo { - }; - - mmcldo1_reg: mmcldo1 { - }; - - mmcldo2_reg: mmcldo2 { - }; - - audldo_reg: audldo { - }; - - micldo_reg: micldo { - }; - - usbldo_reg: usbldo { - }; - - vibldo_reg: vibldo { - }; - - csr_reg: csr { - }; - - iosr1_reg: iosr1 { - }; - - iosr2_reg: iosr2 { - }; - - msr_reg: msr { - }; - - sdsr1_reg: sdsr1 { - }; - - sdsr2_reg: sdsr2 { - }; - - vsr_reg: vsr { - }; - - gpldo1_reg: gpldo1 { - }; - - gpldo2_reg: gpldo2 { - }; - - gpldo3_reg: gpldo3 { - }; - - gpldo4_reg: gpldo4 { - }; - - gpldo5_reg: gpldo5 { - }; - - gpldo6_reg: gpldo6 { - }; - - vbus_reg: vbus { - }; - }; -}; diff --git a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts index 808cd5778e27..adc74243ed19 100644 --- a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts @@ -88,7 +88,7 @@ }; &portd { - lcden { + lcden-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts index 19d56e9aec9d..a351a97d257e 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts @@ -8,6 +8,7 @@ #include "intel-ixp42x.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "Netgear WG302 v1"; @@ -32,6 +33,35 @@ serial0 = &uart1; }; + leds { + compatible = "gpio-leds"; + test_led: led-test { + color = <LED_COLOR_ID_AMBER>; + function = "test"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + wlan_led: led-wlan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "phy0tx"; + }; + }; + + gpio_keys { + /* RESET is on GPIO13 which can't fire interrupts */ + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-reset { + linux,code = <KEY_RESTART>; + label = "reset"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + soc { bus@c4000000 { flash@0,0 { @@ -57,7 +87,7 @@ status = "okay"; /* - * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) + * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c) * We have slots (IDSEL) 1 and 2 with one assigned IRQ * each handling all IRQs. */ @@ -70,10 +100,10 @@ <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ - <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ }; ethernet@c8009000 { diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi index 51a716c59669..0adeccabd4fe 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi @@ -193,10 +193,10 @@ compatible = "intel,ixp4xx-ethernet"; reg = <0xc800c000 0x1000>; status = "disabled"; - intel,npe = <0>; /* Dummy values that depend on firmware */ queue-rx = <&qmgr 0>; queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 0>; }; }; }; diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index c467828aeb4b..7f69a0355ea5 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_de10nano.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sodia.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts new file mode 100644 index 000000000000..ec25106caacf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Intel Corporation + * + * based on socfpga_cyclone5_de0_nano_soc.dts + */ +/dts-v1/; + +#include "socfpga_cyclone5.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Terasic DE10-Nano"; + compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + /* 1 GiB */ + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + soc { + fpga: bus@ff200000 { + compatible = "simple-bus"; + reg = <0xff200000 0x00200000>; + ranges = <0x00000000 0xff200000 0x00200000>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Here the devices will appear if an FPGA image is + * loaded. Their description is expected to be added + * using a device tree overlay that matches the image. + */ + }; + }; +}; + +&gmac1 { + /* Uses a KSZ9031RNX phy */ + phy-mode = "rgmii-id"; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + rxdv-skew-ps = <420>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + /* HPS_GSENSOR_INT is routed to UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61 */ + interrupt-parent = <&portc>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + }; +}; + +&mmc0 { + /* micro SD card socket J11 */ + status = "okay"; +}; + +&uart0 { + /* + * Accessible via USB (FT232R) on Mini-USB plug J4 + * RX = TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49 + * TX = TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50 + * no handshaking lines + */ + clock-frequency = <100000000>; +}; diff --git a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi index 8208c6a9627a..7aa71a9aa1bb 100644 --- a/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +++ b/arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi @@ -453,7 +453,7 @@ pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; - wifi-disable { + wifi-disable-hog { gpio-hog; gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; output-low; @@ -465,7 +465,7 @@ pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; - lte-disable { + lte-disable-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_LOW>; output-low; @@ -476,14 +476,14 @@ * This signal, when asserted, isolates Armada 38x sample at reset pins * from control of external devices. Should be de-asserted after reset. */ - sar-isolation { + sar-isolation-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_LOW>; output-low; line-name = "sar-isolation"; }; - poe-reset { + poe-reset-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts index f7daa3bc707e..cf32ba9b4e8e 100644 --- a/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts +++ b/arch/arm/boot/dts/marvell/armada-388-clearfog-base.dts @@ -34,7 +34,7 @@ }; &gpio0 { - phy1_reset { + phy1-reset-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm/boot/dts/marvell/kirkwood-db.dtsi b/arch/arm/boot/dts/marvell/kirkwood-db.dtsi index 6fe2e31534af..8bacaeb4f4bd 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-db.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-db.dtsi @@ -39,7 +39,7 @@ status = "okay"; }; - ehci@50000 { + usb@50000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts index 2f6793f794cd..36394d1ab3e2 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts @@ -129,7 +129,7 @@ status = "okay"; }; - ehci@50000 { + usb@50000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts index e3b41784c876..051579fc36b8 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts @@ -63,7 +63,7 @@ status = "okay"; }; - ehci@50000 { + usb@50000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi index 47f03c69c55a..9d7cff4feada 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-openrd.dtsi @@ -53,7 +53,7 @@ cd-gpios = <&gpio0 29 9>; }; gpio@10100 { - p28 { + p28-hog { gpio-hog; gpios = <28 GPIO_ACTIVE_HIGH>; /* @@ -71,7 +71,7 @@ }; }; gpio@10140 { - p2 { + p2-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; /* diff --git a/arch/arm/boot/dts/marvell/kirkwood.dtsi b/arch/arm/boot/dts/marvell/kirkwood.dtsi index 815ef7719d13..8a1338e672b3 100644 --- a/arch/arm/boot/dts/marvell/kirkwood.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood.dtsi @@ -263,7 +263,7 @@ status = "okay"; }; - usb0: ehci@50000 { + usb0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x1000>; interrupts = <19>; diff --git a/arch/arm/boot/dts/marvell/orion5x.dtsi b/arch/arm/boot/dts/marvell/orion5x.dtsi index 2d41f5c166ee..939259c57e05 100644 --- a/arch/arm/boot/dts/marvell/orion5x.dtsi +++ b/arch/arm/boot/dts/marvell/orion5x.dtsi @@ -146,7 +146,7 @@ status = "okay"; }; - ehci0: ehci@50000 { + ehci0: usb@50000 { compatible = "marvell,orion-ehci"; reg = <0x50000 0x1000>; interrupts = <17>; @@ -218,7 +218,7 @@ status = "okay"; }; - ehci1: ehci@a0000 { + ehci1: usb@a0000 { compatible = "marvell,orion-ehci"; reg = <0xa0000 0x1000>; interrupts = <12>; diff --git a/arch/arm/boot/dts/mediatek/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts index 4c76366aa938..e97dc37f716c 100644 --- a/arch/arm/boot/dts/mediatek/mt2701-evb.dts +++ b/arch/arm/boot/dts/mediatek/mt2701-evb.dts @@ -50,6 +50,7 @@ bt_sco_codec:bt_sco_codec { compatible = "linux,bt-sco"; + #sound-dai-cells = <0>; }; backlight_lcd: backlight_lcd { diff --git a/arch/arm/boot/dts/microchip/aks-cdu.dts b/arch/arm/boot/dts/microchip/aks-cdu.dts index b65f80e1ef05..302cb872efa1 100644 --- a/arch/arm/boot/dts/microchip/aks-cdu.dts +++ b/arch/arm/boot/dts/microchip/aks-cdu.dts @@ -56,7 +56,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/animeo_ip.dts b/arch/arm/boot/dts/microchip/animeo_ip.dts index 7f527622d3f2..c11f4f7dac94 100644 --- a/arch/arm/boot/dts/microchip/animeo_ip.dts +++ b/arch/arm/boot/dts/microchip/animeo_ip.dts @@ -136,7 +136,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/microchip/at91-foxg20.dts b/arch/arm/boot/dts/microchip/at91-foxg20.dts index 9dfd5de808d1..8e9e87665045 100644 --- a/arch/arm/boot/dts/microchip/at91-foxg20.dts +++ b/arch/arm/boot/dts/microchip/at91-foxg20.dts @@ -131,7 +131,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-qil_a9260.dts b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts index 5ccb3c139592..892dbd8dbbed 100644 --- a/arch/arm/boot/dts/microchip/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/microchip/at91-qil_a9260.dts @@ -114,7 +114,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts index 2fb51b9aca2a..49dc1a4ccb36 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9_l9260.dts @@ -105,7 +105,7 @@ status = "okay"; }; - usb0: ohci@500000 { + usb0: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts index f3ffb8f01d8a..45edf6214cf7 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts @@ -37,7 +37,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ &pioA PIN_PA27 GPIO_ACTIVE_HIGH @@ -48,7 +48,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts index e4ae60ef5f8a..10d69f6957cf 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_ptc_ek.dts @@ -47,7 +47,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioA PIN_PB12 GPIO_ACTIVE_HIGH @@ -58,7 +58,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts index 4bab3f25b855..7e77a55ed41d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_xplained.dts @@ -46,7 +46,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ &pioA PIN_PB10 GPIO_ACTIVE_HIGH @@ -57,7 +57,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts index 5662992cf213..d2c43957497d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d3_xplained.dts @@ -283,7 +283,7 @@ status = "okay"; }; - usb1: ohci@600000 { + usb1: usb@600000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 3 GPIO_ACTIVE_LOW @@ -294,7 +294,7 @@ status = "okay"; }; - usb2: ehci@700000 { + usb2: usb@700000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts index 8adf567f2f0f..b9725e400501 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_ma5d4evk.dts @@ -22,7 +22,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -31,7 +31,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts index 95d701d13fef..0ecccb9a809d 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d4_xplained.dts @@ -164,7 +164,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_HIGH @@ -175,7 +175,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts index 20ac775059ca..69107d6cd26c 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d4ek.dts @@ -198,7 +198,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ &pioE 11 GPIO_ACTIVE_LOW @@ -207,7 +207,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 0f86360fb733..53a657cf4efb 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -30,6 +30,27 @@ device_type = "memory"; reg = <0x60000000 0x40000000>; }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + +}; + +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; }; &flx6 { @@ -43,11 +64,259 @@ status = "okay"; }; +&flx10 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; +}; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0_default + &pinctrl_gmac0_mdio_default + &pinctrl_gmac0_txck_default + &pinctrl_gmac0_phy_irq>; + phy-mode = "rgmii-id"; + nvmem-cells = <&eeprom0_eui48>; + nvmem-cell-names = "mac-address"; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioa>; + interrupts = <PIN_PC1 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c10 { + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "okay"; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <47000>; + label = "VDD3V3"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDIODDR"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDCORE"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDCPU"; + }; + }; + + pmic@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + lvin-supply = <®_5v>; + pvin1-supply = <®_5v>; + pvin2-supply = <®_5v>; + pvin3-supply = <®_5v>; + pvin4-supply = <®_5v>; + status = "okay"; + + regulators { + vdd_3v3: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddioddr: VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1350000>; + regulator-mode = <4>; + }; + }; + + vddcore: VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vddcpu: VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1250000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-ramp-delay = <3125>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1050000>; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + vldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-standby { + regulator-suspend-microvolt = <1800000>; + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + eeprom0: eeprom@51 { + compatible = "microchip,24aa025e48"; + reg = <0x51>; + size = <256>; + pagesize = <16>; + vcc-supply = <&vdd_3v3>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom0_eui48: eui48@fa { + reg = <0xfa 0x6>; + }; + }; + }; +}; + &main_xtal { clock-frequency = <24000000>; }; &pioa { + pinctrl_gmac0_default: gmac0-default { + pinmux = <PIN_PA26__G0_TX0>, + <PIN_PA27__G0_TX1>, + <PIN_PB4__G0_TX2>, + <PIN_PB5__G0_TX3>, + <PIN_PA29__G0_RX0>, + <PIN_PA30__G0_RX1>, + <PIN_PB2__G0_RX2>, + <PIN_PB6__G0_RX3>, + <PIN_PA25__G0_TXCTL>, + <PIN_PB3__G0_RXCK>, + <PIN_PA28__G0_RXCTL>; + slew-rate = <0>; + bias-disable; + }; + + pinctrl_gmac0_mdio_default: gmac0-mdio-default { + pinmux = <PIN_PA31__G0_MDC>, + <PIN_PB0__G0_MDIO>; + bias-disable; + }; + + pinctrl_gmac0_phy_irq: gmac0-phy-irq { + pinmux = <PIN_PC1__GPIO>; + bias-disable; + }; + + pinctrl_gmac0_txck_default: gmac0-txck-default { + pinmux = <PIN_PB1__G0_REFCK>; + slew-rate = <0>; + bias-pull-up; + }; + + pinctrl_i2c10_default: i2c10-default{ + pinmux = <PIN_PB19__FLEXCOM10_IO1>, + <PIN_PB20__FLEXCOM10_IO0>; + bias-pull-up; + }; + pinctrl_sdmmc1_default: sdmmc1-default { cmd-data { pinmux = <PIN_PB22__SDMMC1_CMD>, @@ -77,6 +346,10 @@ }; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + &sdmmc1 { bus-width = <4>; pinctrl-names = "default"; @@ -84,6 +357,15 @@ status = "okay"; }; +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + &slow_xtal { clock-frequency = <32768>; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts index 2dec2218f32c..eb5f27ce1942 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts @@ -369,6 +369,38 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; + label = "at91-qspi"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "qspi1: at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "qspi1: u-boot"; + reg = <0x40000 0x100000>; + }; + + bootloaderenv@140000 { + label = "qspi1: u-boot env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "qspi1: device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "qspi1: kernel"; + reg = <0x200000 0x600000>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts index 0f5e6ad438dd..2543599013b1 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -137,6 +137,7 @@ vref-supply = <&vddout25>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91-vinco.dts b/arch/arm/boot/dts/microchip/at91-vinco.dts index ecbdacf48708..c5fc51667066 100644 --- a/arch/arm/boot/dts/microchip/at91-vinco.dts +++ b/arch/arm/boot/dts/microchip/at91-vinco.dts @@ -162,7 +162,7 @@ status = "disabled"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -171,7 +171,7 @@ status = "disabled"; }; - usb2: ehci@600000 { + usb2: usb@600000 { /* 4G Modem */ status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi index 02a838541dc3..2a4c83d88733 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -702,7 +702,7 @@ status = "disabled"; }; - usb0: ohci@300000 { + usb0: usb@300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91rm9200ek.dts b/arch/arm/boot/dts/microchip/at91rm9200ek.dts index 0bf472b157a5..ce691c4692b9 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200ek.dts +++ b/arch/arm/boot/dts/microchip/at91rm9200ek.dts @@ -89,7 +89,7 @@ }; }; - usb0: ohci@300000 { + usb0: usb@300000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi index 0038183e9a53..ec973f07a961 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -742,7 +742,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9260ek.dts b/arch/arm/boot/dts/microchip/at91sam9260ek.dts index e8e65e60564d..8522a210b484 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9260ek.dts @@ -131,7 +131,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi index b57a7fd67197..0b556c234557 100644 --- a/arch/arm/boot/dts/microchip/at91sam9261.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi @@ -77,7 +77,7 @@ #size-cells = <1>; ranges; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9261ek.dts b/arch/arm/boot/dts/microchip/at91sam9261ek.dts index a8f523131cd6..313bc2797fde 100644 --- a/arch/arm/boot/dts/microchip/at91sam9261ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9261ek.dts @@ -31,7 +31,7 @@ }; ahb { - usb0: ohci@500000 { + usb0: usb@500000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9263.dtsi b/arch/arm/boot/dts/microchip/at91sam9263.dtsi index b95d4016ae9f..3e9e5ce7c6c8 100644 --- a/arch/arm/boot/dts/microchip/at91sam9263.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9263.dtsi @@ -768,7 +768,7 @@ status = "disabled"; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9263ek.dts b/arch/arm/boot/dts/microchip/at91sam9263ek.dts index f25692543d71..93c5268a0845 100644 --- a/arch/arm/boot/dts/microchip/at91sam9263ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9263ek.dts @@ -152,7 +152,7 @@ nand@3 { reg = <0x3 0x0 0x800000>; rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; nand-bus-width = <8>; nand-ecc-mode = "soft"; nand-on-flash-bbt; @@ -207,7 +207,7 @@ }; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { num-ports = <2>; status = "okay"; atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH diff --git a/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi index 4e7cfbbd4241..84a7287107f8 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek_common.dtsi @@ -211,7 +211,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi index 157d306ef5c9..535e26e05e99 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi @@ -964,7 +964,7 @@ status = "disabled"; }; - usb0: ohci@700000 { + usb0: usb@700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -973,7 +973,7 @@ status = "disabled"; }; - usb1: ehci@800000 { + usb1: usb@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts index 071db4f16313..2a31b2f14893 100644 --- a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts @@ -303,14 +303,14 @@ }; }; - usb0: ohci@700000 { + usb0: usb@700000 { status = "okay"; num-ports = <2>; atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW &pioD 3 GPIO_ACTIVE_LOW>; }; - usb1: ehci@800000 { + usb1: usb@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi index 844bd50943fc..2f930c39ce4d 100644 --- a/arch/arm/boot/dts/microchip/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9n12.dtsi @@ -748,7 +748,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/at91sam9n12ek.dts b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts index 643c3b2ab97e..b06a54e8e237 100644 --- a/arch/arm/boot/dts/microchip/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9n12ek.dts @@ -180,7 +180,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <1>; atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi index 27c1f2861cc3..17bdf1e4db01 100644 --- a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi @@ -886,7 +886,7 @@ }; }; - usb0: ohci@600000 { + usb0: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -895,7 +895,7 @@ status = "disabled"; }; - usb1: ehci@700000 { + usb1: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/ethernut5.dts b/arch/arm/boot/dts/microchip/ethernut5.dts index ad7a0850252a..52ccef31b391 100644 --- a/arch/arm/boot/dts/microchip/ethernut5.dts +++ b/arch/arm/boot/dts/microchip/ethernut5.dts @@ -101,7 +101,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/evk-pro3.dts b/arch/arm/boot/dts/microchip/evk-pro3.dts index 6d519d02d190..40c5111c2f0a 100644 --- a/arch/arm/boot/dts/microchip/evk-pro3.dts +++ b/arch/arm/boot/dts/microchip/evk-pro3.dts @@ -45,7 +45,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/mpa1600.dts b/arch/arm/boot/dts/microchip/mpa1600.dts index 005c2758e229..2a97e2c0b894 100644 --- a/arch/arm/boot/dts/microchip/mpa1600.dts +++ b/arch/arm/boot/dts/microchip/mpa1600.dts @@ -57,7 +57,7 @@ }; }; - usb0: ohci@300000 { + usb0: usb@300000 { num-ports = <1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/microchip/pm9g45.dts b/arch/arm/boot/dts/microchip/pm9g45.dts index c349fd3758a6..2258e62f5864 100644 --- a/arch/arm/boot/dts/microchip/pm9g45.dts +++ b/arch/arm/boot/dts/microchip/pm9g45.dts @@ -139,12 +139,12 @@ }; }; - usb0: ohci@700000 { + usb0: usb@700000 { status = "okay"; num-ports = <2>; }; - usb1: ehci@800000 { + usb1: usb@800000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index b8b2c1ddf3f1..b075865e6a76 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -88,7 +88,7 @@ status = "disabled"; }; - usb1: ohci@600000 { + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -97,7 +97,7 @@ status = "disabled"; }; - usb2: ehci@700000 { + usb2: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi index 3f99451aef83..dc22fb679333 100644 --- a/arch/arm/boot/dts/microchip/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -136,7 +136,7 @@ status = "disabled"; }; - usb1: ohci@400000 { + usb1: usb@400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -145,7 +145,7 @@ status = "disabled"; }; - usb2: ehci@500000 { + usb2: usb@500000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi index 70f380c399ce..e95799c17fdb 100644 --- a/arch/arm/boot/dts/microchip/sama5d3.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -1074,7 +1074,7 @@ status = "disabled"; }; - usb1: ohci@600000 { + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1083,7 +1083,7 @@ status = "disabled"; }; - usb2: ehci@700000 { + usb2: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi index 3652c9e24124..90da04b84b39 100644 --- a/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3xmb.dtsi @@ -172,7 +172,7 @@ status = "okay"; }; - usb1: ohci@600000 { + usb1: usb@600000 { num-ports = <3>; atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH &pioD 26 GPIO_ACTIVE_LOW @@ -181,7 +181,7 @@ status = "okay"; }; - usb2: ehci@700000 { + usb2: usb@700000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi index 355132628604..59a7d557c7cb 100644 --- a/arch/arm/boot/dts/microchip/sama5d4.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -119,7 +119,7 @@ status = "disabled"; }; - usb1: ohci@500000 { + usb1: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -128,7 +128,7 @@ status = "disabled"; }; - usb2: ehci@600000 { + usb2: usb@600000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 854b30d15dcd..d08d773b1cc5 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -9,6 +9,7 @@ */ #include <dt-bindings/clock/at91.h> +#include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -46,12 +47,42 @@ }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x20000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + soc { compatible = "simple-bus"; ranges; #address-cells = <1>; #size-cells = <1>; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + ranges = <0 0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + }; + + secumod: security-module@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + + sfrbu: sfr@e0008000 { + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -76,6 +107,38 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + ps_wdt: watchdog@e001d000 { + compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; + reg = <0xe001d000 0x30>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k 0>; + }; + + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + + shdwc: poweroff@e001d200 { + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d200 0x20>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + + rtt: rtc@e001d300 { + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; + reg = <0xe001d300 0x30>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -83,6 +146,34 @@ #clock-cells = <1>; }; + gpbr: syscon@e001d700 { + compatible = "microchip,sama7d65-gpbr", "syscon"; + reg = <0xe001d700 0x48>; + }; + + rtc: rtc@e001d800 { + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d800 0x30>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k 1>; + }; + + chipid@e0020000 { + compatible = "microchip,sama7d65-chipid"; + reg = <0xe0020000 0x8>; + }; + + dma2: dma-controller@e1200000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1200000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "dma_clk"; + dma-requests = <0>; + status = "disabled"; + }; + sdmmc1: mmc@e1208000 { compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; reg = <0xe1208000 0x400>; @@ -95,6 +186,58 @@ status = "disabled"; }; + dma0: dma-controller@e1610000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1610000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + dma1: dma-controller@e1614000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1614000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + gmac0: ethernet@e1618000 { + compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; + reg = <0xe1618000 0x2000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; + assigned-clock-rates = <125000000>, <200000000>; + status = "disabled"; + }; + + gmac1: ethernet@e161c000 { + compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; + reg = <0xe161c000 0x2000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; + assigned-clock-rates = <125000000>, <200000000>; + status = "disabled"; + }; + pit64b0: timer@e1800000 { compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x100>; @@ -111,6 +254,199 @@ clock-names = "pclk", "gclk"; }; + flx0: flexcom@e1820000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe1820000 0x200>; + ranges = <0x0 0xe1820000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>, + <&dma0 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + }; + + flx1: flexcom@e1824000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe1824000 0x200>; + ranges = <0x0 0xe1824000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + spi1: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx2: flexcom@e1828000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe1828000 0x200>; + ranges = <0x0 0xe1828000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + }; + + flx3: flexcom@e182c000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe182c000 0x200>; + ranges = <0x0 0xe182c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c3: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + #address-cells = <1>; + #size-cells = <1>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + }; + + flx4: flexcom@e2018000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2018000 0x200>; + ranges = <0x0 0xe2018000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>, + <&dma0 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx5: flexcom@e201c000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe201c000 0x200>; + ranges = <0x0 0xe201c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c5: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + flx6: flexcom@e2020000 { compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg = <0xe2020000 0x200>; @@ -132,6 +468,111 @@ }; }; + flx7: flexcom@e2024000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2024000 0x200>; + ranges = <0x0 0xe2024000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + status = "disabled"; + }; + }; + + flx8: flexcom@e281c000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe281c000 0x200>; + ranges = <0x0 0xe281c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c8: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx9: flexcom@e2820000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2820000 0x200>; + ranges = <0x0 0xe281c000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c9: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + flx10: flexcom@e2824000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2824000 0x200>; + ranges = <0x0 0xe2824000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>, diff --git a/arch/arm/boot/dts/microchip/tny_a9260.dts b/arch/arm/boot/dts/microchip/tny_a9260.dts index ef6d586ce887..f0f2a787d669 100644 --- a/arch/arm/boot/dts/microchip/tny_a9260.dts +++ b/arch/arm/boot/dts/microchip/tny_a9260.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board + * tny_a9260.dts - Device Tree file for Calao TNY A9260 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi index 70e5635c78ed..4d4377f51bec 100644 --- a/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/microchip/tny_a9260_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board + * tny_a9260_common.dtsi - Device Tree file for Calao TNY A926x board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/tny_a9263.dts b/arch/arm/boot/dts/microchip/tny_a9263.dts index 62b7d9f9a926..fd8244b56e05 100644 --- a/arch/arm/boot/dts/microchip/tny_a9263.dts +++ b/arch/arm/boot/dts/microchip/tny_a9263.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * usb_a9263.dts - Device Tree file for Calao USB A9293 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ @@ -64,7 +64,7 @@ nand@3 { reg = <0x3 0x0 0x800000>; rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; nand-bus-width = <8>; nand-ecc-mode = "soft"; nand-on-flash-bbt; diff --git a/arch/arm/boot/dts/microchip/tny_a9g20.dts b/arch/arm/boot/dts/microchip/tny_a9g20.dts index 118d766a1265..cebd5696a2c1 100644 --- a/arch/arm/boot/dts/microchip/tny_a9g20.dts +++ b/arch/arm/boot/dts/microchip/tny_a9g20.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board + * tny_a9g20.dts - Device Tree file for Calao TNY A9G20 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ diff --git a/arch/arm/boot/dts/microchip/usb_a9260.dts b/arch/arm/boot/dts/microchip/usb_a9260.dts index 66f8da89007d..3b61e7145060 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260.dts +++ b/arch/arm/boot/dts/microchip/usb_a9260.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9260.dts - Device Tree file for Caloa USB A9260 board + * usb_a9260.dts - Device Tree file for Calao USB A9260 board * * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ @@ -12,14 +12,6 @@ model = "Calao USB A9260"; compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9"; - chosen { - bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - ahb { apb { shdwc: poweroff@fffffd10 { diff --git a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi index 8744b5f6f792..da32c5fdcc47 100644 --- a/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9260_common.dtsi @@ -1,11 +1,16 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a926x.dts - Device Tree file for Caloa USB A926x board + * usb_a926x.dts - Device Tree file for Calao USB A926x board * * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ / { + chosen { + bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; + stdout-path = "serial0:115200n8"; + }; + clocks { slow_xtal { clock-frequency = <32768>; @@ -16,6 +21,10 @@ }; }; + memory@20000000 { + reg = <0x20000000 0x4000000>; + }; + ahb { apb { dbgu: serial@fffff200 { @@ -111,7 +120,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; @@ -122,17 +131,14 @@ user_led { label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user-pb { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/microchip/usb_a9263.dts b/arch/arm/boot/dts/microchip/usb_a9263.dts index 45745915b2e1..8e1a3fb61087 100644 --- a/arch/arm/boot/dts/microchip/usb_a9263.dts +++ b/arch/arm/boot/dts/microchip/usb_a9263.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * usb_a9263.dts - Device Tree file for Calao USB A9293 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ @@ -9,7 +9,7 @@ / { model = "Calao USB A9263"; - compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; + compatible = "calao,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; chosen { bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; @@ -58,7 +58,7 @@ }; spi0: spi@fffa4000 { - cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioA 5 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { compatible = "atmel,at45", "atmel,dataflash"; @@ -84,7 +84,7 @@ nand@3 { reg = <0x3 0x0 0x800000>; rb-gpios = <&pioA 22 GPIO_ACTIVE_HIGH>; - cs-gpios = <&pioA 15 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; nand-bus-width = <8>; nand-ecc-mode = "soft"; nand-on-flash-bbt; @@ -139,7 +139,7 @@ }; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { num-ports = <2>; status = "okay"; }; @@ -151,16 +151,13 @@ user_led { label = "user_led"; gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user-pb { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi index 08d58081201a..5b1d80c0ab26 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi +++ b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi @@ -65,28 +65,26 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb1 { + button-user-pb1 { label = "user_pb1"; gpios = <&pioB 25 GPIO_ACTIVE_LOW>; linux,code = <0x100>; }; - user_pb2 { + button-user-pb2 { label = "user_pb2"; gpios = <&pioB 13 GPIO_ACTIVE_LOW>; linux,code = <0x101>; }; - user_pb3 { + button-user-pb3 { label = "user_pb3"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <0x102>; }; - user_pb4 { + button-user-pb4 { label = "user_pb4"; gpios = <&pioC 9 GPIO_ACTIVE_LOW>; linux,code = <0x103>; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20.dts b/arch/arm/boot/dts/microchip/usb_a9g20.dts index 2f667b083e81..555291cd30b3 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20.dts @@ -1,13 +1,28 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * usb_a9g20.dts - Device Tree file for Calao USB A9G20 board * * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ /dts-v1/; -#include "usb_a9g20_common.dtsi" +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9G20"; compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9"; }; + +&spi0 { + cs-gpios = <&pioC 11 GPIO_ACTIVE_LOW>; + status = "okay"; + /* TODO: Some revisions might have a dataflash here instead of an EEPROM */ + eeprom@0 { + compatible = "st,m95640", "atmel,at25"; + reg = <0>; + spi-max-frequency = <2000000>; + size = <8192>; + pagesize = <32>; + address-width = <16>; + }; +}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi deleted file mode 100644 index 7d10b36db1ee..000000000000 --- a/arch/arm/boot/dts/microchip/usb_a9g20_common.dtsi +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - */ - -#include "at91sam9g20.dtsi" -#include "usb_a9260_common.dtsi" - -/ { - chosen { - bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs"; - stdout-path = "serial0:115200n8"; - }; - - memory@20000000 { - reg = <0x20000000 0x4000000>; - }; - - i2c-gpio-0 { - rtc@56 { - compatible = "microcrystal,rv3029"; - reg = <0x56>; - }; - }; -}; diff --git a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts index f65712015d40..2eda00477bc5 100644 --- a/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts +++ b/arch/arm/boot/dts/microchip/usb_a9g20_lpw.dts @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board + * usb_a9g20_lpw.dts - Device Tree file for Calao USB A9G20 Low Power board * * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> */ /dts-v1/; -#include "usb_a9g20_common.dtsi" +#include "at91sam9g20.dtsi" +#include "usb_a9260_common.dtsi" / { model = "Calao USB A9G20 Low Power"; @@ -16,7 +17,7 @@ spi1: spi@fffcc000 { cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; status = "okay"; - mmc-slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3200 3400>; @@ -27,4 +28,11 @@ }; }; }; + + i2c-gpio-0 { + rtc@56 { + compatible = "microcrystal,rv3029"; + reg = <0x56>; + }; + }; }; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index 868454ae6bde..791090f54d8b 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -99,6 +99,11 @@ }; }; + udc0_phy: usb-phy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + ahb { #address-cells = <1>; #size-cells = <1>; @@ -122,6 +127,13 @@ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; }; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0xf0824000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + gmac0: eth@f0802000 { device_type = "network"; compatible = "snps,dwmac"; @@ -137,6 +149,29 @@ status = "disabled"; }; + sdmmc: mmc@f0842000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0842000 0x200>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc8_pins + &mmc_pins>; + }; + + sdhci: mmc@f0840000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0840000 0x200>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_sdhc"; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pins>; + }; + ehci1: usb@f0806000 { compatible = "nuvoton,npcm750-ehci"; reg = <0xf0806000 0x1000>; @@ -144,6 +179,13 @@ status = "disabled"; }; + ohci1: usb@f0807000 { + compatible = "generic-ohci"; + reg = <0xf0807000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + fiu0: spi@fb000000 { compatible = "nuvoton,npcm750-fiu"; #address-cells = <1>; @@ -179,6 +221,72 @@ status = "disabled"; }; + udc5: usb@f0835000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0835000 0x1000 + 0xfffd2800 0x800>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc6: usb@f0836000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0836000 0x1000 + 0xfffd3000 0x800>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc7: usb@f0837000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0837000 0x1000 + 0xfffd3800 0x800>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc8: usb@f0838000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0838000 0x1000 + 0xfffd4000 0x800>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc9: usb@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd4800 0x800>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + nuvoton,sysgcr = <&gcr>; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts index c3501786d600..231228842e63 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts @@ -1050,19 +1050,19 @@ "","","","SIO_POWER_GOOD","","","",""; }; gpio2: gpio@f0012000 { - bmc_usb_mux_oe_n { + bmc-usb-mux-oe-n-hog { gpio-hog; gpios = <25 GPIO_ACTIVE_HIGH>; output-low; line-name = "bmc-usb-mux-oe-n"; }; - bmc_usb_mux_sel { + bmc-usb-mux-sel-hog { gpio-hog; gpios = <26 GPIO_ACTIVE_HIGH>; output-low; line-name = "bmc-usb-mux-sel"; }; - bmc_usb2517_reset_n { + bmc-usb2517-reset-n-hog { gpio-hog; gpios = <27 GPIO_ACTIVE_LOW>; output-low; @@ -1070,19 +1070,19 @@ }; }; gpio3: gpio@f0013000 { - assert_cpu0_reset { + assert-cpu0-reset-hog { gpio-hog; gpios = <14 GPIO_ACTIVE_HIGH>; output-low; line-name = "assert-cpu0-reset"; }; - assert_pwrok_cpu0_n { + assert-pwrok-cpu0-n-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_HIGH>; output-low; line-name = "assert-pwrok-cpu0-n"; }; - assert_cpu0_prochot { + assert-cpu0-prochot-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts index f67ede148209..0c94e14d40e8 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -427,91 +427,91 @@ gpio-controller; #gpio-cells = <2>; reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; - G1A_P0_0 { + g1a-p0-0-hog { gpio-hog; gpios = <0 0>; output-high; line-name = "TPM_BMC_ALERT_N"; }; - G1A_P0_1 { + g1a-p0-1-hog { gpio-hog; gpios = <1 0>; input; line-name = "FM_BIOS_TOP_SWAP"; }; - G1A_P0_2 { + g1a-p0-2-hog { gpio-hog; gpios = <2 0>; input; line-name = "FM_BIOS_PREFRB2_GOOD"; }; - G1A_P0_3 { + g1a-p0-3-hog { gpio-hog; gpios = <3 0>; input; line-name = "BMC_SATAXPCIE_0TO3_SEL"; }; - G1A_P0_4 { + g1a-p0-4-hog { gpio-hog; gpios = <4 0>; input; line-name = "BMC_SATAXPCIE_4TO7_SEL"; }; - G1A_P0_5 { + g1a-p0-5-hog { gpio-hog; gpios = <5 0>; output-low; line-name = "FM_UV_ADR_TRIGGER_EN_N"; }; - G1A_P0_6 { + g1a-p0-6-hog { gpio-hog; gpios = <6 0>; input; line-name = "RM_THROTTLE_EN_N"; }; - G1A_P1_0 { + g1a-p1-0-hog { gpio-hog; gpios = <8 0>; input; line-name = "FM_BMC_TPM_PRES_N"; }; - G1A_P1_1 { + g1a-p1-1-hog { gpio-hog; gpios = <9 0>; input; line-name = "FM_CPU0_SKTOCC_LVT3_N"; }; - G1A_P1_2 { + g1a-p1-2-hog { gpio-hog; gpios = <10 0>; input; line-name = "FM_CPU1_SKTOCC_LVT3_N"; }; - G1A_P1_3 { + g1a-p1-3-hog { gpio-hog; gpios = <11 0>; input; line-name = "PSU1_ALERT_N"; }; - G1A_P1_4 { + g1a-p1-4-hog { gpio-hog; gpios = <12 0>; input; line-name = "PSU2_ALERT_N"; }; - G1A_P1_5 { + g1a-p1-5-hog { gpio-hog; gpios = <13 0>; input; line-name = "H_CPU0_FAST_WAKE_LVT3_N"; }; - G1A_P1_6 { + g1a-p1-6-hog { gpio-hog; gpios = <14 0>; output-high; line-name = "I2C_MUX1_RESET_N"; }; - G1A_P1_7 { + g1a-p1-7-hog { gpio-hog; gpios = <15 0>; input; @@ -524,91 +524,91 @@ reg = <0x75>; gpio-controller; #gpio-cells = <2>; - G1B_P0_0 { + g1b-p0-0-hog { gpio-hog; gpios = <0 0>; input; line-name = "PVDDQ_ABC_PINALERT_N"; }; - G1B_P0_1 { + g1b-p0-1-hog { gpio-hog; gpios = <1 0>; input; line-name = "PVDDQ_DEF_PINALERT_N"; }; - G1B_P0_2 { + g1b-p0-2-hog { gpio-hog; gpios = <2 0>; input; line-name = "PVDDQ_GHJ_PINALERT_N"; }; - G1B_P0_3 { + g1b-p0-3-hog { gpio-hog; gpios = <3 0>; input; line-name = "PVDDQ_KLM_PINALERT_N"; }; - G1B_P0_5 { + g1b-p0-5-hog { gpio-hog; gpios = <5 0>; input; line-name = "FM_BOARD_REV_ID0"; }; - G1B_P0_6 { + g1b-p0-6-hog { gpio-hog; gpios = <6 0>; input; line-name = "FM_BOARD_REV_ID1"; }; - G1B_P0_7 { + g1b-p0-7-hog { gpio-hog; gpios = <7 0>; input; line-name = "FM_BOARD_REV_ID2"; }; - G1B_P1_0 { + g1b-p1-0-hog { gpio-hog; gpios = <8 0>; input; line-name = "FM_OC_DETECT_EN_N"; }; - G1B_P1_1 { + g1b-p1-1-hog { gpio-hog; gpios = <9 0>; input; line-name = "FM_FLASH_DESC_OVERRIDE"; }; - G1B_P1_2 { + g1b-p1-2-hog { gpio-hog; gpios = <10 0>; output-low; line-name = "FP_PWR_ID_LED_N"; }; - G1B_P1_3 { + g1b-p1-3-hog { gpio-hog; gpios = <11 0>; output-low; line-name = "BMC_LED_PWR_GRN"; }; - G1B_P1_4 { + g1b-p1-4-hog { gpio-hog; gpios = <12 0>; output-low; line-name = "BMC_LED_PWR_AMBER"; }; - G1B_P1_5 { + g1b-p1-5-hog { gpio-hog; gpios = <13 0>; output-high; line-name = "FM_BMC_FAULT_LED_N"; }; - G1B_P1_6 { + g1b-p1-6-hog { gpio-hog; gpios = <14 0>; output-high; line-name = "FM_CPLD_BMC_PWRDN_N"; }; - G1B_P1_7 { + g1b-p1-7-hog { gpio-hog; gpios = <15 0>; output-high; @@ -626,91 +626,91 @@ gpio-controller; #gpio-cells = <2>; reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; - G2A_P0_0 { + g2a-p0-0-hog { gpio-hog; gpios = <0 0>; output-high; line-name = "BMC_PON_RST_REQ_N"; }; - G2A_P0_1 { + g2a-p0-1-hog { gpio-hog; gpios = <1 0>; output-high; line-name = "BMC_RST_IND_REQ_N"; }; - G2A_P0_2 { + g2a-p0-2-hog { gpio-hog; gpios = <2 0>; input; line-name = "RST_BMC_RTCRST"; }; - G2A_P0_3 { + g2a-p0-3-hog { gpio-hog; gpios = <3 0>; output-high; line-name = "FM_BMC_PWRBTN_OUT_N"; }; - G2A_P0_4 { + g2a-p0-4-hog { gpio-hog; gpios = <4 0>; output-high; line-name = "RST_BMC_SYSRST_BTN_OUT_N"; }; - G2A_P0_5 { + g2a-p0-5-hog { gpio-hog; gpios = <5 0>; output-high; line-name = "FM_BATTERY_SENSE_EN_N"; }; - G2A_P0_6 { + g2a-p0-6-hog { gpio-hog; gpios = <6 0>; output-high; line-name = "FM_BMC_READY_N"; }; - G2A_P0_7 { + g2a-p0-7-hog { gpio-hog; gpios = <7 0>; input; line-name = "IRQ_BMC_PCH_SMI_LPC_N"; }; - G2A_P1_0 { + g2a-p1-0-hog { gpio-hog; gpios = <8 0>; input; line-name = "FM_SLOT4_CFG0"; }; - G2A_P1_1 { + g2a-p1-1-hog { gpio-hog; gpios = <9 0>; input; line-name = "FM_SLOT4_CFG1"; }; - G2A_P1_2 { + g2a-p1-2-hog { gpio-hog; gpios = <10 0>; input; line-name = "FM_NVDIMM_EVENT_N"; }; - G2A_P1_3 { + g2a-p1-3-hog { gpio-hog; gpios = <11 0>; input; line-name = "PSU1_BLADE_EN_N"; }; - G2A_P1_4 { + g2a-p1-4-hog { gpio-hog; gpios = <12 0>; input; line-name = "BMC_PCH_FNM"; }; - G2A_P1_5 { + g2a-p1-5-hog { gpio-hog; gpios = <13 0>; input; line-name = "FM_SOL_UART_CH_SEL"; }; - G2A_P1_6 { + g2a-p1-6-hog { gpio-hog; gpios = <14 0>; input; @@ -723,91 +723,91 @@ reg = <0x75>; gpio-controller; #gpio-cells = <2>; - G2B_P0_0 { + g2b-p0-0-hog { gpio-hog; gpios = <0 0>; input; line-name = "FM_CPU_MSMI_LVT3_N"; }; - G2B_P0_1 { + g2b-p0-1-hog { gpio-hog; gpios = <1 0>; input; line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; }; - G2B_P0_2 { + g2b-p0-2-hog { gpio-hog; gpios = <2 0>; input; line-name = "FM_CPU1_DISABLE_BMC_N"; }; - G2B_P0_3 { + g2b-p0-3-hog { gpio-hog; gpios = <3 0>; output-low; line-name = "BMC_JTAG_SELECT"; }; - G2B_P0_4 { + g2b-p0-4-hog { gpio-hog; gpios = <4 0>; output-high; line-name = "PECI_MUX_SELECT"; }; - G2B_P0_5 { + g2b-p0-5-hog { gpio-hog; gpios = <5 0>; output-high; line-name = "I2C_MUX2_RESET_N"; }; - G2B_P0_6 { + g2b-p0-6-hog { gpio-hog; gpios = <6 0>; input; line-name = "FM_BMC_CPLD_PSU2_ON"; }; - G2B_P0_7 { + g2b-p0-7-hog { gpio-hog; gpios = <7 0>; output-high; line-name = "PSU2_ALERT_EN_N"; }; - G2B_P1_0 { + g2b-p1-0-hog { gpio-hog; gpios = <8 0>; output-high; line-name = "FM_CPU_BMC_INIT"; }; - G2B_P1_1 { + g2b-p1-1-hog { gpio-hog; gpios = <9 0>; output-high; line-name = "IRQ_BMC_PCH_SCI_LPC_N"; }; - G2B_P1_2 { + g2b-p1-2-hog { gpio-hog; gpios = <10 0>; output-low; line-name = "PMB_ALERT_EN_N"; }; - G2B_P1_3 { + g2b-p1-3-hog { gpio-hog; gpios = <11 0>; output-high; line-name = "FM_FAST_PROCHOT_EN_N"; }; - G2B_P1_4 { + g2b-p1-4-hog { gpio-hog; gpios = <12 0>; output-high; line-name = "BMC_NVDIMM_PRSNT_N"; }; - G2B_P1_5 { + g2b-p1-5-hog { gpio-hog; gpios = <13 0>; output-low; line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; }; - G2B_P1_6 { + g2b-p1-6-hog { gpio-hog; gpios = <14 0>; output-high; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi index 30eed40b89b5..f42ad259636c 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi @@ -58,5 +58,70 @@ &rg2mdio_pins>; status = "disabled"; }; + + udc0: usb@f0830000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0830000 0x1000 + 0xfffd0000 0x800>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc1: usb@f0831000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0831000 0x1000 + 0xfffd0800 0x800>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc2: usb@f0832000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0832000 0x1000 + 0xfffd1000 0x800>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc3: usb@f0833000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0833000 0x1000 + 0xfffd1800 0x800>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; + + udc4: usb@f0834000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0834000 0x1000 + 0xfffd2000 0x800>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + phys = <&udc0_phy>; + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile index 96972559253c..ff2c5bfd8efa 100644 --- a/arch/arm/boot/dts/nvidia/Makefile +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -34,6 +34,7 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-asus-tf201.dtb \ tegra30-asus-tf300t.dtb \ tegra30-asus-tf300tg.dtb \ + tegra30-asus-tf300tl.dtb \ tegra30-asus-tf700t.dtb \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 86f14e2fd29f..4caf2073c556 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -139,7 +139,7 @@ reg = <0x54400000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIB>, <&tegra_car TEGRA114_CLK_DSIBLP>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 82>; reset-names = "dsi"; @@ -577,6 +577,21 @@ #iommu-cells = <1>; }; + hda@70030000 { + compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA114_CLK_HDA>, + <&tegra_car TEGRA114_CLK_HDA2HDMI>, + <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; + }; + ahub@70080000 { compatible = "nvidia,tegra114-ahub"; reg = <0x70080000 0x200>, @@ -805,31 +820,40 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts index 0f3debeb294b..1aa7265554d9 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts @@ -84,11 +84,6 @@ status = "okay"; clock-frequency = <400000>; - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - /* M41T0M6 real time clock on carrier board */ rtc@68 { compatible = "st,m41t0"; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts index d13b8d25ca6a..23158bb82173 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts @@ -85,11 +85,6 @@ status = "okay"; clock-frequency = <400000>; - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - /* M41T0M6 real time clock on carrier board */ rtc@68 { compatible = "st,m41t0"; diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi index 8f1fff373461..ec4f0e346b2b 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -165,6 +165,22 @@ status = "disabled"; }; + dsia: dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x0 0x54300000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + vic@54340000 { compatible = "nvidia,tegra124-vic"; reg = <0x0 0x54340000 0x0 0x00040000>; @@ -177,6 +193,22 @@ iommus = <&mc TEGRA_SWGROUP_VIC>; }; + dsib: dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x0 0x54400000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; @@ -938,6 +970,14 @@ }; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x0 0x700e3000 0x0 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + clock-names = "mipi-cal"; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0 0x70110000 0 0x100>, /* DFLL control */ diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index e118809dc6d9..67764afeb013 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -1085,6 +1085,17 @@ sbs,poll-retry-count = <10>; power-supplies = <&mains>; }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3000a"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&vdd_1v8_sys>; + }; }; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi index 8da75ccc4402..882adb7f2f26 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -284,7 +284,7 @@ reg = <0x60007000 0x1000>; }; - apbdma: dma@6000a000 { + apbdma: dma-controller@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts index fc284155cd76..ccb9f29c5de3 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts @@ -91,11 +91,6 @@ status = "okay"; clock-frequency = <400000>; - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - /* M41T0M6 real time clock on carrier board */ rtc@68 { compatible = "st,m41t0"; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts index 9d08e2b094b4..bc353324df43 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts @@ -92,11 +92,6 @@ status = "okay"; clock-frequency = <400000>; - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; - /* M41T0M6 real time clock on carrier board */ rtc@68 { compatible = "st,m41t0"; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tl.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tl.dts new file mode 100644 index 000000000000..2ef9d8737901 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf300tl.dts @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra30-asus-transformer-common.dtsi" +#include "tegra30-asus-lvds-display.dtsi" + +/ { + model = "Asus Transformer Pad LTE TF300TL"; + compatible = "asus,tf300tl", "nvidia,tegra30"; + + gpio@6000d000 { + tf300tl-init-hog { + gpio-hog; + gpios = <TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + output-low; + }; + }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + serial@70006200 { + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + }; + }; + + i2c@7000c400 { + /* Elantech EKTH1036 touchscreen */ + touchscreen@10 { + compatible = "elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vdd_3v3_sys>; + vccio-supply = <&vdd_3v3_sys>; + + touchscreen-size-x = <2240>; + touchscreen-size-y = <1408>; + touchscreen-inverted-y; + }; + }; + + i2c@7000c500 { + clock-frequency = <400000>; + + magnetometer@e { + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + + gyroscope@68 { + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + + /* External I2C interface */ + i2c-gate { + accelerometer@f { + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + }; + }; + }; + + i2c@7000d000 { + /* Realtek ALC5631 audio codec */ + rt5631: audio-codec@1a { + compatible = "realtek,rt5631"; + reg = <0x1a>; + }; + }; + + memory-controller@7000f000 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emem-configuration = < 0x00020001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x74830303 0x001f0000 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emem-configuration = < 0x00010001 0xc0000020 + 0x00000001 0x00000001 0x00000002 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0502 0x73430303 0x001f0000 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emem-configuration = < 0x00000001 0xc0000030 + 0x00000001 0x00000001 0x00000003 0x00000000 + 0x00000001 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0503 0x72830504 0x001f0000 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emem-configuration = < 0x00000003 0xc0000025 + 0x00000001 0x00000001 0x00000005 0x00000002 + 0x00000003 0x00000001 0x00000003 0x00000008 + 0x00000002 0x00000001 0x00000002 0x00000006 + 0x06020102 0x000a0505 0x72440a06 0x001f0000 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emem-configuration = < 0x00000005 0xc000003d + 0x00000001 0x00000002 0x00000008 0x00000004 + 0x00000004 0x00000001 0x00000002 0x00000007 + 0x00000002 0x00000002 0x00000003 0x00000006 + 0x06030202 0x000b0608 0x70850f09 0x001f0000 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < 0x0000000a 0xc0000079 + 0x00000003 0x00000004 0x00000010 0x0000000b + 0x0000000a 0x00000001 0x00000003 0x0000000b + 0x00000002 0x00000002 0x00000004 0x00000008 + 0x08040202 0x00130b10 0x70ea1f11 0x001f0000 >; + }; + }; + }; + + memory-controller@7000f400 { + emc-timings-0 { + /* Elpida 1GB 667MHZ */ + nvidia,ram-code = <0>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00050000 0x00050000 0x00050000 + 0x00050000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000001f + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00018000 0x00018000 0x00018000 + 0x00018000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0800013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x0a000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xe8000000 0xff00ff49 >; + }; + }; + + emc-timings-1 { + /* Hynix 1GB 667MHZ */ + nvidia,ram-code = <1>; + + timing-25500000 { + clock-frequency = <25500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000001 + 0x00000004 0x00000000 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x000000c0 0x00000000 0x00000030 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000005 0x00000005 + 0x00000004 0x00000001 0x00000000 0x00000004 + 0x00000005 0x000000c7 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000287 0xe8000000 0xff00ff00 >; + }; + + timing-51000000 { + clock-frequency = <51000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000002 + 0x00000008 0x00000001 0x00000000 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000000 + 0x00000000 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000181 0x00000000 0x00000060 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000009 0x00000009 + 0x00000004 0x00000002 0x00000000 0x00000004 + 0x00000005 0x0000018e 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x8000040b 0xe8000000 0xff00ff00 >; + }; + + timing-102000000 { + clock-frequency = <102000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000005 + 0x00000010 0x00000003 0x00000001 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000001 + 0x00000001 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000005 0x00000004 0x0000000a + 0x0000000b 0x00000303 0x00000000 0x000000c0 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000012 0x00000012 + 0x00000004 0x00000004 0x00000000 0x00000004 + 0x00000005 0x0000031c 0x00000006 0x00000004 + 0x00000000 0x00000000 0x00004288 0x007800a4 + 0x00008000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x000fc000 0x000fc000 0x000fc000 + 0x000fc000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00000000 + 0x00000040 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000713 0xe8000000 0xff00ff00 >; + }; + + timing-204000000 { + clock-frequency = <204000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200048>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x0000000a + 0x00000020 0x00000007 0x00000002 0x00000002 + 0x0000000a 0x00000005 0x0000000b 0x00000002 + 0x00000002 0x00000003 0x00000001 0x00000000 + 0x00000005 0x00000006 0x00000004 0x0000000a + 0x0000000b 0x00000607 0x00000000 0x00000181 + 0x00000002 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000f 0x00000023 0x00000023 + 0x00000004 0x00000007 0x00000000 0x00000004 + 0x00000005 0x00000638 0x00000007 0x00000004 + 0x00000000 0x00000000 0x00004288 0x004400a4 + 0x00008000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00080000 0x00080000 0x00080000 + 0x00080000 0x000002a0 0x0800211c 0x00000000 + 0x77fff884 0x01f1f108 0x05057404 0x54000007 + 0x08000168 0x08000000 0x00000802 0x00020000 + 0x00000100 0x000c000c 0xa0f10000 0x00000000 + 0x00000000 0x80000d22 0xe8000000 0xff00ff00 >; + }; + + timing-333500000 { + clock-frequency = <333500000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200040>; + nvidia,emc-mode-reset = <0x80000321>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + + nvidia,emc-configuration = < 0x0000000f + 0x00000034 0x0000000a 0x00000003 0x00000003 + 0x00000008 0x00000002 0x00000009 0x00000003 + 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000004 0x00000006 0x00000004 0x0000000a + 0x0000000c 0x000009e9 0x00000000 0x0000027a + 0x00000001 0x00000008 0x00000001 0x00000000 + 0x00000007 0x0000000e 0x00000039 0x00000200 + 0x00000004 0x0000000a 0x00000000 0x00000004 + 0x00000005 0x00000a2a 0x00000000 0x00000004 + 0x00000000 0x00000000 0x00007088 0x002600a4 + 0x00008000 0x0003c000 0x0003c000 0x0003c000 + 0x0003c000 0x00014000 0x00014000 0x00014000 + 0x00014000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00048000 0x00048000 0x00048000 + 0x00048000 0x000002a0 0x0800013d 0x00000000 + 0x77fff884 0x01f1f508 0x05057404 0x54000007 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x018b000c 0xa0f10000 0x00000000 + 0x00000000 0x800014d4 0xe8000000 0xff00ff89 >; + }; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200058>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + + nvidia,emc-configuration = < 0x00000020 + 0x00000069 0x00000017 0x00000007 0x00000005 + 0x0000000c 0x00000003 0x00000011 0x00000007 + 0x00000007 0x00000002 0x00000001 0x00000000 + 0x00000007 0x0000000b 0x00000009 0x0000000b + 0x00000011 0x00001412 0x00000000 0x00000504 + 0x00000002 0x0000000e 0x00000001 0x00000000 + 0x0000000c 0x00000016 0x00000072 0x00000200 + 0x00000005 0x00000015 0x00000000 0x00000006 + 0x00000007 0x00001453 0x0000000c 0x00000004 + 0x00000000 0x00000000 0x00005088 0xf00b0191 + 0x00008000 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x0000000a 0x0000000a 0x0000000a + 0x0000000a 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x0000000c 0x0000000c 0x0000000c + 0x0000000c 0x000002a0 0x0600013d 0x22220000 + 0x77fff884 0x01f1f501 0x07077404 0x54000000 + 0x080001e8 0x08000021 0x00000802 0x00020000 + 0x00000100 0x0156000c 0xa0f10000 0x00000000 + 0x00000000 0x800028a5 0xf8000000 0xff00ff49 >; + }; + }; + }; + + pad_battery: battery-pad { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + charge-full-design-microamp-hours = <2940000>; + energy-full-design-microwatt-hours = <22000000>; + operating-range-celsius = <0 45>; + }; + + dock_battery: battery-dock { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + charge-full-design-microamp-hours = <2260000>; + energy-full-design-microwatt-hours = <16000000>; + operating-range-celsius = <0 45>; + }; + + display-panel { + compatible = "innolux,g101ice-l01"; + }; + + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf300tl", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Pad TF300TL RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi index f866fa7b55a5..2a4d93db8134 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -431,7 +431,7 @@ reg = <0x60007000 0x1000>; }; - apbdma: dma@6000a000 { + apbdma: dma-controller@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 39a153536d2a..8b3abe817e12 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -69,6 +69,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-colibri-eval-v3.dtb \ imx6dl-colibri-iris.dtb \ imx6dl-colibri-iris-v2.dtb \ + imx6dl-colibri-v1.2-aster.dtb \ + imx6dl-colibri-v1.2-eval-v3.dtb \ + imx6dl-colibri-v1.2-iris.dtb \ + imx6dl-colibri-v1.2-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ @@ -158,6 +162,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ imx6q-apalis-ixora-v1.2.dtb \ + imx6q-apalis-v1.2-eval.dtb \ + imx6q-apalis-v1.2-eval-v1.2.dtb \ + imx6q-apalis-v1.2-ixora.dtb \ + imx6q-apalis-v1.2-ixora-v1.1.dtb \ + imx6q-apalis-v1.2-ixora-v1.2.dtb \ imx6q-apf6dev.dtb \ imx6q-arm2.dtb \ imx6q-b450v3.dtb \ @@ -329,6 +338,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ + imx6ul-var-som-concerto.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi index 9cfff2151b7e..82601a4b7b4b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi @@ -611,7 +611,7 @@ reg = <0x80000000 0x3b002000>; ranges; - nfc: nand@bb000000 { + nfc: nand-controller@bb000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts index d17abdfb6330..630f8fa69ba8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx31-lite.dts +++ b/arch/arm/boot/dts/nxp/imx/imx31-lite.dts @@ -157,7 +157,7 @@ &weim { status = "okay"; - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; reg = <0 0x0 0x200000>; bank-width = <2>; diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi index 00006c90d9a7..8541a666747a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi @@ -218,7 +218,7 @@ }; iim: efuse@5001c000 { - compatible = "fsl,imx31-iim", "fsl,imx27-iim"; + compatible = "fsl,imx31-iim"; reg = <0x5001c000 0x1000>; interrupts = <19>; clocks = <&clks 25>; @@ -340,7 +340,7 @@ #address-cells = <1>; #size-cells = <1>; - nfc: nand@b8000000 { + nfc: nand-controller@b8000000 { compatible = "fsl,imx31-nand", "fsl,imx27-nand"; reg = <0xb8000000 0x1000>; interrupts = <33>; diff --git a/arch/arm/boot/dts/nxp/imx/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi index 30beb39e0162..111d7c0331f5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -363,7 +363,7 @@ reg = <0x80000000 0x40000000>; ranges; - nfc: nand@bb000000 { + nfc: nand-controller@bb000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx35-nand", "fsl,imx25-nand"; diff --git a/arch/arm/boot/dts/nxp/imx/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi index 1b6f444443dd..d76c496b3f71 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx50.dtsi @@ -338,7 +338,7 @@ clks: ccm@53fd4000 { compatible = "fsl,imx50-ccm"; reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi index dc72a2d14960..1980f751f161 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51-digi-connectcore-som.dtsi @@ -165,7 +165,7 @@ mma7455l@1d { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mma7455l>; - compatible = "fsl,mma7455l"; + compatible = "fsl,mma7455"; reg = <0x1d>; interrupt-parent = <&gpio1>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi index cc88da4d7785..c8698a9af1a7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51.dtsi @@ -458,7 +458,7 @@ clks: ccm@73fd4000 { compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; }; @@ -476,7 +476,7 @@ }; iim: efuse@83f98000 { - compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon"; + compatible = "fsl,imx51-iim"; reg = <0x83f98000 0x4000>; interrupts = <69>; clocks = <&clks IMX5_CLK_IIM_GATE>; @@ -595,7 +595,7 @@ status = "disabled"; }; - nfc: nand@83fdb000 { + nfc: nand-controller@83fdb000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx51-nand"; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts index c14eb7280f09..3cdb87ac1d7c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts @@ -162,7 +162,7 @@ }; expander: pca9554@20 { - compatible = "pca9554"; + compatible = "nxp,pca9554"; reg = <0x20>; interrupts = <109>; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts index e939acc1c88b..2892e457fea7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -593,7 +593,7 @@ touchscreen@4b { compatible = "atmel,maxtouch"; - reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; reg = <0x4b>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi index 845e2bf8460a..93225a56896f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53.dtsi @@ -598,7 +598,7 @@ clks: ccm@53fd4000 { compatible = "fsl,imx53-ccm"; reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; @@ -668,7 +668,7 @@ }; iim: efuse@63f98000 { - compatible = "fsl,imx53-iim", "fsl,imx27-iim", "syscon"; + compatible = "fsl,imx53-iim"; reg = <0x63f98000 0x4000>; interrupts = <69>; clocks = <&clks IMX5_CLK_IIM_GATE>; @@ -775,7 +775,7 @@ status = "disabled"; }; - nfc: nand@63fdb000 { + nfc: nand-controller@63fdb000 { compatible = "fsl,imx53-nand"; reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; interrupts = <8>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts new file mode 100644 index 000000000000..44c78c07f431 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-aster.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Aster Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts new file mode 100644 index 000000000000..93fd0af53a3c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-eval-v3.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Evaluation Board V3"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts new file mode 100644 index 000000000000..92d41fc9a13f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-iris-v2.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris V2 Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts new file mode 100644 index 000000000000..c8957948c887 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts index e1077e2da5f4..1f2200f50059 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-eval.dts @@ -36,15 +36,6 @@ status = "okay"; }; -/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ -&i2c1 { - /* PCIe Switch */ - pcie-switch@58 { - compatible = "plx,pex8605"; - reg = <0x58>; - }; -}; - &pcie { vpcie-supply = <®_pcie_switch>; status = "okay"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts new file mode 100644 index 000000000000..908dab57fd87 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-eval-v1.2.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board v1.2"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts new file mode 100644 index 000000000000..5463d4127382 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-eval.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts new file mode 100644 index 000000000000..84eabf81ba84 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora-v1.1.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.1"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts new file mode 100644 index 000000000000..d7cfab4de457 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora-v1.2.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.2"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts new file mode 100644 index 000000000000..189b074e31ce --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts index f08b37010291..bba82126aaaa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts @@ -279,7 +279,7 @@ ranges = <0 0 0x08000000 0x08000000>; status = "okay"; - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x02000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi new file mode 100644 index 000000000000..83fa04fc9f18 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +&i2c2 { + /delete-node/ stmpe811@41; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + tla2024_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Apalis AN1_ADC0 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_ADC1 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_ADC2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_TSWIP_ADC3 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi index dffab5aa8b9c..b13000a62a7b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi @@ -10,7 +10,6 @@ / { model = "Toradex Apalis iMX6Q/D Module"; - compatible = "toradex,apalis_imx6q", "fsl,imx6q"; aliases { mmc0 = &usdhc3; /* eMMC */ @@ -108,6 +107,11 @@ }; }; + poweroff { + compatible = "regulator-poweroff"; + cpu-supply = <&vgen2_reg>; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-always-on; @@ -236,10 +240,6 @@ status = "disabled"; }; -&clks { - fsl,pmic-stby-poweroff; -}; - /* Apalis SPI1 */ &ecspi1 { cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; @@ -527,7 +527,6 @@ pmic: pmic@8 { compatible = "fsl,pfuze100"; - fsl,pmic-stby-poweroff; reg = <0x08>; regulators { @@ -664,7 +663,6 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; - status = "disabled"; }; stmpe_adc: stmpe_adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi new file mode 100644 index 000000000000..d11bf911b728 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +&i2c2 { + /delete-node/ stmpe811@41; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + tla2024_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Colibri AIN0 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN1 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN3 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi index 9f33419c260b..3525cbcda57f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -10,7 +10,6 @@ / { model = "Toradex Colibri iMX6DL/S Module"; - compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; aliases { mmc0 = &usdhc3; /* eMMC */ @@ -588,7 +587,6 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; - status = "disabled"; }; stmpe_adc: stmpe_adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index 8cefda70db63..ee2c6bec92e8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -124,7 +124,7 @@ compatible = "fsl,imx-audio-tlv320aic32x4"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&ssi1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index a381cb224c1e..2587d17c5918 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -854,7 +854,7 @@ ranges = <0 0 0x08000000 0x08000000>; status = "disabled"; /* pin conflict with SPI NOR */ - nor@0,0 { + flash@0,0 { compatible = "cfi-flash"; reg = <0 0 0x02000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi index 6152a9ed4768..07492f63a1f8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi @@ -7,16 +7,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> -/ { - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -25,11 +15,16 @@ m25p80: flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; + spi-max-frequency = <50000000>; + vcc-supply = <&sw4_reg>; m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; @@ -119,7 +114,7 @@ }; sw4_reg: sw4 { - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -183,7 +178,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&sw4_reg>; non-removable; disable-wp; no-sd; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi index 828996382f24..e8fd37dd8835 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -30,14 +30,14 @@ temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; - vs-supply = <®_3p3v>; + vs-supply = <&sw4_reg>; }; eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; - vcc-supply = <®_3p3v>; + vcc-supply = <&sw4_reg>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi index 1d0966b8d99e..0e404c1f62f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -23,14 +23,14 @@ temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; - vs-supply = <®_3p3v>; + vs-supply = <&sw4_reg>; }; eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; - vcc-supply = <®_3p3v>; + vcc-supply = <&sw4_reg>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts index fbe260c9872e..cad985e341a1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-prtwd3.dts @@ -384,7 +384,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 0e839bbfea08..911ccbd132cf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -62,6 +62,33 @@ gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -139,6 +166,11 @@ wlf,gpio-cfg = <1 3>; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; camera@3c { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi index f2386dcb9ff2..dda4fa91b2f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi @@ -40,6 +40,9 @@ reg = <1>; interrupt-parent = <&gpio4>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi index c9c0794f01a2..2dd635a615cb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -162,13 +162,18 @@ status = "okay"; flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; + reg = <0>; spi-max-frequency = <33000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; - reg = <0>; + vcc-supply = <®_vldo4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts index f2a5f17f312e..2e7b96e7b791 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts @@ -6,8 +6,9 @@ /dts-v1/; -#include "imx6ul-tqma6ul1.dtsi" +#include "imx6ul-tqma6ul2.dtsi" #include "mba6ulx.dtsi" +#include "imx6ul-tqma6ul1.dtsi" / { model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi index 24192d012ef7..79c8c5529135 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi @@ -4,8 +4,6 @@ * Author: Markus Niebel <Markus.Niebel@tq-group.com> */ -#include "imx6ul-tqma6ul2.dtsi" - / { model = "TQ-Systems TQMa6UL1 SoM"; compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts new file mode 100644 index 000000000000..9ff3b374a2b3 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL + * Variscite SoM mounted on it + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include "imx6ul-var-som.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Variscite VAR-SOM-MX6UL Concerto Board"; + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; + + key-back { + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + }; + + key-wakeup { + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + label = "gpled2"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@68 { + /* + * To actually use this interrupt + * connect pins J14.8 & J14.10 on the Concerto-Board. + */ + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_gpio_key_back: gpio-key-backgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + + pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 + >; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&tsc { + /* + * Conflics with wdog1 ext-reset-output & SD CD pins, + * so we keep it disabled by default. + */ + status = "disabled"; +}; + +/* Console UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* ttymxc4 UART */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + /* + * To actually use ext-reset-output + * connect pins J17.3 & J17.8 on the Concerto-Board + */ + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi new file mode 100644 index 000000000000..4e536e0252de --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-MX6UL Module + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +/dts-v1/; + +#include "imx6ul.dtsi" +#include <dt-bindings/clock/imx6ul-clock.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Variscite VAR-SOM-MX6UL module"; + compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_gpio_dvfs: reg-gpio-dvfs { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 + 1400000 0x0>; + }; + + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + dc-supply = <®_gpio_dvfs>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; + +&pxp { + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi index 576a7df505d3..4d948a9757f9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi @@ -170,7 +170,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-routing = diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index aa8f65cd4adf..2966a33bc528 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -265,6 +265,13 @@ spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; + vcc-supply = <&vgen4_reg>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts index eec526a96311..ff9d50942884 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-remarkable2.dts @@ -374,7 +374,7 @@ cap-power-off-card; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index 6cde84636900..17236f90ab33 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -143,6 +143,33 @@ gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; @@ -406,6 +433,11 @@ <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <884736000>, <12288000>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi index 0484e349e064..d961c61a93af 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi @@ -48,7 +48,7 @@ opp-792000000 { opp-hz = /bits/ 64 <792000000>; - opp-microvolt = <1000000>; + opp-microvolt = <1000000 950000 1250000>; clock-latency-ns = <150000>; opp-supported-hw = <0xd>, <0x7>; opp-suspend; @@ -56,7 +56,7 @@ opp-996000000 { opp-hz = /bits/ 64 <996000000>; - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1045000 1250000>; clock-latency-ns = <150000>; opp-supported-hw = <0xc>, <0x7>; opp-suspend; @@ -64,7 +64,7 @@ opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; + opp-microvolt = <1225000 1200000 1250000>; clock-latency-ns = <150000>; opp-supported-hw = <0x8>, <0x3>; opp-suspend; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 22dd72499ef2..9235dd7e93bb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -73,7 +73,6 @@ device_type = "cpu"; reg = <0>; clock-frequency = <792000000>; - clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; cpu-idle-states = <&cpu_sleep_wait>; operating-points-v2 = <&cpu0_opp_table>; @@ -176,6 +175,34 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -529,34 +556,6 @@ #mux-control-cells = <1>; mux-reg-masks = <0x14 0x00000010>; }; - - video_mux: csi-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - csi_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_csi_mux>; - }; - }; - - port@2 { - reg = <2>; - - csi_mux_to_csi: endpoint { - remote-endpoint = <&csi_from_csi_mux>; - }; - }; - }; }; ocotp: efuse@30350000 { diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index 941d9860218e..67a3d484bc9f 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -142,7 +142,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 974410918f35..41f41a786f9d 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -94,7 +94,7 @@ /* * Enable either ohci or usbd (gadget)! */ - ohci: ohci@0 { + ohci: usb@0 { compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x0 0x300>; interrupt-parent = <&sic1>; diff --git a/arch/arm/boot/dts/nxp/ls/Makefile b/arch/arm/boot/dts/nxp/ls/Makefile index 14759331dba2..53240b04c968 100644 --- a/arch/arm/boot/dts/nxp/ls/Makefile +++ b/arch/arm/boot/dts/nxp/ls/Makefile @@ -6,3 +6,12 @@ dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-tqmls1021a-mbls1021a.dtb \ ls1021a-tsn.dtb \ ls1021a-twr.dtb + +ls1021a-tqmls1021a-mbls1021a-hdmi-dtbs += ls1021a-tqmls1021a-mbls1021a.dtb ls1021a-tqmls1021a-mbls1021a-hdmi.dtbo +ls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33-dtbs += ls1021a-tqmls1021a-mbls1021a.dtb ls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33.dtbo +ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44-dtbs += ls1021a-tqmls1021a-mbls1021a.dtb ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtbo +ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21-dtbs += ls1021a-tqmls1021a-mbls1021a.dtb ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtbo +dtb-$(CONFIG_SOC_LS1021A) += ls1021a-tqmls1021a-mbls1021a-hdmi.dtb +dtb-$(CONFIG_SOC_LS1021A) += ls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33.dtb +dtb-$(CONFIG_SOC_LS1021A) += ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtb +dtb-$(CONFIG_SOC_LS1021A) += ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtb diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-hdmi.dtso b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-hdmi.dtso new file mode 100644 index 000000000000..e713a2ecbfc2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-hdmi.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +&dcu { + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&sii9022a_in>; + }; + }; +}; + +&hdmi_out { + status = "okay"; +}; + +&sii9022a { + status = "okay"; +}; + +&sii9022a_in { + remote-endpoint = <&dcu_out>; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33.dtso b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..e9708f3c6740 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include <dt-bindings/gpio/gpio.h> + +/dts-v1/; +/plugin/; + +&backlight_dcu { + status = "okay"; +}; + +&dcu { + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&lvds_encoder_in>; + }; + }; +}; + +&display { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; + +&lvds_encoder { + status = "okay"; +}; + +&lvds_encoder_in { + remote-endpoint = <&dcu_out>; +}; + +&lvds_encoder_out { + remote-endpoint = <&panel_in>; +}; + +&panel_in { + remote-endpoint = <&lvds_encoder_out>; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso new file mode 100644 index 000000000000..146d45601f69 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/dts-v1/; +/plugin/; + +&backlight_dcu { + status = "okay"; +}; + +&dcu { + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&display { + compatible = "cdtech,s070swv29hg-dc44"; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&pca9554_0>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + /* LCD_PWR_EN -> TSC_WAKE */ + wake-gpios = <&pca9554_1 4 GPIO_ACTIVE_HIGH>; + iovcc-supply = <®_3p3v>; + vcc-supply = <®_3p3v>; + gain = <20>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&panel_in { + remote-endpoint = <&dcu_out>; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso new file mode 100644 index 000000000000..db66831f31af --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/dts-v1/; +/plugin/; + +&backlight_dcu { + status = "okay"; +}; + +&dcu { + status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&display { + compatible = "cdtech,s070pws19hp-fc21"; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&pca9554_0>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + /* LCD_PWR_EN -> TSC_WAKE */ + wake-gpios = <&pca9554_1 4 GPIO_ACTIVE_HIGH>; + iovcc-supply = <®_3p3v>; + vcc-supply = <®_3p3v>; + gain = <20>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&panel_in { + remote-endpoint = <&dcu_out>; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts index 34636fcdfd6a..5606585dd560 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright 2013-2014 Freescale Semiconductor, Inc. * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, @@ -147,6 +147,7 @@ display: panel { backlight = <&backlight_dcu>; enable-gpios = <&pca9554_1 3 GPIO_ACTIVE_HIGH>; + power-supply = <®_3p3v>; status = "disabled"; port { @@ -156,7 +157,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "ls1021a-mbls1021a-tlv320aic32"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; }; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi index 1b13851ad997..271001eb5ad7 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* * Copyright 2013-2014 Freescale Semiconductor, Inc. * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, @@ -72,6 +72,7 @@ spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; reg = <0>; + vcc-supply = <®_3p3v_som>; partitions { compatible = "fixed-partitions"; diff --git a/arch/arm/boot/dts/nxp/mxs/Makefile b/arch/arm/boot/dts/nxp/mxs/Makefile index a430d04f9c69..96dd31ea19ba 100644 --- a/arch/arm/boot/dts/nxp/mxs/Makefile +++ b/arch/arm/boot/dts/nxp/mxs/Makefile @@ -8,6 +8,9 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-apf28.dtb \ imx28-apf28dev.dtb \ imx28-apx4devkit.dtb \ + imx28-btt3-0.dtb \ + imx28-btt3-1.dtb \ + imx28-btt3-2.dtb \ imx28-cfa10036.dtb \ imx28-cfa10037.dtb \ imx28-cfa10049.dtb \ diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts index cb661bf2d157..613f13b6c8a8 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-sansa.dts @@ -93,9 +93,9 @@ MX23_PAD_LCD_HSYNC__GPIO_1_24 MX23_PAD_PWM3__GPIO_1_29 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts index 0b088c8ab6b6..fad08f6c008f 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-xfi3.dts @@ -83,9 +83,9 @@ fsl,pinmux-ids = < MX23_PAD_GPMI_D07__GPIO_0_7 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; }; key_pins_a: keys@0 { @@ -94,9 +94,9 @@ MX23_PAD_ROTARYA__GPIO_2_7 MX23_PAD_ROTARYB__GPIO_2_8 >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <1>; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts new file mode 100644 index 000000000000..6ac46e4b21bb --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" + +&hog_pins_rev { + fsl,pull-up = <MXS_PULL_ENABLE>; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts new file mode 100644 index 000000000000..213fe931c58b --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts new file mode 100644 index 000000000000..4bccd784d065 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" + +/ { + panel { + compatible = "powertip,st7272", "panel-dpi"; + power-supply = <®_3v3>; + width-mm = <70>; + height-mm = <52>; + + panel-timing { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hfront-porch = <20>; + hback-porch = <68>; + hsync-len = <30>; + vfront-porch = <4>; + vback-porch = <14>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi new file mode 100644 index 000000000000..a6903ef2b093 --- /dev/null +++ b/arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + model = "BTT3"; + + compatible = "lwn,imx28-btt3", "fsl,imx28"; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1 quiet"; + }; + + memory@40000000 { + reg = <0x40000000 0x10000000>; + device_type = "memory"; + }; + + panel { + compatible = "powertip,hx8238a", "panel-dpi"; + power-supply = <®_3v3>; + width-mm = <70>; + height-mm = <52>; + + panel-timing { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hfront-porch = <20>; + hback-porch = <38>; + hsync-len = <30>; + vfront-porch = <4>; + vback-porch = <14>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "BTTC Audio"; + simple-audio-card,widgets = "Speaker", "BTTC Speaker"; + simple-audio-card,routing = "BTTC Speaker", "SPKOUTN", "BTTC Speaker", "SPKOUTP"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + bitclock-master = <&dai0_master>; + frame-master = <&dai0_master>; + mclk-fs = <256>; + + dai0_master: cpu { + sound-dai = <&saif0>; + }; + + codec { + sound-dai = <&wm89xx>; + clocks = <&saif0>; + }; + }; + }; + + wifi_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pin_bttc>; + reset-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + /* W1-163 needs 60us for WL_EN to be low and */ + /* 150ms after high before downloading FW is possible */ + post-power-on-delay-ms = <200>; + power-off-delay-us = <100>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + wm89xx: audio-codec@1a { + compatible = "wlf,wm8940"; + reg = <0x1a>; + #sound-dai-cells = <0>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>, <&lcdif_sync_pins_bttc>, + <&lcdif_reset_pins_bttc>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&mac0 { + clocks = <&clks 57>, <&clks 57>, <&clks 64>; + clock-names = "ipg", "ahb", "enet_out"; + phy-handle = <&mac0_phy>; + phy-mode = "rmii"; + phy-supply = <®_3v3>; + /* + * This MAC address is adjusted during production. + * Value specified below is used as a fallback during recovery. + */ + local-mac-address = [ 00 11 B8 00 BF 8A ]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mac0_phy: ethernet-phy@0 { + /* LAN8720Ai - PHY ID */ + compatible = "ethernet-phy-id0007.c0f0","ethernet-phy-ieee802.3-c22"; + reg = <0>; + smsc,disable-energy-detect; + max-speed = <100>; + reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>, <&hog_pins_rev>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_AUART2_CTS__GPIO_3_10 + MX28_PAD_AUART2_RTS__GPIO_3_11 + MX28_PAD_GPMI_WRN__GPIO_0_25 + MX28_PAD_ENET0_RXD2__GPIO_4_9 + MX28_PAD_ENET0_TXD2__GPIO_4_11 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + hog_pins_rev: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RXD3__GPIO_4_10 + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 + MX28_PAD_ENET0_COL__GPIO_4_14 + MX28_PAD_ENET0_CRS__GPIO_4_15 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + keypad_pins_bttc: keypad-bttc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_AUART0_CTS__GPIO_3_2 + MX28_PAD_AUART0_RTS__GPIO_3_3 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_CE2N__GPIO_0_18 + MX28_PAD_GPMI_CE3N__GPIO_0_19 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_sync_pins_bttc: lcdif-bttc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_RD_E__LCD_VSYNC + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + lcdif_reset_pins_bttc: lcdif-bttc@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + ssp1_sdio_pins_a: ssp1-sdio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP1_DATA0__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_SSP1_DATA3__SSP1_D3 + MX28_PAD_SSP1_CMD__SSP1_CMD + MX28_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + wifi_en_pin_bttc: wifi-en-pin@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CLE__GPIO_0_27 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a>; + status = "okay"; +}; + +®_usb_5v { + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + #sound-dai-cells = <0>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_sdio_pins_a>; + bus-width = <4>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + vmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts index d004b1cbb4ae..f170df37b3f8 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts @@ -102,9 +102,9 @@ 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts index 0f01dded4e3d..ca62e7933116 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts @@ -24,30 +24,25 @@ }; leds { - #address-cells = <1>; - #size-cells = <0>; compatible = "gpio-leds"; status = "okay"; - led@1 { + led-1 { label = "sps1-1:yellow:user"; gpios = <&gpio0 6 0>; linux,default-trigger = "heartbeat"; - reg = <0>; }; - led@2 { + led-2 { label = "sps1-2:red:user"; gpios = <&gpio0 3 0>; linux,default-trigger = "heartbeat"; - reg = <1>; }; - led@3 { + led-3 { label = "sps1-3:red:user"; gpios = <&gpio0 0 0>; - default-trigger = "heartbeat"; - reg = <2>; + linux,default-trigger = "heartbeat"; }; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts index 722182f5fd17..2492fb99956c 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-bk4.dts @@ -119,7 +119,7 @@ status = "okay"; spidev0@0 { - compatible = "lwn,bk4"; + compatible = "lwn,bk4-spi"; spi-max-frequency = <30000000>; reg = <0>; fsl,spi-cs-sck-delay = <200>; @@ -136,7 +136,7 @@ #address-cells = <0>; slave { - compatible = "lwn,bk4"; + compatible = "lwn,bk4-spi"; spi-max-frequency = <30000000>; }; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi index 607cec2df861..20aed3946214 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi @@ -8,7 +8,6 @@ / { model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; memory@80000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts index 6f9878f124c4..4f99044837f8 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts @@ -392,7 +392,7 @@ }; &gpio0 { - eth0_intrp { + eth0-intrp-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; input; @@ -401,7 +401,7 @@ }; &gpio3 { - eth0_intrp { + eth0-intrp-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; input; diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index acccf9a3c898..597f20be82f1 100644 --- a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -158,8 +158,8 @@ clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <6>; - dmas = <&edma1 1 12>, <&edma1 1 13>; - dma-names = "rx", "tx"; + dmas = <&edma1 1 13>, <&edma1 1 12>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -172,8 +172,8 @@ clocks = <&clks VF610_CLK_DSPI1>; clock-names = "dspi"; spi-num-chipselects = <4>; - dmas = <&edma1 1 14>, <&edma1 1 15>; - dma-names = "rx", "tx"; + dmas = <&edma1 1 15>, <&edma1 1 14>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -529,9 +529,8 @@ clocks = <&clks VF610_CLK_DSPI2>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 10>, - <&edma1 0 11>; - dma-names = "rx", "tx"; + dmas = <&edma1 0 11>, <&edma1 0 10>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -544,8 +543,8 @@ clocks = <&clks VF610_CLK_DSPI3>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 12>, <&edma1 0 13>; - dma-names = "rx", "tx"; + dmas = <&edma1 0 13>, <&edma1 0 12>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -725,13 +724,13 @@ clocks = <&clks VF610_CLK_CAAM>; clock-names = "ipg"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index f06c6d425e91..0c1d116f6e84 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-lagan-yuga.dtb \ qcom-apq8064-asus-nexus7-flo.dtb \ + qcom-apq8064-lg-nexus4-mako.dtb \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index 5dbca83f2230..e6392f7d14c7 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -31,6 +31,15 @@ vsp-supply = <®_lcd_pos>; vsn-supply = <®_lcd_neg>; vddio-supply = <&vddio_disp_vreg>; + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; @@ -53,9 +62,12 @@ }; }; + /* TI TPS22902 */ vddio_disp_vreg: regulator-vddio-disp { compatible = "regulator-fixed"; regulator-name = "vddio_disp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; vin-supply = <&pm8226_l8>; startup-delay-us = <300>; @@ -97,6 +109,7 @@ }; &blsp1_i2c2 { + clock-frequency = <100000>; status = "okay"; magnetometer@c { @@ -126,6 +139,7 @@ }; &blsp1_i2c3 { + clock-frequency = <400000>; status = "okay"; regulator@3e { @@ -136,8 +150,8 @@ reg_lcd_pos: outp { regulator-name = "outp"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; regulator-active-discharge = <1>; regulator-boot-on; enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; @@ -145,8 +159,8 @@ reg_lcd_neg: outn { regulator-name = "outn"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5400000>; regulator-active-discharge = <1>; regulator-boot-on; enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/qcom/msm8926.dtsi b/arch/arm/boot/dts/qcom/msm8926.dtsi new file mode 100644 index 000000000000..629654c525b4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8926.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss <luca@lucaweiss.eu> + */ + +#include "qcom-msm8226.dtsi" + +&modem { + compatible = "qcom,msm8926-mss-pil"; + /delete-property/ qcom,ext-bhs-reg; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts index da3be658e822..4546fa8beba4 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-matisse-wifi.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-samsung-matisse-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts index 7d519156d91d..a8543ca7b556 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts @@ -12,6 +12,8 @@ #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index b3ff8010b149..717bfd74edb7 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -138,7 +138,6 @@ &hdmi { core-vdda-supply = <&pm8921_hdmi_switch>; - hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts new file mode 100644 index 000000000000..c187c6875bc6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/mfd/qcom-rpm.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +#include "qcom-apq8064-v2.0.dtsi" +#include "pm8821.dtsi" +#include "pm8921.dtsi" + +/ { + model = "LG Nexus 4 (mako)"; + compatible = "lg,nexus4-mako", "qcom,apq8064"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi6_serial; + serial2 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + battery_cell: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <900000>; + operating-range-celsius = <0 45>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@88d00000{ + compatible = "ramoops"; + reg = <0x88d00000 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + }; + }; +}; + +&gsbi1 { + qcom,mode = <GSBI_PROT_I2C>; + + status = "okay"; +}; + +&gsbi1_i2c { + clock-frequency = <200000>; + + status = "okay"; +}; + +&gsbi4 { + qcom,mode = <GSBI_PROT_I2C_UART>; + + status = "okay"; +}; + +&gsbi4_serial { + status = "okay"; +}; + +&pm8821 { + interrupts-extended = <&tlmm_pinmux 76 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921 { + interrupts-extended = <&tlmm_pinmux 74 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921_keypad { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 1, KEY_VOLUMEUP) + >; + + keypad,num-rows = <1>; + keypad,num-columns = <5>; + + status = "okay"; +}; + +&riva { + pinctrl-names = "default"; + pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>; + + vddcx-supply = <&pm8921_s3>; + vddmx-supply = <&pm8921_l24>; + vddpx-supply = <&pm8921_s4>; + + status = "okay"; + + iris { + vddxo-supply = <&pm8921_l4>; + vddrfa-supply = <&pm8921_s2>; + vddpa-supply = <&pm8921_l10>; + vdddig-supply = <&pm8921_lvs2>; + }; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + pm8921_l1: l1 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi1_pll_vdda */ + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_3p3 */ + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3500000>; + bias-pull-down; + }; + + /* msm_otg-HSUSB_1p8 */ + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* msm_sdcc.1-sdc_vdd */ + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + /* earjack_debug */ + pm8921_l6: l6 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi_vci */ + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vddpa */ + pm8921_l10: l10 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + bias-pull-down; + }; + + /* mipi_dsi.1-dsi1_avdd */ + pm8921_l11: l11 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + /* touch_vdd */ + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + /* slimport_dvdd */ + pm8921_l18: l18 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + bias-pull-down; + }; + + /* touch_io */ + pm8921_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * mipi_dsi.1-dsi_vddio + * pil_qdsp6v4.1-pll_vdd + * pil_qdsp6v4.2-pll_vdd + * msm_ehci_host.0-HSUSB_1p8 + * msm_ehci_host.1-HSUSB_1p8 + */ + pm8921_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + /* + * tabla2x-slim-CDC_VDDA_A_1P2V + * tabla2x-slim-VDDD_CDC_D + */ + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + bias-pull-down; + }; + + pm8921_l26: l26 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + bias-pull-down; + }; + + pm8921_l27: l27 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + pm8921_l28: l28 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vddio */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + /* wcnss_wlan.0-iris_vdddig */ + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + /* mipi_dsi.1-dsi_iovcc */ + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + /* + * pil_riva-pll_vdd + * lvds.0-lvds_vdda + * mipi_dsi.1-dsi1_vddio + * hdmi_msm.0-hdmi_vdda + */ + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* msm otg HSUSB_VDDCX */ + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + /* + * msm_sdcc.1-sdc-vdd_io + * tabla2x-slim-CDC_VDDA_RX + * tabla2x-slim-CDC_VDDA_TX + * tabla2x-slim-CDC_VDD_CP + * tabla2x-slim-VDDIO_CDC + */ + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>; + }; + + /* + * supply vdd_l26, vdd_l27, vdd_l28 + */ + pm8921_s7: s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s8: s8 { + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +/* eMMC */ +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 5f1a6b4b7644..17e506ca2438 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -213,12 +213,6 @@ }; }; - sfpb_mutex: hwmutex { - compatible = "qcom,sfpb-mutex"; - syscon = <&sfpb_wrapper_mutex 0x604 0x4>; - #hwlock-cells = <1>; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_region>; @@ -284,6 +278,40 @@ }; }; + replicator { + compatible = "arm,coresight-static-replicator"; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&funnel_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -305,9 +333,10 @@ pinctrl-0 = <&ps_hold_default_state>; }; - sfpb_wrapper_mutex: syscon@1200000 { - compatible = "syscon"; - reg = <0x01200000 0x8000>; + sfpb_mutex: hwmutex@1200600 { + compatible = "qcom,sfpb-mutex"; + reg = <0x01200600 0x100>; + #hwlock-cells = <1>; }; intc: interrupt-controller@2000000 { @@ -326,6 +355,8 @@ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; @@ -405,8 +436,8 @@ }; }; - sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; + sps_sic_non_secure: interrupt-controller@12100000 { + compatible = "qcom,apq8064-sps-sic", "syscon"; reg = <0x12100000 0x10000>; }; @@ -737,7 +768,8 @@ <&dsi0_phy 0>, <&dsi1_phy 1>, <&dsi1_phy 0>, - <&hdmi_phy>; + <&hdmi_phy>, + <&mdp>; clock-names = "pxo", "pll3", "pll8_vote", @@ -745,7 +777,8 @@ "dsi1pllbyte", "dsi2pll", "dsi2pllbyte", - "hdmipll"; + "hdmipll", + "lvdspll"; }; l2cc: clock-controller@2011000 { @@ -1089,7 +1122,7 @@ }; mmss_sfpb: syscon@5700000 { - compatible = "syscon"; + compatible = "qcom,apq8064-mmss-sfpb", "syscon"; reg = <0x5700000 0x70>; }; @@ -1404,13 +1437,19 @@ <&mmcc MDP_AXI_CLK>, <&mmcc MDP_LUT_CLK>, <&mmcc HDMI_TV_CLK>, - <&mmcc MDP_TV_CLK>; + <&mmcc MDP_TV_CLK>, + <&mmcc LVDS_CLK>, + <&rpmcc RPM_PXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_clk", "lut_clk", "hdmi_clk", - "tv_clk"; + "tv_clk", + "lcdc_clk", + "pxo"; + + #clock-cells = <0>; iommus = <&mdp_port0 0 &mdp_port0 2 @@ -1532,39 +1571,6 @@ }; }; - replicator { - compatible = "arm,coresight-static-replicator"; - - clocks = <&rpmcc RPM_QDSS_CLK>; - clock-names = "apb_pclk"; - - out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out0: endpoint { - remote-endpoint = <&etb_in>; - }; - }; - port@1 { - reg = <1>; - replicator_out1: endpoint { - remote-endpoint = <&tpiu_in>; - }; - }; - }; - - in-ports { - port { - replicator_in: endpoint { - remote-endpoint = <&funnel_out>; - }; - }; - }; - }; - funnel@1a04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x1a04000 0x1000>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 6fce0112361f..34b0cf35fdac 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -149,7 +149,7 @@ }; &pm8941_gpios { - msm_keys_default: pm8941-gpio-keys-state { + msm_keys_default: pm8941-gpio-keys-state { pins = "gpio5", "gpio23"; function = "normal"; input-enable; @@ -157,7 +157,7 @@ bias-pull-up; qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; power-source = <PM8941_GPIO_S3>; /* 1.8V */ - }; + }; }; &pm8941_lpg { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index a6d4390efa7c..be76bc39ac27 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -251,7 +251,7 @@ status = "okay"; nvmem-cell-names = "pre-calibration"; nvmem-cells = <&precal_art_5000>; - qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; + qcom,calibration-variant = "ALFA-Network-AP120C-AC"; }; &usb3_hs_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts index 6640ea7b6acb..15baaf0d1529 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -179,13 +179,13 @@ &wifi0 { status = "okay"; - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; + qcom,calibration-variant = "8devices-Jalapeno"; }; &wifi1 { status = "okay"; - qcom,ath10k-calibration-variant = "8devices-Jalapeno"; + qcom,calibration-variant = "8devices-Jalapeno"; }; &usb3_ss_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi index cc88cf5f0d9b..5a95a2d03c42 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -43,7 +43,7 @@ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69"; function = "qpic"; - }; + }; }; serial@78af000 { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 06b20c196faf..f77542fb3d4f 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -53,7 +53,6 @@ reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -67,7 +66,6 @@ reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -81,7 +79,6 @@ reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -95,7 +92,6 @@ reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; clock-frequency = <0>; - clock-latency = <256000>; operating-points-v2 = <&cpu0_opp_table>; }; @@ -126,7 +122,7 @@ opp-716000000 { opp-hz = /bits/ 64 <716000000>; clock-latency-ns = <256000>; - }; + }; }; memory { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi index ca76bf8af75e..d4a32af0ef8f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi @@ -8,7 +8,11 @@ * Copyright (c) 2023, Rayyan Ansari <rayyan@ansari.sh> */ -#include "qcom-msm8226.dtsi" +/* + * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on + * the SoC on the given device. + */ + #include "pm8226.dtsi" #include <dt-bindings/input/input.h> diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts index 2c664b5934ec..f448c9088416 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-dempsey.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts index 731c5c375678..94bf3b1ad1bd 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-makepeace.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts index a28a83cb5340..d8cdb75dfbb8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "qcom-msm8226.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has no magnetometer */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi index a15a44fc0181..f1544a7e8369 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-matisse-common.dtsi @@ -3,11 +3,17 @@ * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com> */ +/* + * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on + * the SoC on the given device. + */ + #include <dt-bindings/input/input.h> -#include "qcom-msm8226.dtsi" #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { @@ -145,12 +151,12 @@ no-map; }; - mpss@8400000 { + mpss_region: mpss@8400000 { reg = <0x08400000 0x1f00000>; no-map; }; - mba@a300000 { + mba_region: mba@a300000 { reg = <0x0a300000 0x100000>; no-map; }; @@ -223,6 +229,13 @@ status = "okay"; }; +&modem { + mx-supply = <&pm8226_l3>; + pll-supply = <&pm8226_l8>; + + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm8226-regulators"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 64c8ac94f352..51a7a3fb36d8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -213,6 +214,18 @@ no-map; }; + mpss_region: mpss@8000000 { + reg = <0x08000000 0x5100000>; + no-map; + status = "disabled"; + }; + + mba_region: mba@d100000 { + reg = <0x0d100000 0x100000>; + no-map; + status = "disabled"; + }; + adsp_region: adsp@dc00000 { reg = <0x0dc00000 0x1900000>; no-map; @@ -253,6 +266,65 @@ }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + #address-cells = <1>; + #size-cells = <0>; + + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + adsp_smsm: adsp@2 { + reg = <2>; + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; @@ -845,12 +917,96 @@ #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + + modem: remoteproc@fc880000 { + compatible = "qcom,msm8226-mss-pil"; + reg = <0xfc880000 0x4040>, + <0xfc820000 0x10000>; + reg-names = "qdsp6", + "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "bus", + "mem", + "xo"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + power-domains = <&rpmpd MSM8226_VDDCX>; + power-domain-names = "cx"; + + qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>; + qcom,halt-regs = <&tcsr_regs_1 0x180 0x200 0x280>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + memory-region = <&mba_region>, <&mpss_region>; + + status = "disabled"; + + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs 12>; + qcom,smd-edge = <0>; + + label = "modem"; + }; + }; + tcsr_mutex: hwlock@fd484000 { compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; reg = <0xfd484000 0x1000>; #hwlock-cells = <1>; }; + tcsr_regs_1: syscon@fd485000 { + compatible = "qcom,tcsr-msm8226", "syscon"; + reg = <0xfd485000 0x1000>; + }; + tlmm: pinctrl@fd510000 { compatible = "qcom,msm8226-pinctrl"; reg = <0xfd510000 0x4000>; @@ -983,8 +1139,8 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>; + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; clock-names = "xo", "mmss_gpll0_vote", "gpll0_vote", @@ -1060,8 +1216,8 @@ assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts index 3037344eb240..cb571aa13c11 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-htc-memul.dts @@ -5,10 +5,12 @@ /dts-v1/; -#include "qcom-msm8226.dtsi" +#include "msm8926.dtsi" #include "pm8226.dtsi" /delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; /delete-node/ &smem_region; / { @@ -193,6 +195,16 @@ /* TPS61310 Flash/Torch @ 33 */ }; +&modem { + mx-supply = <&pm8226_l3>; + pll-supply = <&pm8226_l8>; + mss-supply = <&pm8226_s5>; + + firmware-name = "qcom/msm8926/memul/mba.b00", "qcom/msm8926/memul/modem.mdt"; + + status = "okay"; +}; + &pm8226_vib { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts index 9b48661d69c5..eea4fd8cd972 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-superman-lte.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has touchscreen on i2c3 instead */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts index 55077a5f2e34..f23bbb94cc5e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-microsoft-common.dtsi" /* This device has touchscreen on i2c1 instead */ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index 376a33125941..db3273c755c2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "qcom-msm8226.dtsi" +#include "msm8926.dtsi" #include "pm8226.dtsi" /delete-node/ &smem_region; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts index d0e1bc39f8ef..73e19176eb97 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-samsung-matisselte.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "msm8926.dtsi" #include "qcom-msm8226-samsung-matisse-common.dtsi" / { @@ -27,6 +28,10 @@ }; }; +&modem { + mss-supply = <&pm8226_s5>; +}; + &tlmm { tsp_en1_default_state: tsp-en1-default-state { pins = "gpio32"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 865fe7cc3951..4babd0bbe5d6 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -52,6 +52,48 @@ reg = <0x80000000 0>; }; + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 0>; + + trips { + cpu_alert0: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens 1>; + + trips { + cpu_alert1: trip0 { + temperature = <60000>; + hysteresis = <10000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <95000>; + hysteresis = <10000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <GIC_PPI 10 0x304>; @@ -112,9 +154,26 @@ <GIC_PPI 3 0x301>; reg = <0x0200a000 0x100>; clock-frequency = <27000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; cpu-offset = <0x80000>; }; + qfprom: efuse@700000 { + compatible = "qcom,msm8960-qfprom", "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_calib: calib@404 { + reg = <0x404 0x10>; + }; + + tsens_backup: backup-calib@414 { + reg = <0x414 0x10>; + }; + }; + msmgpio: pinctrl@800000 { compatible = "qcom,msm8960-pinctrl"; gpio-controller; @@ -127,7 +186,7 @@ }; gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; + compatible = "qcom,gcc-msm8960", "syscon"; #clock-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; @@ -135,6 +194,18 @@ <&pxo_board>, <&lcc PLL4>; clock-names = "cxo", "pxo", "pll4"; + + tsens: thermal-sensor { + compatible = "qcom,msm8960-tsens"; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; }; lcc: clock-controller@28000000 { @@ -279,7 +350,7 @@ compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; status = "disabled"; - reg = <0x12180000 0x8000>; + reg = <0x12180000 0x2000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -289,13 +360,25 @@ max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc3bam: dma-controller@12182000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x4000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; sdcc1: mmc@12400000 { status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; + reg = <0x12400000 0x2000>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; @@ -305,6 +388,18 @@ cap-sd-highspeed; cap-mmc-highspeed; vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc1bam: dma-controller@12402000 { + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; }; tcsr: syscon@1a400000 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index e3f9c56a778c..7e119370f337 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -3,6 +3,7 @@ #include <dt-bindings/interconnect/qcom,msm8974.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> #include <dt-bindings/clock/qcom,mmcc-msm8974.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -1871,10 +1872,10 @@ <&gcc GPLL0_VOTE>, <&gcc GPLL1_VOTE>, <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi1_phy 1>, - <&mdss_dsi1_phy 0>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, <0>, <0>, <0>; @@ -1961,8 +1962,10 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, @@ -2032,8 +2035,10 @@ interrupt-parent = <&mdss>; interrupts = <4>; - assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 39530eb580ea..20fdae9825e0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -57,7 +57,7 @@ enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX55_CX>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 6b23ee676c9e..c8e312dcd26b 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -58,7 +58,7 @@ enable-method = "psci"; clocks = <&apcs>; power-domains = <&rpmhpd SDX65_CX_AO>; - power-domain-names = "rpmhpd"; + power-domain-names = "perf"; operating-points-v2 = <&cpu_opp_table>; }; }; diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile index 833a02447ecf..947c7fe02803 100644 --- a/arch/arm/boot/dts/renesas/Makefile +++ b/arch/arm/boot/dts/renesas/Makefile @@ -30,4 +30,5 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7794-alt.dtb \ r8a7794-silk.dtb \ r9a06g032-rzn1d400-db.dtb \ + r9a06g032-rzn1d400-eb.dtb \ sh73a0-kzm9g.dtb diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 3bce5876a9d8..4f002aa7fbaf 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -754,6 +754,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts index d7c0a9574ce8..b1e20579e071 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -268,6 +268,7 @@ &scifa0 { pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index f746f0b9e686..4f97c09dbc9f 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -227,6 +227,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -265,6 +266,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -374,6 +376,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -395,6 +398,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -412,6 +416,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7790-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1948,6 +1953,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -2018,5 +2024,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index e4e1d9c98c61..e9f90fa44d55 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -679,6 +679,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index 08381498350a..f518eadd8b9c 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -312,6 +312,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index e57567adff55..5023b41c28b3 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -125,6 +125,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -152,6 +153,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -291,6 +293,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -312,6 +315,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -323,6 +327,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7791-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1875,6 +1880,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1945,5 +1951,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts index a3986076d8e3..23ec0f8a6651 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-blanche.dts @@ -301,6 +301,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts index bfc780f7e396..93bd81723c8f 100644 --- a/arch/arm/boot/dts/renesas/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/renesas/r8a7792-wheat.dts @@ -183,6 +183,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 08cbe6c13cee..7513afc1c958 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -82,6 +82,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; lbsc: bus { @@ -109,6 +110,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -308,6 +310,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -318,6 +321,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -329,6 +333,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7792-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -947,6 +952,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 2c05d7c2b377..45b267ec2679 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -642,6 +642,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index e48e43cc6b03..fc6d3bcca296 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -117,6 +117,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -137,6 +138,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -276,6 +278,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; /* Special CPG clocks */ @@ -287,6 +290,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -298,6 +302,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7793-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1454,6 +1459,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1524,5 +1530,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index f70e26aa83a0..3f06a7f67d62 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -479,6 +479,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts index 2a0819311a3c..342825605768 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -394,6 +394,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index bc16c896c0f9..92010d09f6c4 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -99,6 +99,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -119,6 +120,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -243,6 +245,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -253,6 +256,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -264,6 +268,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7794-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1440,6 +1445,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1491,5 +1497,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index 31cdca3e623c..2de047393652 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -8,8 +8,10 @@ /dts-v1/; -#include <dt-bindings/pinctrl/rzn1-pinctrl.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/net/pcs-rzn1-miic.h> +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> #include "r9a06g032.dtsi" @@ -24,6 +26,68 @@ aliases { serial0 = &uart0; }; + + keyboard { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + switch-1 { + linux,code = <KEY_1>; + label = "SW1-1"; + debounce-interval = <20>; + gpios = <&pca9698 8 GPIO_ACTIVE_LOW>; + }; + + switch-2 { + linux,code = <KEY_2>; + label = "SW1-2"; + debounce-interval = <20>; + gpios = <&pca9698 9 GPIO_ACTIVE_LOW>; + }; + + switch-3 { + linux,code = <KEY_3>; + label = "SW1-3"; + debounce-interval = <20>; + gpios = <&pca9698 10 GPIO_ACTIVE_LOW>; + }; + + switch-4 { + linux,code = <KEY_4>; + label = "SW1-4"; + debounce-interval = <20>; + gpios = <&pca9698 11 GPIO_ACTIVE_LOW>; + }; + + switch-5 { + linux,code = <KEY_5>; + label = "SW1-5"; + debounce-interval = <20>; + gpios = <&pca9698 12 GPIO_ACTIVE_LOW>; + }; + + switch-6 { + linux,code = <KEY_6>; + label = "SW1-6"; + debounce-interval = <20>; + gpios = <&pca9698 13 GPIO_ACTIVE_LOW>; + }; + + switch-7 { + linux,code = <KEY_7>; + label = "SW1-7"; + debounce-interval = <20>; + gpios = <&pca9698 14 GPIO_ACTIVE_LOW>; + }; + + switch-8 { + linux,code = <KEY_8>; + label = "SW1-8"; + debounce-interval = <20>; + gpios = <&pca9698 15 GPIO_ACTIVE_LOW>; + }; + + }; }; &can0 { @@ -57,6 +121,44 @@ }; }; +&i2c2 { + pinctrl-0 = <&pins_i2c2>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = <400000>; + + pca9698: gpio@20 { + compatible = "nxp,pca9698"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + /* configure the analog switch to let i2c2 access the eeprom */ + max4662-in1-hog { + gpio-hog; + gpios = <16 0>; + output-high; + }; + max4662-in2-hog { + gpio-hog; + gpios = <17 0>; + output-low; + }; + max4662-in3-hog { + gpio-hog; + gpios = <18 0>; + output-low; + }; + }; + + /* Some revisions may have a 24cs64 at address 0x58 */ + eeprom@50 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x50>; + }; +}; + &mii_conv4 { renesas,miic-input = <MIIC_SWITCH_PORTB>; status = "okay"; @@ -68,6 +170,9 @@ }; &pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pins_cpld>; + pins_can0: pins_can0 { pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */ <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */ @@ -80,6 +185,13 @@ drive-strength = <6>; }; + pins_cpld: pins-cpld { + pinmux = <RZN1_PINMUX(119, RZN1_FUNC_USB)>, + <RZN1_PINMUX(120, RZN1_FUNC_USB)>, + <RZN1_PINMUX(121, RZN1_FUNC_USB)>, + <RZN1_PINMUX(122, RZN1_FUNC_USB)>; + }; + pins_eth3: pins_eth3 { pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, @@ -114,6 +226,12 @@ bias-disable; }; + pins_i2c2: pins_i2c2 { + pinmux = <RZN1_PINMUX(115, RZN1_FUNC_I2C)>, + <RZN1_PINMUX(116, RZN1_FUNC_I2C)>; + drive-strength = <12>; + }; + pins_mdio1: pins_mdio1 { pinmux = <RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)>, <RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)>; @@ -174,6 +292,10 @@ status = "okay"; }; +&udc { + status = "okay"; +}; + &wdt0 { timeout-sec = <60>; status = "okay"; diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts new file mode 100644 index 000000000000..97a339b30d76 --- /dev/null +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZN1D-EB Board + * + * Copyright (C) 2023 Schneider-Electric + * + */ + +#include <dt-bindings/leds/common.h> +#include "r9a06g032-rzn1d400-db.dts" + +/ { + model = "RZN1D-EB Board"; + compatible = "renesas,rzn1d400-eb", "renesas,rzn1d400-db", + "renesas,r9a06g032"; +}; + +&gmac1 { + pinctrl-0 = <&pins_eth0>, <&pins_mdio0>; + pinctrl-names = "default"; + + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy_mii0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy_mii0: ethernet-phy@8 { + reg = <8>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + }; + }; + }; + }; +}; + +&i2c2 { + /* Sensors are different across revisions. All are LM75B compatible */ + sensor@49 { + compatible = "national,lm75b"; + reg = <0x49>; + }; +}; + +&mii_conv1 { + renesas,miic-input = <MIIC_GMAC1_PORT>; + status = "okay"; +}; + +&mii_conv2 { + renesas,miic-input = <MIIC_SWITCH_PORTD>; + status = "okay"; +}; + +&mii_conv3 { + renesas,miic-input = <MIIC_SWITCH_PORTC>; + status = "okay"; +}; + +&pci_usb { + status = "okay"; +}; + +&pinctrl { + pins_eth0: pins-eth0 { + pinmux = <RZN1_PINMUX(0, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(1, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(2, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(3, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(4, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(5, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(6, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(7, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(8, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(9, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(10, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(11, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_eth1: pins-eth1 { + pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(14, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(15, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(16, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(17, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(18, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(19, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(20, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(21, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(22, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(23, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_eth2: pins-eth2 { + pinmux = <RZN1_PINMUX(24, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(25, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(26, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(27, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(28, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(29, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(30, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(31, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(32, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(33, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(34, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, + <RZN1_PINMUX(35, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>; + drive-strength = <6>; + bias-disable; + }; + + pins_mdio0: pins-mdio0 { + pinmux = <RZN1_PINMUX(150, RZN1_FUNC_MDIO0_GMAC0)>, + <RZN1_PINMUX(151, RZN1_FUNC_MDIO0_GMAC0)>; + }; + + pins_sdio1: pins-sdio1 { + pinmux = <RZN1_PINMUX(95, RZN1_FUNC_SDIO)>, + <RZN1_PINMUX(97, RZN1_FUNC_SDIO)>, + <RZN1_PINMUX(98, RZN1_FUNC_SDIO)>, + <RZN1_PINMUX(99, RZN1_FUNC_SDIO)>, + <RZN1_PINMUX(100, RZN1_FUNC_SDIO)>, + <RZN1_PINMUX(101, RZN1_FUNC_SDIO_E)>, + <RZN1_PINMUX(102, RZN1_FUNC_SDIO_E)>; + }; + + pins_sdio1_clk: pins-sdio1-clk { + pinmux = <RZN1_PINMUX(96, RZN1_FUNC_SDIO)>; + drive-strength = <12>; + }; + + pins_uart2: pins-uart2 { + pinmux = <RZN1_PINMUX(105, RZN1_FUNC_UART2)>, + <RZN1_PINMUX(106, RZN1_FUNC_UART2)>, + <RZN1_PINMUX(107, RZN1_FUNC_UART2)>, + <RZN1_PINMUX(108, RZN1_FUNC_UART2)>; + bias-disable; + }; +}; + +&sdio1 { + pinctrl-0 = <&pins_sdio1>, <&pins_sdio1_clk>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&switch { + pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>, + <&pins_mdio1>; + + mdio { + /* CN15 and CN16 switches must be configured in MDIO2 mode */ + switch0phy1: ethernet-phy@1 { + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + }; + }; + }; + + switch0phy10: ethernet-phy@10 { + reg = <10>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + default-state = "keep"; + }; + }; + }; + }; +}; + +&switch_port2 { + label = "lan2"; + phy-mode = "rgmii-id"; + phy-handle = <&switch0phy10>; + status = "okay"; +}; + +&switch_port3 { + label = "lan3"; + phy-mode = "rgmii-id"; + phy-handle = <&switch0phy1>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&pins_uart2>; + pinctrl-names = "default"; + status = "okay"; + uart-has-rtscts; +}; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 7548291c8d7e..80ad1fdc77a0 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -211,8 +211,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -224,8 +224,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -237,8 +237,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -250,8 +250,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,8 +263,30 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c1: i2c@40063000 { + compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; + reg = <0x40063000 0x100>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>; + clock-names = "ref", "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@40064000 { + compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; + reg = <0x40064000 0x100>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>; + clock-names = "ref", "pclk"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; @@ -276,6 +298,30 @@ status = "okay"; }; + sdio1: mmc@40100000 { + compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; + reg = <0x40100000 0x1000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int", "wakeup"; + clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>; + clock-names = "clk_xin", "clk_ahb"; + no-1-8-v; + status = "disabled"; + }; + + sdio2: mmc@40101000 { + compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; + reg = <0x40101000 0x1000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int", "wakeup"; + clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>; + clock-names = "clk_xin", "clk_ahb"; + no-1-8-v; + status = "disabled"; + }; + nand_controller: nand-controller@40102000 { compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; reg = <0x40102000 0x2000>; diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts index 4f928c7898e9..ae2f84a4e922 100644 --- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts @@ -8,6 +8,12 @@ model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + chosen { stdout-path = "serial2:115200n8"; }; @@ -382,6 +388,18 @@ status = "okay"; }; +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; + &vop { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 63b9912be06a..fca21ebb224b 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -213,6 +213,8 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -224,6 +226,8 @@ clocks = <&cru HCLK_OTG1>; clock-names = "otg"; dr_mode = "host"; + phys = <&usb2phy_host>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -342,6 +346,37 @@ grf: syscon@20008000 { compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usb2phy: usb2phy@17c { + compatible = "rockchip,rk3036-usb2phy"; + reg = <0x017c 0x20>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + assigned-clocks = <&cru SCLK_USB480M>; + assigned-clock-parents = <&usb2phy>; + #clock-cells = <0>; + status = "disabled"; + + usb2phy_host: host-port { + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_otg: otg-port { + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; power: power-controller { compatible = "rockchip,rk3036-power-controller"; @@ -398,8 +433,9 @@ compatible = "rockchip,rk3036-inno-hdmi"; reg = <0x20034000 0x4000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; + clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; + clock-names = "pclk", "ref"; + rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index ada7dbfc06a5..de42d1855121 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -19,6 +19,17 @@ reg = <0x60000000 0x40000000>; }; + hdmi_con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vdd_log: regulator-vdd-log { compatible = "pwm-regulator"; pwms = <&pwm3 0 1000>; @@ -58,6 +69,28 @@ cpu-supply = <&vdd_arm>; }; +&gpu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -216,6 +249,10 @@ status = "okay"; }; +&vop0 { + status = "okay"; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index d4572146d135..c49099954c28 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -48,7 +48,6 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; @@ -87,31 +86,38 @@ opp-216000000 { opp-hz = /bits/ 64 <216000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-696000000 { opp-hz = /bits/ 64 <696000000>; opp-microvolt = <975000 975000 1325000>; + clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1075000 1075000 1325000>; opp-suspend; + clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1325000>; + clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1325000 1325000 1325000>; + clock-latency-ns = <40000>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi index 44b54af0bbf9..850bd6e67895 100644 --- a/arch/arm/boot/dts/rockchip/rk3188.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3188.dtsi @@ -23,7 +23,6 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 96421355c274..cd11a018105b 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -36,7 +36,6 @@ resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; enable-method = "psci"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 3f1d640afafa..42d705b544ec 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -70,7 +70,6 @@ resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -81,7 +80,6 @@ resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -92,7 +90,6 @@ resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -103,7 +100,6 @@ resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -116,6 +112,7 @@ opp-126000000 { opp-hz = /bits/ 64 <126000000>; opp-microvolt = <900000>; + clock-latency-ns = <40000>; }; opp-216000000 { opp-hz = /bits/ 64 <216000000>; diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi index f3291f3bbc6f..42a4d72597a5 100644 --- a/arch/arm/boot/dts/rockchip/rv1108.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -32,7 +32,6 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <75>; diff --git a/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi index 9a87dc0d5f66..1aedcd3a2167 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi @@ -323,15 +323,15 @@ }; &pmu_io_domains { - pmuio0-supply = <&vcc1v8_pmu>; + pmuio0-supply = <&vcc3v3_sys>; pmuio1-supply = <&vcc3v3_sys>; vccio1-supply = <&vcc_1v8>; vccio2-supply = <&vccio_sd>; vccio3-supply = <&vcc3v3_sd>; - vccio4-supply = <&vcc_dovdd>; - vccio5-supply = <&vcc_1v8>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_dovdd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_1v8>; status = "okay"; }; @@ -342,16 +342,14 @@ &sdio { bus-width = <4>; - cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <50000000>; + max-frequency = <25000000>; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; rockchip,default-sample-phase = <90>; - sd-uhs-sdr50; vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vcc_1v8>; status = "okay"; diff --git a/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi index f628d3660493..153514e80c9a 100644 --- a/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210-aries.dtsi @@ -855,7 +855,7 @@ assigned-clock-rates = <0>, <50000000>; assigned-clock-parents = <&clocks MOUT_MPLL>; - wlan@1 { + wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gph2>; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index b7d5d305cbbe..cc9948b9870f 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -28,7 +28,9 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32h747i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ @@ -37,8 +39,11 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-dhcor-testbench.dtb \ stm32mp151c-mecio1r0.dtb \ stm32mp151c-mect1s.dtb \ + stm32mp151c-plyaqm.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp153c-lxa-fairytux2-gen1.dtb \ + stm32mp153c-lxa-fairytux2-gen2.dtb \ stm32mp153c-lxa-tac-gen3.dtb \ stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ @@ -66,7 +71,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-osd32mp1-red.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb + stm32mp157c-phycore-stm32mp1-3.dtb \ + stm32mp157c-ultra-fly-sbc.dtb dtb-$(CONFIG_ARCH_U8500) += \ ste-snowball.dtb \ ste-hrefprev60-stuib.dtb \ diff --git a/arch/arm/boot/dts/st/spear1310-evb.dts b/arch/arm/boot/dts/st/spear1310-evb.dts index ad216571ba57..089bd7db55c7 100644 --- a/arch/arm/boot/dts/st/spear1310-evb.dts +++ b/arch/arm/boot/dts/st/spear1310-evb.dts @@ -205,19 +205,19 @@ }; }; - ehci@e4800000 { + usb@e4800000 { status = "okay"; }; - ehci@e5800000 { + usb@e5800000 { status = "okay"; }; - ohci@e4000000 { + usb@e4000000 { status = "okay"; }; - ohci@e5000000 { + usb@e5000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts index 9b515b21a633..d24146c3c9e8 100644 --- a/arch/arm/boot/dts/st/spear1340-evb.dts +++ b/arch/arm/boot/dts/st/spear1340-evb.dts @@ -203,7 +203,7 @@ }; }; - ehci@e4800000 { + usb@e4800000 { status = "okay"; }; @@ -221,7 +221,7 @@ }; }; - ehci@e5800000 { + usb@e5800000 { status = "okay"; }; @@ -238,11 +238,11 @@ status = "okay"; }; - ohci@e4000000 { + usb@e4000000 { status = "okay"; }; - ohci@e5000000 { + usb@e5000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi index 3b6897084e26..76749992394d 100644 --- a/arch/arm/boot/dts/st/spear13xx.dtsi +++ b/arch/arm/boot/dts/st/spear13xx.dtsi @@ -174,7 +174,7 @@ status = "disabled"; }; - ehci@e4800000 { + usb@e4800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe4800000 0x1000>; interrupts = <0 64 0x4>; @@ -182,7 +182,7 @@ status = "disabled"; }; - ehci@e5800000 { + usb@e5800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe5800000 0x1000>; interrupts = <0 66 0x4>; @@ -190,7 +190,7 @@ status = "disabled"; }; - ohci@e4000000 { + usb@e4000000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe4000000 0x1000>; interrupts = <0 65 0x4>; @@ -198,7 +198,7 @@ status = "disabled"; }; - ohci@e5000000 { + usb@e5000000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe5000000 0x1000>; interrupts = <0 67 0x4>; diff --git a/arch/arm/boot/dts/st/spear300-evb.dts b/arch/arm/boot/dts/st/spear300-evb.dts index 303ef29fb805..7d4e6412d558 100644 --- a/arch/arm/boot/dts/st/spear300-evb.dts +++ b/arch/arm/boot/dts/st/spear300-evb.dts @@ -119,15 +119,15 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear310-evb.dts b/arch/arm/boot/dts/st/spear310-evb.dts index ea0b53036f7b..459182210825 100644 --- a/arch/arm/boot/dts/st/spear310-evb.dts +++ b/arch/arm/boot/dts/st/spear310-evb.dts @@ -133,15 +133,15 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear320-evb.dts b/arch/arm/boot/dts/st/spear320-evb.dts index 3c026d021c92..6ac53d993cf3 100644 --- a/arch/arm/boot/dts/st/spear320-evb.dts +++ b/arch/arm/boot/dts/st/spear320-evb.dts @@ -142,15 +142,15 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear320-hmi.dts b/arch/arm/boot/dts/st/spear320-hmi.dts index 721e5ee7b680..8010918e5257 100644 --- a/arch/arm/boot/dts/st/spear320-hmi.dts +++ b/arch/arm/boot/dts/st/spear320-hmi.dts @@ -92,7 +92,7 @@ status = "okay"; }; - ehci@e1800000 { + usb@e1800000 { status = "okay"; }; @@ -147,11 +147,11 @@ }; }; - ohci@e1900000 { + usb@e1900000 { status = "okay"; }; - ohci@e2100000 { + usb@e2100000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/spear3xx.dtsi b/arch/arm/boot/dts/st/spear3xx.dtsi index cc88ebe7a60c..f54bb80ba28a 100644 --- a/arch/arm/boot/dts/st/spear3xx.dtsi +++ b/arch/arm/boot/dts/st/spear3xx.dtsi @@ -73,21 +73,21 @@ status = "disabled"; }; - ehci@e1800000 { + usb@e1800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe1800000 0x1000>; interrupts = <26>; status = "disabled"; }; - ohci@e1900000 { + usb@e1900000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe1900000 0x1000>; interrupts = <25>; status = "disabled"; }; - ohci@e2100000 { + usb@e2100000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe2100000 0x1000>; interrupts = <27>; diff --git a/arch/arm/boot/dts/st/spear600.dtsi b/arch/arm/boot/dts/st/spear600.dtsi index 6b67c0ceaed9..9a93367445ca 100644 --- a/arch/arm/boot/dts/st/spear600.dtsi +++ b/arch/arm/boot/dts/st/spear600.dtsi @@ -91,7 +91,7 @@ status = "disabled"; }; - ehci_usb0: ehci@e1800000 { + ehci_usb0: usb@e1800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe1800000 0x1000>; interrupt-parent = <&vic1>; @@ -99,7 +99,7 @@ status = "disabled"; }; - ehci_usb1: ehci@e2000000 { + ehci_usb1: usb@e2000000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe2000000 0x1000>; interrupt-parent = <&vic1>; @@ -107,7 +107,7 @@ status = "disabled"; }; - ohci_usb0: ohci@e1900000 { + ohci_usb0: usb@e1900000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe1900000 0x1000>; interrupt-parent = <&vic1>; @@ -115,7 +115,7 @@ status = "disabled"; }; - ohci_usb1: ohci@e2100000 { + ohci_usb1: usb@e2100000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe2100000 0x1000>; interrupt-parent = <&vic1>; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 087de6f09629..b57dbdce2f40 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -78,6 +78,24 @@ serial0 = &usart1; }; + leds { + compatible = "gpio-leds"; + led-usr { + gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = <KEY_HOME>; + gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 2537b3d47e6f..208f8c6dfc9d 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -43,6 +43,7 @@ #include "../armv7-m.dtsi" #include <dt-bindings/clock/stm32fx-clock.h> #include <dt-bindings/mfd/stm32f7-rcc.h> +#include <dt-bindings/interrupt-controller/irq.h> / { #address-cells = <1>; @@ -245,6 +246,39 @@ }; }; + lptimer1: timer@40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + interrupts-extended = <&exti 23 IRQ_TYPE_EDGE_RISING>; + clocks = <&rcc 1 CLK_LPTIMER>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + rtc: rtc@40002800 { compatible = "st,stm32-rtc"; reg = <0x40002800 0x400>; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 52c5baf58ab9..535cfdc4681c 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -79,13 +79,16 @@ leds { compatible = "gpio-leds"; - led-green { + led-usr2 { gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - led-red { + led-usr1 { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; + led-usr3 { + gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; + }; }; gpio-keys { diff --git a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi index 7f1d234e1024..8a6db484383d 100644 --- a/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32h7-pinctrl.dtsi @@ -198,7 +198,7 @@ }; }; - uart4_pins: uart4-0 { + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */ bias-disable; @@ -211,7 +211,20 @@ }; }; - usart1_pins: usart1-0 { + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('J', 8, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('J', 9, AF8)>; /* UART8_RX */ + bias-disable; + }; + }; + + usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ bias-disable; @@ -224,7 +237,20 @@ }; }; - usart2_pins: usart2-0 { + usart1_pins_b: usart1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */ + bias-disable; + }; + }; + + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ bias-disable; @@ -237,7 +263,7 @@ }; }; - usart3_pins: usart3-0 { + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */ diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi index b8d4c44c8a82..2f19cfbc57ad 100644 --- a/arch/arm/boot/dts/st/stm32h743.dtsi +++ b/arch/arm/boot/dts/st/stm32h743.dtsi @@ -211,6 +211,14 @@ }; }; + uart8: serial@40007c00 { + compatible = "st,stm32h7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + status = "disabled"; + clocks = <&rcc UART8_CK>; + }; + usart1: serial@40011000 { compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts index 2b452883a708..8451a54a9a08 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -105,7 +105,7 @@ }; &usart2 { - pinctrl-0 = <&usart2_pins>; + pinctrl-0 = <&usart2_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts index 5c5d8059bdc7..4b0ced27b80e 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -145,7 +145,7 @@ }; &usart1 { - pinctrl-0 = <&usart1_pins>; + pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts new file mode 100644 index 000000000000..99f0255dae8e --- /dev/null +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com> + */ + +/dts-v1/; +#include "stm32h743.dtsi" +#include "stm32h7-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "STMicroelectronics STM32H747i-Discovery board"; + compatible = "st,stm32h747i-disco", "st,stm32h747"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory@d0000000 { + device_type = "memory"; + reg = <0xd0000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + serial1 = &uart8; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + led-green { + gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + led-orange { + gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; + }; + led-red { + gpios = <&gpioi 14 GPIO_ACTIVE_LOW>; + }; + led-blue { + gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + }; + button-1 { + label = "JoySel"; + linux,code = <KEY_ENTER>; + gpios = <&gpiok 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-2 { + label = "JoyDown"; + linux,code = <KEY_DOWN>; + gpios = <&gpiok 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-3 { + label = "JoyUp"; + linux,code = <KEY_UP>; + gpios = <&gpiok 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-4 { + label = "JoyLeft"; + linux,code = <KEY_LEFT>; + gpios = <&gpiok 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + button-5 { + label = "JoyRight"; + linux,code = <KEY_RIGHT>; + gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&mac { + status = "disabled"; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart8 { + pinctrl-0 = <&uart8_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts index 44c307f8b09c..56c53e262da7 100644 --- a/arch/arm/boot/dts/st/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/st/stm32h750i-art-pi.dts @@ -167,7 +167,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; @@ -197,14 +197,14 @@ }; &usart2 { - pinctrl-0 = <&usart2_pins>; + pinctrl-0 = <&usart2_pins_a>; pinctrl-names = "default"; status = "disabled"; }; &usart3 { pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins>; + pinctrl-0 = <&usart3_pins_a>; dmas = <&dmamux1 45 0x400 0x05>, <&dmamux1 46 0x400 0x05>; dma-names = "rx", "tx"; @@ -221,7 +221,7 @@ }; &uart4 { - pinctrl-0 = <&uart4_pins>; + pinctrl-0 = <&uart4_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 0019d12c3d3d..492bcf586361 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -100,6 +100,31 @@ always-on; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -919,6 +944,16 @@ }; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DTS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -983,6 +1018,9 @@ reg = <0x4 0x2>; bits = <0 12>; }; + vrefint: vrefin-cal@52 { + reg = <0x52 0x2>; + }; ts_cal1: calib@5c { reg = <0x5c 0x2>; }; @@ -1028,6 +1066,8 @@ interrupts = <0>; dmas = <&dmamux1 10 0x400 0x80000001>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@13 { diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 73e470019ce4..e48838374f0d 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -60,6 +60,8 @@ interrupts = <0>; dmas = <&dmamux1 9 0x400 0x80000001>; dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; status = "disabled"; channel@18 { diff --git a/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts b/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts new file mode 100644 index 000000000000..663b6de1b814 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp133c-prihmb.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> +#include "stm32mp133.dtsi" +#include "stm32mp13xc.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "Priva E-Measuringbox board"; + compatible = "pri,prihmb", "st,stm32mp133"; + + aliases { + ethernet0 = ðernet1; + mdio-gpio0 = &mdio0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart6; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + counter-0 { + compatible = "interrupt-counter"; + gpios = <&gpioa 11 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-reset { + label = "reset-button"; + linux,code = <BTN_1>; + gpios = <&gpioi 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + led-controller-0 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm2 2 1000000 1>; + }; + + led-green { + active-low; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm1 1 1000000 1>; + }; + + led-blue { + active-low; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm1 2 1000000 1>; + }; + }; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm1 0 1000000 1>; + }; + + led-green { + active-low; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm2 0 1000000 1>; + }; + + led-blue { + active-low; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm2 1 1000000 1>; + }; + }; + }; + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@ce000000 { + reg = <0xce000000 0x02000000>; + no-map; + }; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc_1_pins_a>; + vdda-supply = <®_3v3>; + vref-supply = <®_3v3>; + status = "okay"; +}; + +&adc1 { + status = "okay"; + + channel@0 { /* Fan current PC0*/ + reg = <0>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@11 { /* Fan voltage */ + reg = <11>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@15 { /* Supply voltage */ + reg = <15>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; +}; + +&dts { + status = "okay"; +}; + +ðernet1 { + status = "okay"; + pinctrl-0 = <ðernet1_rmii_pins_a>; + pinctrl-1 = <ðernet1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + board-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + vs-supply = <®_3v3>; + }; +}; + +&{i2c1_pins_a/pins} { + pinmux = <STM32_PINMUX('D', 3, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('B', 8, AF4)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; +}; + +&{i2c1_sleep_pins_a/pins} { + pinmux = <STM32_PINMUX('D', 3, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('B', 8, ANALOG)>; /* I2C1_SDA */ +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + mmc-ddr-3_3v; + bus-width = <8>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers1 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm1: pwm { + pinctrl-0 = <&pwm1_pins_a>; + pinctrl-1 = <&pwm1_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers4 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm2: pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +/* Fan PWM */ +&timers5 { + status = "okay"; + + pwm3: pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers2 { + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart6 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_sleep_pins_a>; + pinctrl-2 = <&usart6_idle_pins_a>; + linux,rs485-enabled-at-boot-time; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&pinctrl { + adc_1_pins_a: adc1-0 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1 in0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ADC1 in15 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1 in11 */ + }; + }; + + ethernet1_rmii_pins_a: rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>; /* ETH1_RMII_REF_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet1_rmii_sleep_pins_a: rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + + pwm1_pins_a: pwm1-0 { + pins { + pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ + <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ + <STM32_PINMUX('E', 13, AF1)>; /* TIM1_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ + <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ + <STM32_PINMUX('E', 13, ANALOG)>; /* TIM1_CH3 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF2)>, /* TIM4_CH1 */ + <STM32_PINMUX('B', 7, AF2)>, /* TIM4_CH2 */ + <STM32_PINMUX('D', 14, AF2)>; /* TIM4_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* TIM4_CH1 */ + <STM32_PINMUX('B', 7, ANALOG)>, /* TIM4_CH2 */ + <STM32_PINMUX('D', 14, ANALOG)>; /* TIM4_CH3 */ + }; + }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */ + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* TIM5_CH1 */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('E', 10, ANALOG)>; /* UART7_RX */ + }; + }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, AF7)>, /* USART6_TX */ + <STM32_PINMUX('F', 10, AF7)>; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 11, AF7)>; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>; /* USART6_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('F', 10, AF7)>; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('H', 11, AF7)>; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('F', 10, ANALOG)>, /* USART6_DE */ + <STM32_PINMUX('H', 11, ANALOG)>; /* USART6_RX */ + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 853dc21449d9..9902849ed040 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -176,7 +176,7 @@ gpio-line-names = "", "", "", "", "", "DHSBC_USB_PWR_CC1", "", "", "", "", "", "DHSBC_nETH1_RST", - "", "DHCOR_HW-CODING_0", "", ""; + "", "DHCOR_HW-CODING_0", "", "DHSBC_HW-CODE_2"; }; &gpiob { @@ -197,7 +197,7 @@ gpio-line-names = "", "", "", "", "", "DHCOR_RAM-CODING_0", "", "", "", "DHCOR_RAM-CODING_1", "", "", - "", "", "", ""; + "", "DHSBC_HW-CODE_1", "", ""; }; &gpioe { @@ -221,6 +221,13 @@ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; }; +&gpioh { + gpio-line-names = "", "", "", "DHSBC_HW-CODE_0", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + &gpioi { gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", @@ -296,6 +303,9 @@ st33htph: tpm@0 { compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; reg = <0>; + interrupt-parent = <&gpioe>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; spi-max-frequency = <24000000>; }; }; @@ -419,3 +429,19 @@ type = "micro"; }; }; + +/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 19a32f7d4d7d..9764a6bfa5b4 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -421,7 +421,7 @@ #size-cells = <0>; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index 6236ce2a6968..c18156807027 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -287,7 +287,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { /* muRata 1YN */ + brcmf: wifi@1 { /* muRata 1YN */ reg = <1>; compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; interrupt-parent = <&gpioe>; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 95fafc51a1c8..40605ea85ee1 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -26,6 +26,13 @@ }; /omit-if-no-ref/ + adc1_in10_pins_a: adc1-in10-0 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; + }; + }; + + /omit-if-no-ref/ adc12_ain_pins_a: adc12-ain-0 { pins { pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ @@ -585,6 +592,43 @@ }; /omit-if-no-ref/ + ethernet0_rmii_pins_d: rmii-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + ethernet0_rmii_sleep_pins_d: rmii-sleep-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 12, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('B', 13, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + + /omit-if-no-ref/ fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -726,6 +770,25 @@ }; /omit-if-no-ref/ + i2c1_pins_c: i2c1-2 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_c: i2c1-sleep-2 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('D', 13, ANALOG)>; /* I2C1_SDA */ + }; + }; + + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ @@ -820,6 +883,27 @@ }; /omit-if-no-ref/ + i2s1_pins_a: i2s1-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, AF5)>, /* I2S2_SDI */ + <STM32_PINMUX('A', 4, AF5)>, /* I2S2_WS */ + <STM32_PINMUX('A', 5, AF5)>; /* I2S2_CK */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + i2s1_sleep_pins_a: i2s1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, ANALOG)>, /* I2S2_SDI */ + <STM32_PINMUX('A', 4, ANALOG)>, /* I2S2_WS */ + <STM32_PINMUX('A', 5, ANALOG)>; /* I2S2_CK */ + }; + }; + + /omit-if-no-ref/ i2s2_pins_a: i2s2-0 { pins { pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ @@ -1419,6 +1503,23 @@ }; /omit-if-no-ref/ + pwm1_pins_d: pwm1-3 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF2)>; /* TIM5_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm1_sleep_pins_d: pwm1-sleep-3 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; + }; + }; + + /omit-if-no-ref/ pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -2161,6 +2262,66 @@ }; /omit-if-no-ref/ + sdmmc2_b4_pins_c: sdmmc2-b4-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_c: sdmmc2-b4-od-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_c: sdmmc2-b4-sleep-2 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ @@ -2390,6 +2551,66 @@ }; /omit-if-no-ref/ + sdmmc3_b4_pins_c: sdmmc3-b4-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ + <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_c: sdmmc3-b4-od-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_c: sdmmc3-b4-sleep-2 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ + <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ + <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ + <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ + }; + }; + + /omit-if-no-ref/ spdifrx_pins_a: spdifrx-0 { pins { pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ @@ -2601,6 +2822,41 @@ }; /omit-if-no-ref/ + uart4_pins_e: uart4-4 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 8, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_e: uart4-idle-4 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 8, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_e: uart4-sleep-4 { + pins { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 8, ANALOG)>; /* UART4_RX */ + }; + }; + + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ @@ -2678,6 +2934,23 @@ }; /omit-if-no-ref/ + uart7_pins_d: uart7-3 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>, /* UART7_TX */ + <STM32_PINMUX('F', 8, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ + <STM32_PINMUX('F', 9, AF7)>; /* UART7_CTS */ + bias-disable; + }; + }; + + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -3119,6 +3392,25 @@ }; /omit-if-no-ref/ + i2c6_pins_b: i2c6-1 { + pins { + pinmux = <STM32_PINMUX('A', 11, AF2)>, /* I2C6_SCL */ + <STM32_PINMUX('A', 12, AF2)>; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c6_sleep_pins_b: i2c6-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C6_SCL */ + <STM32_PINMUX('A', 12, ANALOG)>; /* I2C6_SDA */ + }; + }; + + /omit-if-no-ref/ spi1_pins_a: spi1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b9a87fbe971d..0daa8ffe2ff5 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -1781,7 +1781,6 @@ st,syscon = <&syscfg 0x4>; snps,mixed-burst; snps,pbl = <2>; - snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; access-controllers = <&etzpc 94>; diff --git a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts new file mode 100644 index 000000000000..39a3211c6133 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include <arm/st/stm32mp151.dtsi> +#include <arm/st/stm32mp15xc.dtsi> +#include <arm/st/stm32mp15-pinctrl.dtsi> +#include <arm/st/stm32mp15xxad-pinctrl.dtsi> +#include <arm/st/stm32mp15-scmi.dtsi> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Plymovent AQM board"; + compatible = "ply,plyaqm", "st,stm32mp151"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &uart7; + }; + + codec { + compatible = "invensense,ics43432"; + + port { + codec_endpoint: endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; /* WHITE_EN */ + color = <LED_COLOR_ID_WHITE>; + default-state = "on"; + }; + }; + + v3v3: fixed-regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v5v_sw: fixed-regulator-v5sw { + compatible = "regulator-fixed"; + regulator-name = "5v-switched"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpioe 10 GPIO_ACTIVE_HIGH>; /* 5V_SWITCHED_EN */ + startup-delay-us = <100000>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@cfd00000 { + reg = <0xcfd00000 0x300000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP15"; + dais = <&i2s1_port>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; /* WLAN_REG_ON */ + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in10_pins_a>; + vdda-supply = <&v3v3>; + vref-supply = <&v3v3>; + status = "okay"; + + adc@0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@10 { /* NTC */ + reg = <10>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; + status = "okay"; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rmii_pins_d>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_d>; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + /* KSZ8081RNA PHY */ + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpiob 0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_PL_N", "HWID_CP", ""; +}; + +&gpiob { + gpio-line-names = + "", "", "", "", "", "", "LED_LATCH", "", + "", "RELAY1_EN", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_Q7", "", ""; +}; + +&gpioe { + gpio-line-names = + "", "", "", "", "RELAY2_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "SW1", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_c>; + pinctrl-1 = <&i2c1_sleep_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&i2c6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_b>; + pinctrl-1 = <&i2c6_sleep_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clocks = <&scmi_clk CK_SCMI_I2C6>; + resets = <&scmi_reset RST_SCMI_I2C6>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pressure-sensor@47 { + compatible = "bosch,bmp580"; + reg = <0x47>; + vdda-supply = <&v5v_sw>; + vddd-supply = <&v5v_sw>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + vdd-supply = <&v5v_sw>; + }; + + pm-sensor@69 { + compatible = "sensirion,sps30"; + reg = <0x69>; + }; +}; + +&i2s1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s1_pins_a>; + pinctrl-1 = <&i2s1_sleep_pins_a>; + clocks = <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + #clock-cells = <0>; /* Set I2S2 as master clock provider */ + status = "okay"; + + i2s1_port: port { + i2s1_endpoint: endpoint { + format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_endpoint>; + }; + }; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status = "okay"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; + status = "okay"; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_c &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_c &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_c &sdmmc2_d47_sleep_pins_b>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_c>; + pinctrl-1 = <&sdmmc3_b4_od_pins_c>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_c>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&timers5 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm { + pinctrl-0 = <&pwm1_pins_d>; + pinctrl-1 = <&pwm1_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_e>; + pinctrl-1 = <&uart4_idle_pins_e>; + pinctrl-2 = <&uart4_sleep_pins_e>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_d>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; /* BT_REG_ON */ + max-speed = <4000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; /* BT_HOST_WAKE */ + interrupt-names = "host-wakeup"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts new file mode 100644 index 000000000000..3a0e84262424 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen1.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 1"; + compatible = "lxa,stm32mp153c-fairytux2-gen1", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = <KEY_ESC>; + gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = <KEY_HOME>; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "GPIO3", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "LED2_GK_YA", + "RS485_EN", "RS485_120R", "", "CAN_120R"; + }; +}; + +&led_controller_io { + /* + * led-2 and led-3 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO1 ---+---|led-2|>--+--- GPIO3 + * +--<|led-3|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usart3 { + /* + * On Gen 1 FairyTux 2 only RTS can be used and not CTS as well, + * Because pins PD11 (CTS) and PI11 (USER_BTN1) share the same + * interrupt and only one of them can be used at a time. + */ + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + dr_mode = "peripheral"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts new file mode 100644 index 000000000000..66e6da912508 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2-gen2.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 2"; + compatible = "lxa,stm32mp153c-fairytux2-gen2", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = <KEY_ESC>; + gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = <KEY_HOME>; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "GPIO1", "GPIO_INT", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "GPIO2", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpioh>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&board_tca6408_pins>; + #interrupt-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "USB_CC_ALERT", + "RS485_EN", "RS485_120R", "USB_CC_RESET", "CAN_120R"; + }; + + usb_c: typec@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupt-parent = <&io_board_gpio>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_5v>; + vsys-supply = <&v3v3_hdmi>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + /* + * The sensor itself is powered by a voltage divider from the + * always-on 5V supply. + * The required pull-up resistors however are on v3v3_hdmi. + */ + vs-supply = <&v3v3_hdmi>; + }; + + io_board_eeprom: eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + vcc-supply = <&v3v3_hdmi>; + }; +}; + +&rtc { + status = "okay"; +}; + +&led_controller_io { + led-2 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_LOW>; + }; +}; + +&usart3 { + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + usb-role-switch; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; +}; + +&pinctrl { + board_tca6408_pins: stusb1600-0 { + pins { + pinmux = <STM32_PINMUX('H', 13, GPIO)>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi new file mode 100644 index 000000000000..9eeb9d6b5eb0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-fairytux2.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix + */ + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + can0 = &m_can1; + ethernet0 = ðernet0; + i2c0 = &i2c1; + i2c1 = &i2c4; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart3; + spi0 = &spi4; + }; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + led-controller-cpu { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + led_controller_io: led-controller-io { + compatible = "gpio-leds"; + + /* + * led-0 and led-1 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO0 ---+---|led-0|>--+--- GPIO2 + * +--<|led-1|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 0 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 2 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_5v>; + }; +}; + +baseboard_eeprom: &sip_eeprom { +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + + st,eth-clk-sel; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiob { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpiod { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "LCD_TE", "", "", /* 5 */ + "LCD_DC", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioe { + gpio-line-names = "LCD_CS", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiog { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", /* 0 */ + "", "HWID4", "HWID5"; /* 5 */ +}; + +&hash1 { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <8>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; + termination-gpios = <&io_board_gpio 7 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&pmic { + regulators { + buck1-supply = <®_5v>; /* VIN */ + buck2-supply = <®_5v>; /* VIN */ + buck3-supply = <®_5v>; /* VIN */ + buck4-supply = <®_5v>; /* VIN */ + ldo2-supply = <®_5v>; /* PMIC_LDO25IN */ + ldo4-supply = <®_5v>; /* VIN */ + ldo5-supply = <®_5v>; /* PMIC_LDO25IN */ + vref_ddr-supply = <®_5v>; /* VIN */ + boost-supply = <®_5v>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + vmmc-supply = <&v3v3>; + + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + lcd: display@0 { + compatible = "shineworld,lh133k", "panel-mipi-dbi-spi"; + reg = <0>; + power-supply = <&v3v3>; + io-supply = <&v3v3>; + backlight = <&backlight>; + dc-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + spi-3wire; + spi-max-frequency = <32000000>; + + width-mm = <23>; + height-mm = <23>; + rotation = <180>; + + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&timers3 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + label = "debug"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usart3 { + label = "external"; + + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + + vusb_d-supply = <&vdd_usb>; + vusb_a-supply = <®18>; + + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&v3v3_hdmi { + regulator-enable-ramp-delay = <1000>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts index 6a5a4af25bd9..84497026a106 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-iot-box.dts @@ -46,7 +46,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 5f9c0160a9c4..1b34fbe10b4f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -67,7 +67,7 @@ touchscreen@38 { compatible = "focaltech,ft6236"; reg = <0x38>; - interrupts = <2 2>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpiof>; touchscreen-size-x = <480>; touchscreen-size-y = <800>; @@ -115,7 +115,7 @@ #size-cells = <0>; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts b/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts new file mode 100644 index 000000000000..ac42d462d449 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts @@ -0,0 +1,1152 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Ultratronik GmbH 2024-2025 - All Rights Reserved + */ + +/dts-v1/; +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include <dt-bindings/pinctrl/stm32-pinfunc.h> +#include <dt-bindings/mfd/st,stpmic1.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "STM STM32MP15x Ultratronik MMI_A7 board"; + compatible = "ultratronik,stm32mp157c-ultra-fly-sbc", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &uart5; + serial2 = &uart7; + serial3 = &usart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x40000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpioh 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x2000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10044000 { + compatible = "shared-dma-pool"; + reg = <0x10044000 0x4000>; + no-map; + }; + + gpu_reserved: gpu@f8000000 { + reg = <0xf8000000 0x8000000>; + no-map; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led0{ + label = "buzzer"; + gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "none"; + }; + + led1 { + label = "led1"; + gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "led2"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3 { + label = "led3"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + key-1 { + label = "KEY1"; + gpios = <&gpiod 1 GPIO_ACTIVE_HIGH>; + wakeup-source; + linux,code = <2>; + }; + + key-2 { + label = "KEY2"; + gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>; + wakeup-source; + linux,code = <3>; + }; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_ux_ain_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <0 1 6 13>; /* ANA0 ANA1 PF12 PC3 */ + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 12>; /* ANA0 ANA1 INT_TEMP*/ + st,min-sample-time-nsecs = <10000>; + status = "okay"; + + channel@12 { + reg = <12>; /* Channel 12 = internal temperature sensor */ + label = "internal_temp"; + }; + }; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ux_ch1_pins_a &dac_ux_ch2_pins_a>; + vref-supply = <&vrefbuf>; + status = "okay"; + + dac1: dac@1 { + status = "okay"; + }; + + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + compatible = "st,stm32-thermal"; + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_ux_rgmii_pins_a>; + pinctrl-1 = <ðernet0_ux_rgmii_pins_sleep_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&gpioa { + gpio-line-names = + "#PMIC_IRQ", "", "", "", "DAC1", "DAC2", "", "", + "", "", "OTG_ID", "TIM1_4", "#LED1", "#LED2", "#LED3", ""; +}; + +&gpiob { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names = + "#AMP_SD", "", "", "ANA5", "", "", "", "", + "", "", "", "", "", "PMIC_WAKEUP", "", ""; +}; + +&gpiod { + gpio-line-names = + "#G_INT", "#TASTER1", "", "", "GPIO1", "GPIO2", "", "#TASTER2", + "", "", "", "", "", "", "TIM4_3", "TIM4_4"; +}; + +&gpioe { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "PWM2", "", "", "", "", ""; +}; + +&gpiof { + gpio-line-names = + "#SD1_CD", "SD1_WP", "BUZZER", "#DISP_POW", "BKL_POW", "#CAM_RES", "", "", + "", "TIM17_1N", "", "CAM_PWDN", "ANA6", "ENA_USB", "", ""; +}; + +&gpiog { + gpio-line-names = + "#ESP_RES", "#ESP_BOOT", "GPIO3", "GPIO4", "", "", "", "", + "", "#TOUCH_IRQ", "", "", "", "", "", "#PCAP_RES"; +}; + +&gpioh { + gpio-line-names = + "", "CAM_LED", "", "USB_OTG_PWR", "", "USB_OTG_OC", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpioi { + gpio-line-names = + "BKL_PWM", "", "", "", "", "", "", "", + "#SPI_CS0", "", "", "#SPI_CS1", "", "", "", ""; +}; + +&gpioj { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiok { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + gpio-line-names = + "", "", "", "#SPI_CS2", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_ux_pins_a>; + pinctrl-1 = <&i2c1_ux_pins_sleep_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + epson,vdet-disable; + trickle-diode-disable; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_ux_pins_a>; + pinctrl-1 = <&i2c4_ux_pins_sleep_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: pmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&exti 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1600000>;/* offset +200 mv ??? */ + regulator-max-microvolt = <1600000>;/* real 1800000 */ + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge = <1>; + }; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_ux_pins_a>; + pinctrl-1 = <&m_can2_ux_sleep_pins_a>; + status = "okay"; +}; + +&pinctrl { + + adc1_ux_ain_pins_a: adc1-ux-ain-0 { + pins { + pinmux = <STM32_PINMUX('F',12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('C', 3, ANALOG)>; /* ADC2 in13 */ + }; + }; + + dac_ux_ch1_pins_a: dac-ux-ch1-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>; + }; + }; + + dac_ux_ch2_pins_a: dac-ux-ch2-0 { + pins { + pinmux = <STM32_PINMUX('A', 5, ANALOG)>; + }; + }; + + ethernet0_ux_rgmii_pins_a: rgmii-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + ethernet0_ux_rgmii_pins_sleep_a: rgmii-ux-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + + i2c1_ux_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_ux_pins_sleep_a: i2c1-1 { + pins { + pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ + }; + }; + + m_can2_ux_pins_a: m-can2-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN1_TX */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can2_ux_sleep_pins_a: m-can2-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('B', 5, ANALOG)>; /* CAN1_RX */ + }; + }; + pwm1_ux_pins_a: pwm1-0 { + pins { + pinmux = <STM32_PINMUX('A',11, AF1)>, /* TIM1_CH4 */ + <STM32_PINMUX('E',10, AF1)>; /* TIM1_CH2N */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_ux_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A',11, ANALOG)>, /* TIM1_CH4 */ + <STM32_PINMUX('E',10, ANALOG)>; /* TIM1_CH2N */ + }; + }; + + pwm4_ux_pins_a: pwm4-0 { + pins { + pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ + <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ + bias-disable; + }; + }; + + pwm4_ux_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ + <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ + }; + }; + + pwm5_ux_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_ux_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ + }; + }; + + pwm17_ux_pins_a: pwm17-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, AF1)>; /* TIM17_CH1N */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm17_ux_sleep_pins_a: pwm17-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM17_CH1N */ + }; + }; + + qspi_bk1_ux_pins_a: qspi-bk1-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('D',12, AF9)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B',10, AF9)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_ux_sleep_pins_a: qspi-bk1-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('D',12, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ + <STM32_PINMUX('B',10, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + qspi_clk_ux_pins_a: qspi-clk_ux-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_ux_sleep_pins_a: qspi-clk-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_CLK */ + }; + }; + + sai2a_ux_pins_a: sai2a-0 { + pins { + pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D',11, AF10)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_ux_sleep_pins_a: sai2a-1 { + pins { + pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ + <STM32_PINMUX('D',11, ANALOG)>, /* SAI2_SD_A */ + <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ + <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ + }; + }; + + sdmmc1_ux_b4_pins_a: sdmmc1-ux-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C',10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C',11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_ux_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_ux_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc2_ux_b4_pins_a: sdmmc2-ux-b4-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_ux_b4_od_pins_a: sdmmc2-ux-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_ux_b4_sleep_pins_a: sdmmc2-ux-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_ux_d47_pins_a: sdmmc2-ux-d47-0 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_ux_d47_sleep_pins_a: sdmmc2-ux-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + uart4_ux_pins_a: uart4-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_ux_idle_pins_a: uart4-ux-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_ux_sleep_pins_a: uart4-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; + }; + + uart5_ux_pins_a: uart5-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF14)>; /* UART5_RX */ + bias-disable; + }; + }; + + uart5_ux_idle_pins_a: uart5-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 13, ANALOG)>; /* UART5_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF14)>; /* UART5_RX*/ + bias-disable; + }; + }; + + uart5_ux_sleep_pins_a: uart5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* UART5_TX */ + <STM32_PINMUX('B', 12, ANALOG)>; /* UART5_RX */ + }; + }; + + uart7_ux_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */ + bias-pull-up; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ + bias-pull-up; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS/DE */ + }; + }; + + uart7_ux_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */ + <STM32_PINMUX('E', 9, AF7)>; /* USART7_RTS/DE */ + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */ + bias-disable; + }; + }; + + uart7_ux_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* USART7_TX */ + <STM32_PINMUX('E', 9, AF7)>, /* USART7_RTS/DE */ + <STM32_PINMUX('E', 7, ANALOG)>; /* USART7_RX */ + }; + }; +}; + +&pinctrl_z { + + i2c4_ux_pins_a: i2c4-ux-0 { + pins { + pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_ux_pins_sleep_a: i2c4-1 { + pins { + pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ + }; + }; + + spi1_ux_pins_a: spi1-ux-0 { + pins1 { + pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; + + spi1_ux_sleep_pins_a: spi1-ux-sleep-0 { + pins { + pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */ + <STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */ + <STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */ + }; + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_ux_pins_a &qspi_bk1_ux_pins_a>; + pinctrl-1 = <&qspi_clk_ux_sleep_pins_a &qspi_bk1_ux_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <133000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_ux_b4_pins_a>; + pinctrl-1 = <&sdmmc1_ux_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_ux_b4_sleep_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + no-1-8-v; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_ux_b4_pins_a &sdmmc2_ux_d47_pins_a>; + pinctrl-1 = <&sdmmc2_ux_b4_od_pins_a &sdmmc2_ux_d47_pins_a>; + pinctrl-2 = <&sdmmc2_ux_b4_sleep_pins_a &sdmmc2_ux_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_ux_pins_a>; + pinctrl-1 = <&spi1_ux_sleep_pins_a>; + status = "okay"; + cs-gpios = <&gpioi 8 0>, <&gpioi 11 0>, <&gpioz 3 0>; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm1_ux_pins_a>; + pinctrl-1 = <&pwm1_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + + timer@0 { + status = "okay"; + }; +}; + +&timers4 { + dmas = <&dmamux1 31 0x400 0x5>; + dma-names = "ch3"; + status = "okay"; + + pwm4_4: pwm { + pinctrl-0 = <&pwm4_ux_pins_a>; + pinctrl-1 = <&pwm4_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm5_4: pwm { + pinctrl-0 = <&pwm5_ux_pins_a>; + pinctrl-1 = <&pwm5_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + + timer@4 { + status = "okay"; + }; +}; + +&timers17 { + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm17_4: pwm { + pinctrl-0 = <&pwm17_ux_pins_a>; + pinctrl-1 = <&pwm17_ux_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + + timer@16 { + status = "okay"; + }; +}; + +&uart4 { + /delete-property/dmas; + /delete-property/dma-names; + pinctrl-names = "default", "sleep", "idle", "no_console_suspend"; + pinctrl-0 = <&uart4_ux_pins_a>; + pinctrl-1 = <&uart4_ux_sleep_pins_a>; + pinctrl-2 = <&uart4_ux_idle_pins_a>; + pinctrl-3 = <&uart4_ux_pins_a>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart5_ux_pins_a>; + pinctrl-1 = <&uart5_ux_sleep_pins_a>; + pinctrl-2 = <&uart5_ux_idle_pins_a>; + status = "okay"; +}; + +&uart7 { + /delete-property/dmas; + /delete-property/dma-names; + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_ux_pins_a>; + pinctrl-1 = <&uart7_ux_sleep_pins_a>; + pinctrl-2 = <&uart7_ux_idle_pins_a>; + status = "okay"; +}; + +&usart1 { + /*Muxing happens in uboot*/ + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + vbus-supply = <&usb_otg_vbus>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,tune-hs-dc-level = <2>; + st,enable-fs-rftime-tuning; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <15>; + st,trim-hs-impedance = <1>; + st,tune-squelch-level = <3>; + st,tune-hs-rx-offset = <2>; + st,no-lsfs-sc; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index 343a4613dfca..aceeff6c38ba 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -435,7 +435,7 @@ #address-cells = <1>; #size-cells = <0>; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; }; diff --git a/arch/arm/boot/dts/ti/davinci/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts index 1f5cd35f8b74..38a191fb0414 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -60,7 +60,7 @@ sync-edge = <0>; sync-ctrl = <1>; raster-order = <0>; - fifo-th = <0>; + fifo-th = <1>; }; display-timings { diff --git a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts index 4df10379ff22..173401c58d53 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts @@ -412,14 +412,14 @@ status = "okay"; /* Don't pull down battery voltage adc io channel */ - batt_volt_en { + batt-volt-en-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; }; /* Don't impede Bluetooth clock signal */ - bt_clock_en { + bt-clock-en-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; @@ -433,19 +433,19 @@ * anything, but they are present in the source code from LEGO. */ - bt_pic_en { + bt-pic-en-hog { gpio-hog; gpios = <51 GPIO_ACTIVE_HIGH>; output-low; }; - bt_pic_rst { + bt-pic-rst-hog { gpio-hog; gpios = <78 GPIO_ACTIVE_HIGH>; output-high; }; - bt_pic_cts { + bt-pic-cts-hog { gpio-hog; gpios = <87 GPIO_ACTIVE_HIGH>; input; diff --git a/arch/arm/boot/dts/ti/omap/am335x-evm.dts b/arch/arm/boot/dts/ti/omap/am335x-evm.dts index 61bf8bcd4c4e..20222f82f21b 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-evm.dts @@ -388,7 +388,7 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; - + wakeup-source; status = "okay"; }; diff --git a/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi index e27837093e43..70e33cdd519a 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-evm-processor-common.dtsi @@ -205,7 +205,7 @@ /* T2_GPIO_2 low to route GPIO_61 to on-board devices */ &twl_gpio { - en_on_board_gpio_61 { + en-on-board-gpio-61-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/ti/omap/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts index 4bde3342bb95..c50ca572d1b9 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-n900.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-n900.dts @@ -816,8 +816,6 @@ reg = <0x0c>; VANA-supply = <&vaux4>; - - #io-channel-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi index 92cd4c99dae7..817474ee2d13 100644 --- a/arch/arm/boot/dts/ti/omap/omap3.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3.dtsi @@ -862,14 +862,14 @@ #size-cells = <1>; ranges; - usbhsohci: ohci@48064400 { + usbhsohci: usb@48064400 { compatible = "ti,ohci-omap3"; reg = <0x48064400 0x400>; interrupts = <76>; remote-wakeup-connected; }; - usbhsehci: ehci@48064800 { + usbhsehci: usb@48064800 { compatible = "ti,ehci-omap"; reg = <0x48064800 0x400>; interrupts = <77>; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi index 3fcef3080eae..4ee53dfb71b4 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -302,14 +302,14 @@ "refclk_60m_ext_p1", "refclk_60m_ext_p2"; - usbhsohci: ohci@800 { + usbhsohci: usb@800 { compatible = "ti,ohci-omap3"; reg = <0x800 0x400>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; remote-wakeup-connected; }; - usbhsehci: ehci@c00 { + usbhsehci: usb@c00 { compatible = "ti,ehci-omap"; reg = <0xc00 0x400>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; @@ -1414,7 +1414,7 @@ uart3: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1765,7 +1765,7 @@ uart1: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1794,7 +1794,7 @@ uart2: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1823,7 +1823,7 @@ uart4: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts index 8fd076e5d1b0..4b8bfd0188ad 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-a4.dts @@ -7,6 +7,11 @@ #include "omap443x.dtsi" #include "omap4-panda-common.dtsi" +/ { + model = "TI OMAP4 PandaBoard (A4)"; + compatible = "ti,omap4-panda-a4", "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +}; + /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ &dss_hdmi_pins { pinctrl-single,pins = < diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi index 97706d6296a6..05c871d31d7b 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-common.dtsi @@ -130,6 +130,12 @@ clock-frequency = <19200000>; }; + wl12xx_pwrseq: wl12xx-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&twl 0>; + clock-names = "ext_clock"; + }; + /* regulator for wl12xx on sdio5 */ wl12xx_vmmc: wl12xx_vmmc { pinctrl-names = "default"; @@ -361,10 +367,8 @@ */ wl12xx_gpio: wl12xx-gpio-pins { pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */ + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 - WLAN_EN */ OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ - OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */ >; }; @@ -387,6 +391,22 @@ OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */ >; }; + + bt_pins: bt-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ + OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ + >; + }; + + uart2_pins: uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; }; &omap4_pmx_wkup { @@ -408,6 +428,7 @@ reg = <0x48>; /* IRQ# = 7 */ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ + #clock-cells = <1>; system-power-controller; }; @@ -488,6 +509,7 @@ non-removable; bus-width = <4>; cap-power-off-card; + mmc-pwrseq = <&wl12xx_pwrseq>; #address-cells = <1>; #size-cells = <0>; @@ -523,8 +545,19 @@ }; &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART2_RX>; + + bluetooth { + compatible = "ti,wl1271-st"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ + clocks = <&twl 0>; + clock-names = "ext_clock"; + }; }; &uart3 { diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts index fe7b156d10ed..a933fe560834 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts @@ -49,22 +49,6 @@ OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; - - bt_pins: bt-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ - OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ - >; - }; - - uart2_pins: uart2-pins { - pinctrl-single,pins = < - OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ - OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; }; &led_wkgpio_pins { @@ -96,19 +80,3 @@ &gpio1_target { ti,no-reset-on-init; }; - -&wl12xx_gpio { - pinctrl-single,pins = < - OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ - OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ - >; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins &bt_pins>; - bluetooth: tiwi { - compatible = "ti,wl1271-st"; - enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ - }; -}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi index 3b505fe415ed..9f6100c7c34d 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -331,14 +331,14 @@ "refclk_60m_ext_p1", "refclk_60m_ext_p2"; - usbhsohci: ohci@800 { + usbhsohci: usb@800 { compatible = "ti,ohci-omap3"; reg = <0x800 0x400>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; remote-wakeup-connected; }; - usbhsehci: ehci@c00 { + usbhsehci: usb@c00 { compatible = "ti,ehci-omap"; reg = <0xc00 0x400>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/vt8500/Makefile b/arch/arm/boot/dts/vt8500/Makefile index 255f4403af91..6fd29c41f366 100644 --- a/arch/arm/boot/dts/vt8500/Makefile +++ b/arch/arm/boot/dts/vt8500/Makefile @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_VT8500) += \ wm8505-ref.dtb \ wm8650-mid.dtb \ wm8750-apc8750.dtb \ - wm8850-w70v2.dtb + wm8850-w70v2.dtb \ + wm8950-apc-rock.dtb diff --git a/arch/arm/boot/dts/vt8500/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi index f23cb5ee11ae..d1dd37220d41 100644 --- a/arch/arm/boot/dts/vt8500/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500/vt8500.dtsi @@ -55,6 +55,11 @@ #gpio-cells = <2>; }; + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; + pmc@d8130000 { compatible = "via,vt8500-pmc"; reg = <0xd8130000 0x1000>; @@ -106,10 +111,10 @@ timer@d8130100 { compatible = "via,vt8500-timer"; reg = <0xd8130100 0x28>; - interrupts = <36>; + interrupts = <36>, <37>, <38>, <39>; }; - ehci@d8007900 { + usb@d8007900 { compatible = "via,vt8500-ehci"; reg = <0xd8007900 0x200>; interrupts = <43>; diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi index d9e1280372c5..2b1819f0c541 100644 --- a/arch/arm/boot/dts/vt8500/wm8505.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi @@ -66,6 +66,11 @@ #gpio-cells = <2>; }; + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; + pmc@d8130000 { compatible = "via,vt8500-pmc"; reg = <0xd8130000 0x1000>; @@ -204,10 +209,10 @@ timer@d8130100 { compatible = "via,vt8500-timer"; reg = <0xd8130100 0x28>; - interrupts = <36>; + interrupts = <36>, <37>, <38>, <39>; }; - ehci@d8007100 { + usb@d8007100 { compatible = "via,vt8500-ehci"; reg = <0xd8007100 0x200>; interrupts = <1>; diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi index 35d12d77efc0..042eec78c085 100644 --- a/arch/arm/boot/dts/vt8500/wm8650.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi @@ -62,6 +62,11 @@ #gpio-cells = <2>; }; + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; + pmc@d8130000 { compatible = "via,vt8500-pmc"; reg = <0xd8130000 0x1000>; @@ -176,10 +181,10 @@ timer@d8130100 { compatible = "via,vt8500-timer"; reg = <0xd8130100 0x28>; - interrupts = <36>; + interrupts = <36>, <37>, <38>, <39>; }; - ehci@d8007900 { + usb@d8007900 { compatible = "via,vt8500-ehci"; reg = <0xd8007900 0x200>; interrupts = <43>; diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi index b292f85d4e69..56342aa1d993 100644 --- a/arch/arm/boot/dts/vt8500/wm8750.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi @@ -68,6 +68,11 @@ #gpio-cells = <2>; }; + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; + pmc@d8130000 { compatible = "via,vt8500-pmc"; reg = <0xd8130000 0x1000>; @@ -248,10 +253,10 @@ timer@d8130100 { compatible = "via,vt8500-timer"; reg = <0xd8130100 0x28>; - interrupts = <36>; + interrupts = <36>, <37>, <38>, <39>; }; - ehci@d8007900 { + usb@d8007900 { compatible = "via,vt8500-ehci"; reg = <0xd8007900 0x200>; interrupts = <26>; diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi index c61717ebb4f1..03e72f28d31b 100644 --- a/arch/arm/boot/dts/vt8500/wm8850.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -65,6 +65,11 @@ #gpio-cells = <2>; }; + chipid@d8120000 { + compatible = "via,vt8500-scc-id"; + reg = <0xd8120000 0x4>; + }; + pmc@d8130000 { compatible = "via,vt8500-pmc"; reg = <0xd8130000 0x1000>; @@ -235,10 +240,10 @@ timer@d8130100 { compatible = "via,vt8500-timer"; reg = <0xd8130100 0x28>; - interrupts = <36>; + interrupts = <36>, <37>, <38>, <39>; }; - ehci@d8007900 { + usb@d8007900 { compatible = "via,vt8500-ehci"; reg = <0xd8007900 0x200>; interrupts = <26>; diff --git a/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts b/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts new file mode 100644 index 000000000000..58b3c8deb4f2 --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8950-apc-rock.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 Alexey Charkov <alchark@gmail.com> + */ + +/dts-v1/; +/include/ "wm8950.dtsi" + +/ { + model = "VIA APC Rock"; + compatible = "via,apc-rock", "wm,wm8950"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vt8500/wm8950.dtsi b/arch/arm/boot/dts/vt8500/wm8950.dtsi new file mode 100644 index 000000000000..31fba05d3c3e --- /dev/null +++ b/arch/arm/boot/dts/vt8500/wm8950.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 Alexey Charkov <alchark@gmail.com> + */ + +/* No differences have been discovered vs. WM8850, but chip markings differ */ +/include/ "wm8850.dtsi" + +/ { + compatible = "wm,wm8950"; +}; diff --git a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi index a7db3f3009f2..153b8d93cbee 100644 --- a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi @@ -8,6 +8,13 @@ #size-cells = <1>; compatible = "xlnx,zynq-7000"; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x3000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -34,7 +41,7 @@ }; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; @@ -93,6 +100,7 @@ }; amba: axi { + bootph-all; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -190,6 +198,17 @@ reg = <0xf8006000 0x1000>; }; + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; @@ -277,13 +296,18 @@ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + }; + nor0: flash@1,0 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <1 0 0x2000000>; }; }; @@ -308,12 +332,14 @@ }; slcr: slcr@f8000000 { + bootph-all; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + bootph-all; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0>; @@ -398,6 +424,7 @@ }; scutimer: timer@f8f00600 { + bootph-all; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/boot/dts/xilinx/zynq-cc108.dts b/arch/arm/boot/dts/xilinx/zynq-cc108.dts index 8b9ab9bba23b..f5525c048426 100644 --- a/arch/arm/boot/dts/xilinx/zynq-cc108.dts +++ b/arch/arm/boot/dts/xilinx/zynq-cc108.dts @@ -18,6 +18,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart0; + spi0 = &qspi; }; chosen { @@ -48,7 +49,44 @@ ethernet_phy: ethernet-phy@1 { reg = <1>; - device_type = "ethernet-phy"; + }; +}; + +&qspi { + status = "okay"; + num-cs = <1>; + flash@0 { /* 16 MB */ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot-bs"; + reg = <0x0 0x400000>; /* 4MB */ + }; + partition@400000 { + label = "qspi-linux"; + reg = <0x400000 0x400000>; /* 4MB */ + }; + partition@800000 { + label = "qspi-rootfs"; + reg = <0x800000 0x400000>; /* 4MB */ + }; + partition@c00000 { + label = "qspi-devicetree"; + reg = <0xc00000 0x100000>; /* 1MB */ + }; + partition@d00000 { + label = "qspi-scratch"; + reg = <0xd00000 0x200000>; /* 2MB */ + }; + partition@f00000 { + label = "qspi-uboot-env"; + reg = <0xf00000 0x100000>; /* 1MB */ + }; }; }; @@ -59,6 +97,7 @@ }; &uart0 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts index 53fa6dbfd8fd..14f644156a6f 100644 --- a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts +++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts @@ -51,6 +51,8 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-microzed.dts b/arch/arm/boot/dts/xilinx/zynq-microzed.dts index 6ed84fb15902..68b867e8369e 100644 --- a/arch/arm/boot/dts/xilinx/zynq-microzed.dts +++ b/arch/arm/boot/dts/xilinx/zynq-microzed.dts @@ -11,8 +11,9 @@ compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { - ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory@0 { @@ -35,6 +36,11 @@ ps-clk-frequency = <33333333>; }; +&qspi { + bootph-all; + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -46,10 +52,12 @@ }; &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-parallella.dts b/arch/arm/boot/dts/xilinx/zynq-parallella.dts index 54592aeb92b9..366af4fcf8d9 100644 --- a/arch/arm/boot/dts/xilinx/zynq-parallella.dts +++ b/arch/arm/boot/dts/xilinx/zynq-parallella.dts @@ -46,7 +46,6 @@ compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22"; reg = <0>; - device_type = "ethernet-phy"; marvell,reg-init = <0x3 0x10 0xff00 0x1e>, <0x3 0x11 0xfff0 0xa>; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts index 6efdbca9d3ef..6955637c5b1a 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc702.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts @@ -15,7 +15,10 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; + nvmem0 = &eeprom; + rtc0 = &rtc; }; memory@0 { @@ -63,19 +66,6 @@ }; }; -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffc0000 0x10000>; - ocm-sram@0 { - reg = <0x0 0x10000>; - }; - }; -}; - &can0 { status = "okay"; pinctrl-names = "default"; @@ -95,7 +85,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -152,7 +141,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@54 { + eeprom: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; @@ -174,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -210,7 +199,7 @@ conf { groups = "can0_9_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -233,7 +222,7 @@ conf { groups = "ethernet0_0_grp"; slew-rate = <0>; - io-standard = <4>; + power-source = <4>; }; conf-rx { @@ -256,7 +245,7 @@ conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; }; @@ -274,7 +263,7 @@ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-pull-up { @@ -298,11 +287,11 @@ groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; @@ -311,7 +300,7 @@ conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -324,7 +313,7 @@ conf { groups = "sdio0_2_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; @@ -338,7 +327,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; mux-wp { @@ -351,7 +340,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -364,7 +353,7 @@ conf { groups = "uart1_10_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -387,7 +376,7 @@ conf { groups = "usb0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -403,13 +392,53 @@ }; }; +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts index 77943c16d33f..3b803c698473 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc706.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc706.dts @@ -14,7 +14,10 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; + nvmem0 = &eeprom; + rtc0 = &rtc; }; memory@0 { @@ -46,7 +49,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -100,7 +102,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@54 { + eeprom: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; @@ -122,7 +124,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -150,7 +152,7 @@ conf { groups = "ethernet0_0_grp"; slew-rate = <0>; - io-standard = <4>; + power-source = <4>; }; conf-rx { @@ -173,7 +175,7 @@ conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; }; @@ -187,7 +189,7 @@ conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-pull-up { @@ -211,7 +213,7 @@ groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -224,7 +226,7 @@ conf { groups = "sdio0_2_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; @@ -238,7 +240,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; mux-wp { @@ -251,7 +253,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -264,7 +266,7 @@ conf { groups = "uart1_10_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -287,7 +289,7 @@ conf { groups = "usb0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -303,13 +305,54 @@ }; }; +&qspi { + bootph-all; + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts index 0dd352289a45..5fe799c3c7cf 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm010.dts @@ -15,6 +15,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; spi1 = &spi1; }; @@ -45,7 +46,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -57,7 +57,43 @@ compatible = "atmel,24c02"; reg = <0x52>; }; +}; +&qspi { + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; }; &sdhci0 { @@ -85,6 +121,7 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts index 56732e8f6ca1..f9a086fe66d3 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm011.dts @@ -47,6 +47,36 @@ }; }; +&nfc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + nand@0 { + reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nand-fsbl-uboot"; + reg = <0x0 0x1000000>; + }; + partition@1000000 { + label = "nand-linux"; + reg = <0x1000000 0x2000000>; + }; + partition@3000000 { + label = "nand-rootfs"; + reg = <0x3000000 0x200000>; + }; + }; + }; +}; + +&smcc { + status = "okay"; +}; + &spi0 { status = "okay"; num-cs = <4>; @@ -54,6 +84,7 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts index d2359b789eb8..24520e7d3965 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm012.dts @@ -53,6 +53,40 @@ }; }; +&nor0 { + status = "okay"; + bank-width = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "nor-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "nor-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; +}; + +&smcc { + status = "okay"; +}; + &spi1 { status = "okay"; num-cs = <4>; @@ -60,5 +94,6 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts index 38d96adc870c..103e87ea7253 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc770-xm013.dts @@ -15,6 +15,7 @@ ethernet0 = &gem1; i2c0 = &i2c1; serial0 = &uart0; + spi0 = &qspi; spi1 = &spi0; }; @@ -40,7 +41,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -58,6 +58,44 @@ }; }; +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &spi0 { status = "okay"; num-cs = <4>; @@ -73,5 +111,6 @@ }; &uart0 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zed.dts b/arch/arm/boot/dts/xilinx/zynq-zed.dts index 6a5a93aa6552..52ba569b2b9f 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zed.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zed.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; }; @@ -43,15 +44,55 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; + }; +}; + +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi index 33b02e05ce82..defef9c8da13 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-zturn-common.dtsi @@ -63,6 +63,11 @@ ps-clk-frequency = <33333333>; }; +&qspi { + bootph-all; + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -73,14 +78,17 @@ }; &sdhci0 { + bootph-all; status = "okay"; }; &uart0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts index 7b87e10d3953..56b917eec783 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zybo-z7.dts @@ -10,6 +10,8 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory@0 { @@ -49,15 +51,21 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; +&qspi { + bootph-all; + status = "okay"; +}; + &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zybo.dts b/arch/arm/boot/dts/xilinx/zynq-zybo.dts index 755f6f109d5a..fbc7d1b12e94 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zybo.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zybo.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; }; @@ -44,15 +45,21 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; +&qspi { + bootph-all; + status = "okay"; +}; + &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; |