diff options
Diffstat (limited to 'arch/arm/mach-imx')
214 files changed, 4482 insertions, 33471 deletions
diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c deleted file mode 100644 index 134377352966..000000000000 --- a/arch/arm/mach-imx/3ds_debugboard.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/smsc911x.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include "hardware.h" - -/* LAN9217 ethernet base address */ -#define LAN9217_BASE_ADDR(n) (n + 0x0) -/* External UART */ -#define UARTA_BASE_ADDR(n) (n + 0x8000) -#define UARTB_BASE_ADDR(n) (n + 0x10000) - -#define BOARD_IO_ADDR(n) (n + 0x20000) -/* LED switchs */ -#define LED_SWITCH_REG 0x00 -/* buttons */ -#define SWITCH_BUTTONS_REG 0x08 -/* status, interrupt */ -#define INTR_STATUS_REG 0x10 -#define INTR_MASK_REG 0x38 -#define INTR_RESET_REG 0x20 -/* magic word for debug CPLD */ -#define MAGIC_NUMBER1_REG 0x40 -#define MAGIC_NUMBER2_REG 0x48 -/* CPLD code version */ -#define CPLD_CODE_VER_REG 0x50 -/* magic word for debug CPLD */ -#define MAGIC_NUMBER3_REG 0x58 -/* module reset register*/ -#define MODULE_RESET_REG 0x60 -/* CPU ID and Personality ID */ -#define MCU_BOARD_ID_REG 0x68 - -#define MXC_MAX_EXP_IO_LINES 16 - -/* interrupts like external uart , external ethernet etc*/ -#define EXPIO_INT_ENET 0 -#define EXPIO_INT_XUART_A 1 -#define EXPIO_INT_XUART_B 2 -#define EXPIO_INT_BUTTON_A 3 -#define EXPIO_INT_BUTTON_B 4 - -static void __iomem *brd_io; -static struct irq_domain *domain; - -static struct resource smsc911x_resources[] = { - { - .flags = IORESOURCE_MEM, - } , { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc_lan9217_device = { - .name = "smsc911x", - .id = -1, - .dev = { - .platform_data = &smsc911x_config, - }, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, -}; - -static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) -{ - u32 imr_val; - u32 int_valid; - u32 expio_irq; - - /* irq = gpio irq number */ - desc->irq_data.chip->irq_mask(&desc->irq_data); - - imr_val = __raw_readw(brd_io + INTR_MASK_REG); - int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val; - - expio_irq = 0; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(irq_find_mapping(domain, expio_irq)); - } - - desc->irq_data.chip->irq_ack(&desc->irq_data); - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * Irq is an expio virtual irq number - */ -static void expio_mask_irq(struct irq_data *d) -{ - u16 reg; - u32 expio = d->hwirq; - - reg = __raw_readw(brd_io + INTR_MASK_REG); - reg |= (1 << expio); - __raw_writew(reg, brd_io + INTR_MASK_REG); -} - -static void expio_ack_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - - __raw_writew(1 << expio, brd_io + INTR_RESET_REG); - __raw_writew(0, brd_io + INTR_RESET_REG); - expio_mask_irq(d); -} - -static void expio_unmask_irq(struct irq_data *d) -{ - u16 reg; - u32 expio = d->hwirq; - - reg = __raw_readw(brd_io + INTR_MASK_REG); - reg &= ~(1 << expio); - __raw_writew(reg, brd_io + INTR_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .irq_ack = expio_ack_irq, - .irq_mask = expio_mask_irq, - .irq_unmask = expio_unmask_irq, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -int __init mxc_expio_init(u32 base, u32 intr_gpio) -{ - u32 p_irq = gpio_to_irq(intr_gpio); - int irq_base; - int i; - - brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); - if (brd_io == NULL) - return -ENOMEM; - - if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || - (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || - (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { - pr_info("3-Stack Debug board not detected\n"); - iounmap(brd_io); - brd_io = NULL; - return -ENODEV; - } - - pr_info("3-Stack Debug board detected, rev = 0x%04X\n", - readw(brd_io + CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - gpio_request(intr_gpio, "expio_pirq"); - gpio_direction_input(intr_gpio); - - /* disable the interrupt and clear the status */ - __raw_writew(0, brd_io + INTR_MASK_REG); - __raw_writew(0xFFFF, brd_io + INTR_RESET_REG); - __raw_writew(0, brd_io + INTR_RESET_REG); - __raw_writew(0x1F, brd_io + INTR_MASK_REG); - - irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); - WARN_ON(irq_base < 0); - - domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { - irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); - irq_set_chained_handler(p_irq, mxc_expio_irq_handler); - - /* Register Lan device on the debugboard */ - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); - smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; - smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET); - smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET); - platform_device_register(&smsc_lan9217_device); - - return 0; -} diff --git a/arch/arm/mach-imx/3ds_debugboard.h b/arch/arm/mach-imx/3ds_debugboard.h deleted file mode 100644 index 9fd6cb3f8fad..000000000000 --- a/arch/arm/mach-imx/3ds_debugboard.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __ASM_ARCH_MXC_3DS_DB_H__ -#define __ASM_ARCH_MXC_3DS_DB_H__ - -extern int __init mxc_expio_init(u32 base, u32 intr_gpio); - -#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f54656091a9d..6ea1bd55acf8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,31 +1,19 @@ -config ARCH_MXC - bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 - select ARCH_REQUIRE_GPIOLIB - select ARM_PATCH_PHYS_VIRT - select AUTO_ZRELADDR if !ZBOOT_ROM - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select GENERIC_ALLOCATOR - select GENERIC_CLOCKEVENTS +# SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_MXC + bool "Freescale i.MX family" + depends on ((ARCH_MULTI_V4T || ARCH_MULTI_V5) && CPU_LITTLE_ENDIAN) || \ + ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M + select CLKSRC_IMX_GPT select GENERIC_IRQ_CHIP - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - select USE_OF + select GPIOLIB + select PINCTRL + select PM_OPP if PM + select SOC_BUS + select SRAM help Support for Freescale MXC/iMX-based family of processors -menu "Freescale i.MX support" - depends on ARCH_MXC - -config MXC_IRQ_PRIOR - bool "Use IRQ priority" - help - Select this if you want to use prioritized IRQ handling. - This feature prevents higher priority ISR to be interrupted - by lower priority IRQ even IRQF_DISABLED flag is not set. - This may be useful in embedded applications, where are strong - requirements for timing. - Say N here, unless you have a specialized requirement. +if ARCH_MXC config MXC_TZIC bool @@ -33,37 +21,12 @@ config MXC_TZIC config MXC_AVIC bool -config MXC_DEBUG_BOARD - bool "Enable MXC debug board(for 3-stack)" - help - The debug board is an integral part of the MXC 3-stack(PDK) - platforms, it can be attached or removed from the peripheral - board. On debug board, several debug devices(ethernet, UART, - buttons, LEDs and JTAG) are implemented. Between the MCU and - these devices, a CPLD is added as a bridge which performs - data/address de-multiplexing and decode, signal level shift, - interrupt control and various board functions. - -config HAVE_EPIT - bool - -config MXC_USE_EPIT - bool "Use EPIT instead of GPT" - depends on HAVE_EPIT - help - Use EPIT as the system timer on systems that have it. Normally you - don't have a reason to do so as the EPIT has the same features and - uses the same clocks as the GPT. Anyway, on some systems the GPT - may be in use for other purposes. - -config ARCH_HAS_RNGA - bool - config HAVE_IMX_ANATOP bool config HAVE_IMX_GPC bool + select PM_GENERIC_DOMAINS if PM config HAVE_IMX_MMDC bool @@ -72,781 +35,219 @@ config HAVE_IMX_SRC def_bool y if SMP select ARCH_HAS_RESET_CONTROLLER -config IMX_HAVE_IOMUX_V1 - bool +if ARCH_MULTI_V6 -config ARCH_MXC_IOMUX_V3 - bool +comment "ARM1136 platforms" -config ARCH_MX1 - bool +config SOC_IMX31 + bool "i.MX31 support" + select CPU_V6 + select MXC_AVIC + help + This enables support for Freescale i.MX31 processor -config ARCH_MX25 - bool +config SOC_IMX35 + bool "i.MX35 support" + select MXC_AVIC + help + This enables support for Freescale i.MX35 processor -config MACH_MX27 - bool +endif + +if ARCH_MULTI_V4T config SOC_IMX1 - bool - select ARCH_MX1 - select COMMON_CLK + bool "i.MX1 support" select CPU_ARM920T - select IMX_HAVE_IOMUX_V1 select MXC_AVIC + help + This enables support for Freescale i.MX1 processor -config SOC_IMX21 - bool - select COMMON_CLK - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 - select MXC_AVIC +endif + +if ARCH_MULTI_V5 config SOC_IMX25 - bool - select ARCH_MX25 - select ARCH_MXC_IOMUX_V3 - select COMMON_CLK + bool "i.MX25 support" select CPU_ARM926T select MXC_AVIC + help + This enables support for Freescale i.MX25 processor config SOC_IMX27 - bool - select ARCH_HAS_CPUFREQ - select ARCH_HAS_OPP - select COMMON_CLK + bool "i.MX27 support" select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 - select MACH_MX27 select MXC_AVIC + help + This enables support for Freescale i.MX27 processor -config SOC_IMX31 - bool - select COMMON_CLK - select CPU_V6 - select IMX_HAVE_PLATFORM_MXC_RNGA - select MXC_AVIC - select SMP_ON_UP if SMP +endif -config SOC_IMX35 - bool - select ARCH_MXC_IOMUX_V3 - select COMMON_CLK - select CPU_V6K - select HAVE_EPIT - select MXC_AVIC - select SMP_ON_UP if SMP +if ARCH_MULTI_V7 + +comment "Cortex-A platforms" config SOC_IMX5 bool - select ARCH_HAS_CPUFREQ - select ARCH_HAS_OPP - select ARCH_MXC_IOMUX_V3 - select COMMON_CLK - select CPU_V7 + select HAVE_IMX_SRC select MXC_TZIC -config SOC_IMX51 - bool - select HAVE_IMX_SRC - select PINCTRL - select PINCTRL_IMX51 +config SOC_IMX50 + bool "i.MX50 support" select SOC_IMX5 -if ARCH_MULTI_V4T - -comment "MX1 platforms:" -config MACH_MXLADS - bool - -config ARCH_MX1ADS - bool "MX1ADS platform" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select MACH_MXLADS - select SOC_IMX1 - help - Say Y here if you are using Motorola MX1ADS/MXLADS boards - -config MACH_SCB9328 - bool "Synertronixx scb9328" - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX1 - help - Say Y here if you are using a Synertronixx scb9328 board - -config MACH_APF9328 - bool "APF9328" - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX1 - help - Say Yes here if you are using the Armadeus APF9328 development board - -endif - -if ARCH_MULTI_V5 - -comment "MX21 platforms:" - -config MACH_MX21ADS - bool "MX21ADS platform" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select SOC_IMX21 - help - Include support for MX21ADS platform. This includes specific - configurations for the board and its peripherals. - -comment "MX25 platforms:" - -config MACH_MX25_3DS - bool "Support MX25PDK (3DS) Platform" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select SOC_IMX25 - -config MACH_EUKREA_CPUIMX25SD - bool "Support Eukrea CPUIMX25 Platform" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMXDI_RTC - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX25 - -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX25SD - default MACH_EUKREA_MBIMXSD25_BASEBOARD - -config MACH_EUKREA_MBIMXSD25_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -config MACH_IMX25_DT - bool "Support i.MX25 platforms from device tree" - select SOC_IMX25 - help - Include support for Freescale i.MX25 based platforms - using the device tree for discovery - -comment "MX27 platforms:" - -config MACH_MX27ADS - bool "MX27ADS platform" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select SOC_IMX27 help - Include support for MX27ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCM038 - bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select IMX_HAVE_PLATFORM_SPI_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX27 - help - Include support for phyCORE-i.MX27 (aka pcm038) platform. This - includes specific configurations for the module and its peripherals. + This enables support for Freescale i.MX50 processor. -choice - prompt "Baseboard" - depends on MACH_PCM038 - default MACH_PCM970_BASEBOARD - -config MACH_PCM970_BASEBOARD - bool "PHYTEC PCM970 development board" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_MXC_MMC +config SOC_IMX51 + bool "i.MX51 support" + select SOC_IMX5 help - This adds board specific devices that can be found on Phytec's - PCM970 evaluation board. + This enables support for Freescale i.MX51 processor -endchoice +config SOC_IMX53 + bool "i.MX53 support" + select SOC_IMX5 -config MACH_CPUIMX27 - bool "Eukrea CPUIMX27 module" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX27 help - Include support for Eukrea CPUIMX27 platform. This includes - specific configurations for the module and its peripherals. + This enables support for Freescale i.MX53 processor. -config MACH_EUKREA_CPUIMX27_USESDHC2 - bool "CPUIMX27 integrates SDHC2 module" - depends on MACH_CPUIMX27 - select IMX_HAVE_PLATFORM_MXC_MMC - help - This adds support for the internal SDHC2 used on CPUIMX27 - for wifi or eMMC. +config SOC_IMX6 + bool + select ARM_CPU_SUSPEND if (PM || CPU_IDLE) + select ARM_GIC + select HAVE_IMX_ANATOP + select HAVE_IMX_GPC + select HAVE_IMX_MMDC + select HAVE_IMX_SRC + select MFD_SYSCON + select PL310_ERRATA_769419 if CACHE_L2X0 -config MACH_EUKREA_CPUIMX27_USEUART4 - bool "CPUIMX27 integrates UART4 module" - depends on MACH_CPUIMX27 - help - This adds support for the internal UART4 used on CPUIMX27 - for bluetooth. +config SOC_IMX6Q + bool "i.MX6 Quad/DualLite support" + select ARM_ERRATA_764369 if SMP + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select HAVE_ARM_SCU if SMP + select HAVE_ARM_TWD + select SOC_IMX6 -choice - prompt "Baseboard" - depends on MACH_CPUIMX27 - default MACH_EUKREA_MBIMX27_BASEBOARD - -config MACH_EUKREA_MBIMX27_BASEBOARD - bool "Eukrea MBIMX27 development board" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER help - This adds board specific devices that can be found on Eukrea's - MBIMX27 evaluation board. - -endchoice + This enables support for Freescale i.MX6 Quad processor. -config MACH_MX27_3DS - bool "MX27PDK platform" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MX2_CAMERA - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX27 - help - Include support for MX27PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_IMX27_VISSTRIM_M10 - bool "Vista Silicon i.MX27 Visstrim_m10" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MX2_CAMERA - select IMX_HAVE_PLATFORM_MX2_EMMA - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select LEDS_GPIO_REGISTER - select SOC_IMX27 - help - Include support for Visstrim_m10 platform and its different variants. - This includes specific configurations for the board and its - peripherals. - -config MACH_IMX27LITE - bool "LogicPD MX27 LITEKIT platform" - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX27 - help - Include support for MX27 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCA100 - bool "Phytec phyCARD-s (pca100)" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select IMX_HAVE_PLATFORM_SPI_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX27 - help - Include support for phyCARD-s (aka pca100) platform. This - includes specific configurations for the module and its peripherals. - -config MACH_MXT_TD60 - bool "Maxtrack i-MXT TD60" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select SOC_IMX27 - help - Include support for i-MXT (aka td60) platform. This - includes specific configurations for the module and its peripherals. - -config MACH_IMX27IPCAM - bool "IMX27 IPCAM platform" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX27 - help - Include support for IMX27 IPCAM platform. This includes specific - configurations for the board and its peripherals. +config SOC_IMX6SL + bool "i.MX6 SoloLite support" + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select SOC_IMX6 -config MACH_IMX27_DT - bool "Support i.MX27 platforms from device tree" - select SOC_IMX27 help - Include support for Freescale i.MX27 based platforms - using the device tree for discovery - -endif - -if ARCH_MULTI_V6 + This enables support for Freescale i.MX6 SoloLite processor. -comment "MX31 platforms:" +config SOC_IMX6SLL + bool "i.MX6 SoloLiteLite support" + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select SOC_IMX6 -config MACH_MX31ADS - bool "Support MX31ADS platforms" - default y - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for MX31ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31ADS_WM1133_EV1 - bool "Support Wolfson Microelectronics 1133-EV1 module" - depends on MACH_MX31ADS - depends on MFD_WM8350_I2C - depends on REGULATOR_WM8350 = y - help - Include support for the Wolfson Microelectronics 1133-EV1 PMU - and audio module for the MX31ADS platform. - -config MACH_MX31LILLY - bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for mx31 based LILLY1131 modules. This includes - specific configurations for the board and its peripherals. - -config MACH_MX31LITE - bool "Support MX31 LITEKIT (LogicPD)" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_RTC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 help - Include support for MX31 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCM037 - bool "Support Phytec pcm037 (i.MX31) platforms" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for Phytec pcm037 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_PCM037_EET - bool "Support pcm037 EET board extensions" - depends on MACH_PCM037 - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_SPI_IMX - help - Add support for PCM037 EET baseboard extensions. If you are using the - OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel - command-line parameter. - -config MACH_MX31_3DS - bool "Support MX31PDK (3DS)" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for MX31PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. + This enables support for Freescale i.MX6 SoloLiteLite processor. -config MACH_MX31_3DS_MXC_NAND_USE_BBT - bool "Make the MXC NAND driver use the in flash Bad Block Table" - depends on MACH_MX31_3DS - depends on MTD_NAND_MXC - help - Enable this if you want that the MXC NAND driver uses the in flash - Bad Block Table to know what blocks are bad instead of scanning the - entire flash looking for bad block markers. - -config MACH_MX31MOBOARD - bool "Support mx31moboard platforms (EPFL Mobots group)" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for mx31moboard platform. This includes specific - configurations for the board and its peripherals. - -config MACH_QONG - bool "Support Dave/DENX QongEVB-LITE platform" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for Dave/DENX QongEVB-LITE platform. This includes - specific configurations for the board and its peripherals. - -config MACH_ARMADILLO5X0 - bool "Support Atmark Armadillo-500 Development Base Board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for Atmark Armadillo-500 platform. This includes - specific configurations for the board and its peripherals. +config SOC_IMX6SX + bool "i.MX6 SoloX support" + select ARM_ERRATA_754322 + select ARM_ERRATA_775420 + select SOC_IMX6 -config MACH_KZM_ARM11_01 - bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 help - Include support for KZM-ARM11-01. This includes specific - configurations for the board and its peripherals. - -config MACH_BUG - bool "Support Buglabs BUGBase platform" - default y - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for BUGBase 1.3 platform. This includes specific - configurations for the board and its peripherals. + This enables support for Freescale i.MX6 SoloX processor. -config MACH_IMX31_DT - bool "Support i.MX31 platforms from device tree" - select SOC_IMX31 - help - Include support for Freescale i.MX31 based platforms - using the device tree for discovery. - -comment "MX35 platforms:" - -config MACH_PCM043 - bool "Support Phytec pcm043 (i.MX35) platforms" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX35 - help - Include support for Phytec pcm043 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_MX35_3DS - bool "Support MX35PDK platform" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_RTC - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_DEBUG_BOARD - select SOC_IMX35 - help - Include support for MX35PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_EUKREA_CPUIMX35SD - bool "Support Eukrea CPUIMX35 Platform" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX35 - help - Include support for Eukrea CPUIMX35 platform. This includes - specific configurations for the board and its peripherals. +config SOC_IMX6UL + bool "i.MX6 UltraLite support" + select SOC_IMX6 + select ARM_ERRATA_814220 -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX35SD - default MACH_EUKREA_MBIMXSD35_BASEBOARD - -config MACH_EUKREA_MBIMXSD35_BASEBOARD - bool "Eukrea MBIMXSD development board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. + This enables support for Freescale i.MX6 UltraLite processor. -endchoice - -config MACH_VPR200 - bool "Support VPR200 platform" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select SOC_IMX35 +config SOC_LS1021A + bool "Freescale LS1021A support" + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select ZONE_DMA if ARM_LPAE help - Include support for VPR200 platform. This includes specific - configurations for the board and its peripherals. + This enables support for Freescale LS1021A processor. endif -if ARCH_MULTI_V7 - -comment "i.MX51 machines:" +if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M -config MACH_IMX51_DT - bool "Support i.MX51 platforms from device tree" - select SOC_IMX51 - help - Include support for Freescale i.MX51 based platforms - using the device tree for discovery - -config MACH_MX51_BABBAGE - bool "Support MX51 BABBAGE platforms" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select IMX_HAVE_PLATFORM_SPI_IMX - select SOC_IMX51 - help - Include support for MX51 Babbage platform, also known as MX51EVK in - u-boot. This includes specific configurations for the board and its - peripherals. - -config MACH_EUKREA_CPUIMX51SD - bool "Support Eukrea CPUIMX51SD module" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - select SOC_IMX51 - help - Include support for Eukrea CPUIMX51SD platform. This includes - specific configurations for the module and its peripherals. +comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" -choice - prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX51SD - default MACH_EUKREA_MBIMXSD51_BASEBOARD - -config MACH_EUKREA_MBIMXSD51_BASEBOARD - prompt "Eukrea MBIMXSD development board" +config SOC_IMX7D_CA7 bool - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select LEDS_GPIO_REGISTER - help - This adds board specific devices that can be found on Eukrea's - MBIMXSD evaluation board. - -endchoice - -comment "Device tree only" - -config SOC_IMX53 - bool "i.MX53 support" - select HAVE_IMX_SRC - select IMX_HAVE_PLATFORM_IMX2_WDT - select PINCTRL - select PINCTRL_IMX53 - select SOC_IMX5 - - help - This enables support for Freescale i.MX53 processor. - -config SOC_IMX6Q - bool "i.MX6 Quad/DualLite support" - select ARCH_HAS_CPUFREQ - select ARCH_HAS_OPP - select ARM_CPU_SUSPEND if PM - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP - select ARM_ERRATA_775420 select ARM_GIC - select COMMON_CLK - select CPU_V7 - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_ARCH_TIMER select HAVE_IMX_ANATOP - select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC - select HAVE_SMP - select MFD_SYSCON - select PINCTRL - select PINCTRL_IMX6Q - select PL310_ERRATA_588369 if CACHE_PL310 - select PL310_ERRATA_727915 if CACHE_PL310 - select PL310_ERRATA_769419 if CACHE_PL310 - select PM_OPP if PM + select IMX_GPCV2 +config SOC_IMX7D_CM4 + bool + select ARMV7M_SYSTICK + +config SOC_IMX7D + bool "i.MX7 Dual support" + select SOC_IMX7D_CA7 if ARCH_MULTI_V7 + select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M + select ARM_ERRATA_814220 if ARCH_MULTI_V7 help - This enables support for Freescale i.MX6 Quad processor. + This enables support for Freescale i.MX7 Dual processor. -config SOC_IMX6SL - bool "i.MX6 SoloLite support" - select ARM_ERRATA_754322 - select ARM_ERRATA_775420 - select ARM_GIC - select CPU_V7 - select HAVE_IMX_ANATOP - select HAVE_IMX_GPC - select HAVE_IMX_MMDC - select HAVE_IMX_SRC - select MFD_SYSCON - select PINCTRL - select PINCTRL_IMX6SL - select PL310_ERRATA_588369 if CACHE_PL310 - select PL310_ERRATA_727915 if CACHE_PL310 - select PL310_ERRATA_769419 if CACHE_PL310 +config SOC_IMX7ULP + bool "i.MX7ULP support" + select CLKSRC_IMX_TPM + select SOC_IMX7D_CA7 if ARCH_MULTI_V7 + select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M + help + This enables support for Freescale i.MX7 Ultra Low Power processor. +config SOC_IMXRT + bool "i.MXRT support" + depends on ARM_SINGLE_ARMV7M + select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M help - This enables support for Freescale i.MX6 SoloLite processor. + This enables support for Freescale i.MXRT Crossover processor. config SOC_VF610 bool "Vybrid Family VF610 support" - select CPU_V7 - select ARM_GIC - select CLKSRC_OF - select PINCTRL - select PINCTRL_VF610 - select VF_PIT_TIMER - select PL310_ERRATA_588369 if CACHE_PL310 - select PL310_ERRATA_727915 if CACHE_PL310 - select PL310_ERRATA_769419 if CACHE_PL310 + select ARM_GIC if ARCH_MULTI_V7 help - This enable support for Freescale Vybrid VF610 processor. + This enables support for Freescale Vybrid VF610 processor. -endif +choice + prompt "Clocksource for scheduler clock" + depends on SOC_VF610 + default VF_USE_ARM_GLOBAL_TIMER + + config VF_USE_ARM_GLOBAL_TIMER + bool "Use ARM Global Timer" + depends on ARCH_MULTI_V7 + select ARM_GLOBAL_TIMER + select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK + help + Use the ARM Global Timer as clocksource + + config VF_USE_PIT_TIMER + bool "Use PIT timer" + select NXP_PIT_TIMER + help + Use SoC Periodic Interrupt Timer (PIT) as clocksource + +endchoice -source "arch/arm/mach-imx/devices/Kconfig" +endif -endmenu +endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e20f22d58fd8..5c650bf40e02 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,116 +1,67 @@ -obj-y := time.o cpu.o system.o irq-common.o +# SPDX-License-Identifier: GPL-2.0 +obj-y := cpu.o system.o irq-common.o -obj-$(CONFIG_SOC_IMX1) += clk-imx1.o mm-imx1.o -obj-$(CONFIG_SOC_IMX21) += clk-imx21.o mm-imx21.o +obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o -obj-$(CONFIG_SOC_IMX25) += clk-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o +obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o -obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o -obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o - -obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o -obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o +obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o +obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o imx5-pm-$(CONFIG_PM) += pm-imx5.o -obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) - -obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ - clk-pfd.o clk-busy.o clk.o - -obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o -obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o +obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y) obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o -obj-$(CONFIG_MXC_USE_EPIT) += epit.o -obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o - ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o +obj-$(CONFIG_SOC_IMX6SLL) += cpuidle-imx6sx.o +obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o +obj-$(CONFIG_SOC_IMX7ULP) += cpuidle-imx7ulp.o endif -ifdef CONFIG_SND_IMX_SOC +ifdef CONFIG_SND_SOC_IMX_PCM_FIQ obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o endif -# Support for CMOS sensor interface -obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o - -# i.MX1 based machines -obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o -obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o - -# i.MX21 based machines -obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o - -# i.MX25 based machines -obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX25SD) += mach-eukrea_cpuimx25.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o -obj-$(CONFIG_MACH_IMX25_DT) += imx25-dt.o - -# i.MX27 based machines -obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o -obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o -obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o -obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o -obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o -obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o -obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o -obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o -obj-$(CONFIG_MACH_PCA100) += mach-pca100.o -obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o -obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o -obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o - -# i.MX31 based machines -obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o -obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o -obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o -obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ - mx31moboard-marxbot.o mx31moboard-smartbot.o -obj-$(CONFIG_MACH_QONG) += mach-qong.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o -obj-$(CONFIG_MACH_BUG) += mach-bug.o -obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o - -# i.MX35 based machines -obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o -obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o - obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o -AFLAGS_headsmp.o :=-Wa,-march=armv7-a +ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),) obj-$(CONFIG_SMP) += headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o -obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o - -ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o endif +obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o +obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o +obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o +obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o +obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o +obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o +obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o + +ifeq ($(CONFIG_SUSPEND),y) +obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o +obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o +endif +ifeq ($(CONFIG_ARM_CPU_SUSPEND),y) +obj-$(CONFIG_SOC_IMX6) += resume-imx6.o +endif +obj-$(CONFIG_SOC_IMX6) += pm-imx6.o -# i.MX5 based machines -obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o -obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o - -obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o +obj-$(CONFIG_SOC_IMX1) += mach-imx1.o +obj-$(CONFIG_SOC_IMX50) += mach-imx50.o +obj-$(CONFIG_SOC_IMX51) += mach-imx51.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o -obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o +obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o + +obj-$(CONFIG_SOC_VF610) += mach-vf610.o -obj-y += devices/ +obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 0cfa07dd9aa4..7bb47eb3fc07 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -1,12 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. */ #include <linux/err.h> @@ -16,6 +11,7 @@ #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include "common.h" +#include "hardware.h" #define REG_SET 0x4 #define REG_CLR 0x8 @@ -23,15 +19,18 @@ #define ANADIG_REG_2P5 0x130 #define ANADIG_REG_CORE 0x140 #define ANADIG_ANA_MISC0 0x150 -#define ANADIG_USB1_CHRG_DETECT 0x1b0 -#define ANADIG_USB2_CHRG_DETECT 0x210 #define ANADIG_DIGPROG 0x260 +#define ANADIG_DIGPROG_IMX6SL 0x280 +#define ANADIG_DIGPROG_IMX7D 0x800 + +#define SRC_SBMR2 0x1c #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 +#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000 -#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000 -#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000 +/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */ +#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000 static struct regmap *anatop; @@ -54,50 +53,111 @@ static void imx_anatop_enable_fet_odrive(bool enable) BM_ANADIG_REG_CORE_FET_ODRIVE); } +static inline void imx_anatop_enable_2p5_pulldown(bool enable) +{ + regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), + BM_ANADIG_REG_2P5_ENABLE_PULLDOWN); +} + +static inline void imx_anatop_disconnect_high_snvs(bool enable) +{ + regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), + BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS); +} + void imx_anatop_pre_suspend(void) { - imx_anatop_enable_weak2p5(true); + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx_anatop_enable_2p5_pulldown(true); + else + imx_anatop_enable_weak2p5(true); + imx_anatop_enable_fet_odrive(true); + + if (cpu_is_imx6sl()) + imx_anatop_disconnect_high_snvs(true); } void imx_anatop_post_resume(void) { + if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) + imx_anatop_enable_2p5_pulldown(false); + else + imx_anatop_enable_weak2p5(false); + imx_anatop_enable_fet_odrive(false); - imx_anatop_enable_weak2p5(false); -} -void imx_anatop_usb_chrg_detect_disable(void) -{ - regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, - BM_ANADIG_USB_CHRG_DETECT_EN_B - | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); - regmap_write(anatop, ANADIG_USB2_CHRG_DETECT, - BM_ANADIG_USB_CHRG_DETECT_EN_B | - BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B); + if (cpu_is_imx6sl()) + imx_anatop_disconnect_high_snvs(false); } -u32 imx_anatop_get_digprog(void) +void __init imx_init_revision_from_anatop(void) { - struct device_node *np; + struct device_node *np, *src_np; void __iomem *anatop_base; - static u32 digprog; - - if (digprog) - return digprog; + unsigned int revision; + u32 digprog; + u16 offset = ANADIG_DIGPROG; + u8 major_part, minor_part; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); WARN_ON(!anatop_base); - digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG); + if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) + offset = ANADIG_DIGPROG_IMX6SL; + if (of_device_is_compatible(np, "fsl,imx7d-anatop")) + offset = ANADIG_DIGPROG_IMX7D; + digprog = readl_relaxed(anatop_base + offset); + iounmap(anatop_base); + + /* + * On i.MX7D digprog value match linux version format, so + * it needn't map again and we can use register value directly. + */ + if (of_device_is_compatible(np, "fsl,imx7d-anatop")) { + revision = digprog & 0xff; + } else { + /* + * MAJOR: [15:8], the major silicon revison; + * MINOR: [7: 0], the minor silicon revison; + * + * please refer to the i.MX RM for the detailed + * silicon revison bit define. + * format the major part and minor part to match the + * linux kernel soc version format. + */ + major_part = (digprog >> 8) & 0xf; + minor_part = digprog & 0xf; + revision = ((major_part + 1) << 4) | minor_part; + + if ((digprog >> 16) == MXC_CPU_IMX6ULL) { + void __iomem *src_base; + u32 sbmr2; + + src_np = of_find_compatible_node(NULL, NULL, + "fsl,imx6ul-src"); + src_base = of_iomap(src_np, 0); + of_node_put(src_np); + WARN_ON(!src_base); + sbmr2 = readl_relaxed(src_base + SRC_SBMR2); + iounmap(src_base); + + /* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */ + if (sbmr2 & (1 << 6)) { + digprog &= ~(0xff << 16); + digprog |= (MXC_CPU_IMX6ULZ << 16); + } + } + } + of_node_put(np); - return digprog; + mxc_set_cpu_type(digprog >> 16 & 0xff); + imx_set_soc_revision(revision); } void __init imx_anatop_init(void) { anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); - if (IS_ERR(anatop)) { + if (IS_ERR(anatop)) pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); - return; - } } diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c index e163ec7a8441..3067c06b4b8e 100644 --- a/arch/arm/mach-imx/avic.c +++ b/arch/arm/mach-imx/avic.c @@ -1,27 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #include <linux/module.h> #include <linux/irq.h> #include <linux/irqdomain.h> +#include <linux/irqchip.h> #include <linux/io.h> #include <linux/of.h> +#include <linux/of_address.h> #include <asm/mach/irq.h> #include <asm/exception.h> @@ -51,49 +40,29 @@ #define AVIC_NUM_IRQS 64 +/* low power interrupt mask registers */ +#define MX25_CCM_LPIMR0 0x68 +#define MX25_CCM_LPIMR1 0x6C + static void __iomem *avic_base; +static void __iomem *mx25_ccm_base; static struct irq_domain *domain; -#ifdef CONFIG_MXC_IRQ_PRIOR -static int avic_irq_set_priority(unsigned char irq, unsigned char prio) -{ - struct irq_data *d = irq_get_irq_data(irq); - unsigned int temp; - unsigned int mask = 0x0F << irq % 8 * 4; - - irq = d->hwirq; - - if (irq >= AVIC_NUM_IRQS) - return -EINVAL; - - temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8)); - temp &= ~mask; - temp |= prio & mask; - - __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); - - return 0; -} -#endif - #ifdef CONFIG_FIQ -static int avic_set_irq_fiq(unsigned int irq, unsigned int type) +static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) { - struct irq_data *d = irq_get_irq_data(irq); unsigned int irqt; - irq = d->hwirq; - - if (irq >= AVIC_NUM_IRQS) + if (hwirq >= AVIC_NUM_IRQS) return -EINVAL; - if (irq < AVIC_NUM_IRQS / 2) { - irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); + if (hwirq < AVIC_NUM_IRQS / 2) { + irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); + imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); } else { - irq -= AVIC_NUM_IRQS / 2; - irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq); - __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); + hwirq -= AVIC_NUM_IRQS / 2; + irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); + imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); } return 0; @@ -102,9 +71,6 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type) static struct mxc_extra_irq avic_extra_irq = { -#ifdef CONFIG_MXC_IRQ_PRIOR - .set_priority = avic_irq_set_priority, -#endif #ifdef CONFIG_FIQ .set_irq_fiq = avic_set_irq_fiq, #endif @@ -119,8 +85,20 @@ static void avic_irq_suspend(struct irq_data *d) struct irq_chip_type *ct = gc->chip_types; int idx = d->hwirq >> 5; - avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask); - __raw_writel(gc->wake_active, avic_base + ct->regs.mask); + avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); + imx_writel(gc->wake_active, avic_base + ct->regs.mask); + + if (mx25_ccm_base) { + u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? + MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; + /* + * The interrupts which are still enabled will be used as wakeup + * sources. Allow those interrupts in low-power mode. + * The LPIMR registers use 0 to allow an interrupt, the AVIC + * registers use 1. + */ + imx_writel(~gc->wake_active, mx25_ccm_base + offs); + } } static void avic_irq_resume(struct irq_data *d) @@ -129,7 +107,14 @@ static void avic_irq_resume(struct irq_data *d) struct irq_chip_type *ct = gc->chip_types; int idx = d->hwirq >> 5; - __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); + imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); + + if (mx25_ccm_base) { + u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ? + MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1; + + imx_writel(0xffffffff, mx25_ccm_base + offs); + } } #else @@ -160,16 +145,16 @@ static __init void avic_init_gc(int idx, unsigned int irq_start) irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); } -asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) +static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) { u32 nivector; do { - nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16; + nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; if (nivector == 0xffff) break; - handle_IRQ(irq_find_mapping(domain, nivector), regs); + generic_handle_domain_irq(domain, nivector); } while (1); } @@ -178,7 +163,7 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ -void __init mxc_init_irq(void __iomem *irqbase) +static void __init mxc_init_irq(void __iomem *irqbase) { struct device_node *np; int irq_base; @@ -186,26 +171,38 @@ void __init mxc_init_irq(void __iomem *irqbase) avic_base = irqbase; + np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); + mx25_ccm_base = of_iomap(np, 0); + + if (mx25_ccm_base) { + /* + * By default, we mask all interrupts. We set the actual mask + * before we go into low-power mode. + */ + imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0); + imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1); + } + /* put the AVIC into the reset value with * all interrupts disabled */ - __raw_writel(0, avic_base + AVIC_INTCNTL); - __raw_writel(0x1f, avic_base + AVIC_NIMASK); + imx_writel(0, avic_base + AVIC_INTCNTL); + imx_writel(0x1f, avic_base + AVIC_NIMASK); /* disable all interrupts */ - __raw_writel(0, avic_base + AVIC_INTENABLEH); - __raw_writel(0, avic_base + AVIC_INTENABLEL); + imx_writel(0, avic_base + AVIC_INTENABLEH); + imx_writel(0, avic_base + AVIC_INTENABLEL); /* all IRQ no FIQ */ - __raw_writel(0, avic_base + AVIC_INTTYPEH); - __raw_writel(0, avic_base + AVIC_INTTYPEL); + imx_writel(0, avic_base + AVIC_INTTYPEH); + imx_writel(0, avic_base + AVIC_INTTYPEL); irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id()); WARN_ON(irq_base < 0); np = of_find_compatible_node(NULL, NULL, "fsl,avic"); - domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0, - &irq_domain_simple_ops, NULL); + domain = irq_domain_create_legacy(of_fwnode_handle(np), AVIC_NUM_IRQS, irq_base, 0, + &irq_domain_simple_ops, NULL); WARN_ON(!domain); for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32) @@ -213,7 +210,9 @@ void __init mxc_init_irq(void __iomem *irqbase) /* Set default priority value (0) for all IRQ's */ for (i = 0; i < 8; i++) - __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); + imx_writel(0, avic_base + AVIC_NIPRIORITY(i)); + + set_handle_irq(avic_handle_irq); #ifdef CONFIG_FIQ /* Initialize FIQ */ @@ -222,3 +221,16 @@ void __init mxc_init_irq(void __iomem *irqbase) printk(KERN_INFO "MXC IRQ initialized\n"); } + +static int __init imx_avic_init(struct device_node *node, + struct device_node *parent) +{ + void __iomem *avic_base; + + avic_base = of_iomap(node, 0); + BUG_ON(!avic_base); + mxc_init_irq(avic_base); + return 0; +} + +IRQCHIP_DECLARE(imx_avic, "fsl,avic", imx_avic_init); diff --git a/arch/arm/mach-imx/board-mx31lilly.h b/arch/arm/mach-imx/board-mx31lilly.h deleted file mode 100644 index 0df71bfefbb1..000000000000 --- a/arch/arm/mach-imx/board-mx31lilly.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - * - * Based on code for mobots boards, - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ -#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ - -#ifndef __ASSEMBLY__ - -enum mx31lilly_boards { - MX31LILLY_NOBOARD = 0, - MX31LILLY_DB = 1, -}; - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - */ - -extern void mx31lilly_db_init(void); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */ diff --git a/arch/arm/mach-imx/board-mx31lite.h b/arch/arm/mach-imx/board-mx31lite.h deleted file mode 100644 index c1ad0ae807cc..000000000000 --- a/arch/arm/mach-imx/board-mx31lite.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - * - * Based on code for mobots boards, - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ -#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ - -#ifndef __ASSEMBLY__ - -enum mx31lite_boards { - MX31LITE_NOBOARD = 0, - MX31LITE_DB = 1, -}; - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - */ - -extern void mx31lite_db_init(void); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ diff --git a/arch/arm/mach-imx/board-mx31moboard.h b/arch/arm/mach-imx/board-mx31moboard.h deleted file mode 100644 index de14543891cf..000000000000 --- a/arch/arm/mach-imx/board-mx31moboard.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ -#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ - -#ifndef __ASSEMBLY__ - -enum mx31moboard_boards { - MX31NOBOARD = 0, - MX31DEVBOARD = 1, - MX31MARXBOT = 2, - MX31SMARTBOT = 3, - MX31EYEBOT = 4, -}; - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - */ - -extern void mx31moboard_devboard_init(void); -extern void mx31moboard_marxbot_init(void); -extern void mx31moboard_smartbot_init(int board); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */ diff --git a/arch/arm/mach-imx/board-pcm038.h b/arch/arm/mach-imx/board-pcm038.h deleted file mode 100644 index 6f371e35753d..000000000000 --- a/arch/arm/mach-imx/board-pcm038.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__ -#define __ASM_ARCH_MXC_BOARD_PCM038_H__ - -#ifndef __ASSEMBLY__ -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - * TODO: Add your own baseboard init function and call it from - * inside pcm038_init(). - * - * This example here is for the development board. Refer pcm970-baseboard.c - */ - -extern void pcm970_baseboard_init(void); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */ diff --git a/arch/arm/mach-imx/clk-busy.c b/arch/arm/mach-imx/clk-busy.c deleted file mode 100644 index 4bb1bc419b79..000000000000 --- a/arch/arm/mach-imx/clk-busy.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/jiffies.h> -#include <linux/err.h> -#include "clk.h" - -static int clk_busy_wait(void __iomem *reg, u8 shift) -{ - unsigned long timeout = jiffies + msecs_to_jiffies(10); - - while (readl_relaxed(reg) & (1 << shift)) - if (time_after(jiffies, timeout)) - return -ETIMEDOUT; - - return 0; -} - -struct clk_busy_divider { - struct clk_divider div; - const struct clk_ops *div_ops; - void __iomem *reg; - u8 shift; -}; - -static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw) -{ - struct clk_divider *div = container_of(hw, struct clk_divider, hw); - - return container_of(div, struct clk_busy_divider, div); -} - -static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_busy_divider *busy = to_clk_busy_divider(hw); - - return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); -} - -static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_busy_divider *busy = to_clk_busy_divider(hw); - - return busy->div_ops->round_rate(&busy->div.hw, rate, prate); -} - -static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_busy_divider *busy = to_clk_busy_divider(hw); - int ret; - - ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); - if (!ret) - ret = clk_busy_wait(busy->reg, busy->shift); - - return ret; -} - -static struct clk_ops clk_busy_divider_ops = { - .recalc_rate = clk_busy_divider_recalc_rate, - .round_rate = clk_busy_divider_round_rate, - .set_rate = clk_busy_divider_set_rate, -}; - -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, - void __iomem *reg, u8 shift, u8 width, - void __iomem *busy_reg, u8 busy_shift) -{ - struct clk_busy_divider *busy; - struct clk *clk; - struct clk_init_data init; - - busy = kzalloc(sizeof(*busy), GFP_KERNEL); - if (!busy) - return ERR_PTR(-ENOMEM); - - busy->reg = busy_reg; - busy->shift = busy_shift; - - busy->div.reg = reg; - busy->div.shift = shift; - busy->div.width = width; - busy->div.lock = &imx_ccm_lock; - busy->div_ops = &clk_divider_ops; - - init.name = name; - init.ops = &clk_busy_divider_ops; - init.flags = CLK_SET_RATE_PARENT; - init.parent_names = &parent_name; - init.num_parents = 1; - - busy->div.hw.init = &init; - - clk = clk_register(NULL, &busy->div.hw); - if (IS_ERR(clk)) - kfree(busy); - - return clk; -} - -struct clk_busy_mux { - struct clk_mux mux; - const struct clk_ops *mux_ops; - void __iomem *reg; - u8 shift; -}; - -static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw) -{ - struct clk_mux *mux = container_of(hw, struct clk_mux, hw); - - return container_of(mux, struct clk_busy_mux, mux); -} - -static u8 clk_busy_mux_get_parent(struct clk_hw *hw) -{ - struct clk_busy_mux *busy = to_clk_busy_mux(hw); - - return busy->mux_ops->get_parent(&busy->mux.hw); -} - -static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index) -{ - struct clk_busy_mux *busy = to_clk_busy_mux(hw); - int ret; - - ret = busy->mux_ops->set_parent(&busy->mux.hw, index); - if (!ret) - ret = clk_busy_wait(busy->reg, busy->shift); - - return ret; -} - -static struct clk_ops clk_busy_mux_ops = { - .get_parent = clk_busy_mux_get_parent, - .set_parent = clk_busy_mux_set_parent, -}; - -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, - u8 width, void __iomem *busy_reg, u8 busy_shift, - const char **parent_names, int num_parents) -{ - struct clk_busy_mux *busy; - struct clk *clk; - struct clk_init_data init; - - busy = kzalloc(sizeof(*busy), GFP_KERNEL); - if (!busy) - return ERR_PTR(-ENOMEM); - - busy->reg = busy_reg; - busy->shift = busy_shift; - - busy->mux.reg = reg; - busy->mux.shift = shift; - busy->mux.mask = BIT(width) - 1; - busy->mux.lock = &imx_ccm_lock; - busy->mux_ops = &clk_mux_ops; - - init.name = name; - init.ops = &clk_busy_mux_ops; - init.flags = 0; - init.parent_names = parent_names; - init.num_parents = num_parents; - - busy->mux.hw.init = &init; - - clk = clk_register(NULL, &busy->mux.hw); - if (IS_ERR(clk)) - kfree(busy); - - return clk; -} diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c deleted file mode 100644 index a63e415609a8..000000000000 --- a/arch/arm/mach-imx/clk-gate2.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com> - * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Gated clock implementation - */ - -#include <linux/clk-provider.h> -#include <linux/module.h> -#include <linux/slab.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/string.h> -#include "clk.h" - -/** - * DOC: basic gatable clock which can gate and ungate it's ouput - * - * Traits of this clock: - * prepare - clk_(un)prepare only ensures parent is (un)prepared - * enable - clk_enable and clk_disable are functional & control gating - * rate - inherits rate from parent. No clk_set_rate support - * parent - fixed parent. No clk_set_parent support - */ - -#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) - -static int clk_gate2_enable(struct clk_hw *hw) -{ - struct clk_gate *gate = to_clk_gate(hw); - u32 reg; - unsigned long flags = 0; - - if (gate->lock) - spin_lock_irqsave(gate->lock, flags); - - reg = readl(gate->reg); - reg |= 3 << gate->bit_idx; - writel(reg, gate->reg); - - if (gate->lock) - spin_unlock_irqrestore(gate->lock, flags); - - return 0; -} - -static void clk_gate2_disable(struct clk_hw *hw) -{ - struct clk_gate *gate = to_clk_gate(hw); - u32 reg; - unsigned long flags = 0; - - if (gate->lock) - spin_lock_irqsave(gate->lock, flags); - - reg = readl(gate->reg); - reg &= ~(3 << gate->bit_idx); - writel(reg, gate->reg); - - if (gate->lock) - spin_unlock_irqrestore(gate->lock, flags); -} - -static int clk_gate2_is_enabled(struct clk_hw *hw) -{ - u32 reg; - struct clk_gate *gate = to_clk_gate(hw); - - reg = readl(gate->reg); - - if (((reg >> gate->bit_idx) & 3) == 3) - return 1; - - return 0; -} - -static struct clk_ops clk_gate2_ops = { - .enable = clk_gate2_enable, - .disable = clk_gate2_disable, - .is_enabled = clk_gate2_is_enabled, -}; - -struct clk *clk_register_gate2(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - void __iomem *reg, u8 bit_idx, - u8 clk_gate2_flags, spinlock_t *lock) -{ - struct clk_gate *gate; - struct clk *clk; - struct clk_init_data init; - - gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); - if (!gate) - return ERR_PTR(-ENOMEM); - - /* struct clk_gate assignments */ - gate->reg = reg; - gate->bit_idx = bit_idx; - gate->flags = clk_gate2_flags; - gate->lock = lock; - - init.name = name; - init.ops = &clk_gate2_ops; - init.flags = flags; - init.parent_names = parent_name ? &parent_name : NULL; - init.num_parents = parent_name ? 1 : 0; - - gate->hw.init = &init; - - clk = clk_register(dev, &gate->hw); - if (IS_ERR(clk)) - kfree(gate); - - return clk; -} diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c deleted file mode 100644 index 15f9d223cf0b..000000000000 --- a/arch/arm/mach-imx/clk-imx1.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/err.h> - -#include "clk.h" -#include "common.h" -#include "hardware.h" - -/* CCM register addresses */ -#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off))) - -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_PCDR IO_ADDR_CCM(0x20) - -/* SCM register addresses */ -#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off))) - -#define SCM_GCCR IO_ADDR_SCM(0xc) - -static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; -static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem", - "fclk", }; -enum imx1_clks { - dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu, - fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate, - mma_gate, usbd_gate, clk_max -}; - -static struct clk *clk[clk_max]; - -int __init mx1_clocks_init(unsigned long fref) -{ - int i; - - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[clk32] = imx_clk_fixed("clk32", fref); - clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000); - clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); - clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); - clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, - ARRAY_SIZE(prem_sel_clks)); - clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); - clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); - clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); - clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1); - clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4); - clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3); - clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4); - clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4); - clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7); - clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, - ARRAY_SIZE(clko_sel_clks)); - clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4); - clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); - clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); - clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("imx1 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma"); - clk_register_clkdev(clk[hclk], "ipg", "imx1-dma"); - clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0"); - clk_register_clkdev(clk[mma_gate], "mma", NULL); - clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0"); - clk_register_clkdev(clk[per1], "per", "imx-gpt.0"); - clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[per1], "per", "imx1-uart.0"); - clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0"); - clk_register_clkdev(clk[per1], "per", "imx1-uart.1"); - clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1"); - clk_register_clkdev(clk[per1], "per", "imx1-uart.2"); - clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2"); - clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0"); - clk_register_clkdev(clk[per2], "per", "imx1-cspi.0"); - clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0"); - clk_register_clkdev(clk[per2], "per", "imx1-cspi.1"); - clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1"); - clk_register_clkdev(clk[per2], NULL, "imx-mmc.0"); - clk_register_clkdev(clk[per2], "per", "imx1-fb.0"); - clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0"); - clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0"); - clk_register_clkdev(clk[hclk], "mshc", NULL); - clk_register_clkdev(clk[per3], "ssi", NULL); - clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0"); - clk_register_clkdev(clk[clko], "clko", NULL); - - mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT); - - return 0; -} diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c deleted file mode 100644 index d7ed66091a2a..000000000000 --- a/arch/arm/mach-imx/clk-imx21.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/err.h> - -#include "clk.h" -#include "common.h" -#include "hardware.h" - -#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) - -/* Register offsets */ -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_MPCTL1 IO_ADDR_CCM(0x8) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_SPCTL1 IO_ADDR_CCM(0x10) -#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) -#define CCM_PCDR0 IO_ADDR_CCM(0x18) -#define CCM_PCDR1 IO_ADDR_CCM(0x1c) -#define CCM_PCCR0 IO_ADDR_CCM(0x20) -#define CCM_PCCR1 IO_ADDR_CCM(0x24) -#define CCM_CCSR IO_ADDR_CCM(0x28) -#define CCM_PMCTL IO_ADDR_CCM(0x2c) -#define CCM_PMCOUNT IO_ADDR_CCM(0x30) -#define CCM_WKGDCTL IO_ADDR_CCM(0x34) - -static const char *mpll_sel_clks[] = { "fpm", "ckih", }; -static const char *spll_sel_clks[] = { "fpm", "ckih", }; - -enum imx21_clks { - ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1, - per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate, - uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate, - pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate, - lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate, - per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate, - ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate, - emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate, - gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max -}; - -static struct clk *clk[clk_max]; - -/* - * must be called very early to get information about the - * available clock rate when the timer framework starts - */ -int __init mx21_clocks_init(unsigned long lref, unsigned long href) -{ - int i; - - clk[ckil] = imx_clk_fixed("ckil", lref); - clk[ckih] = imx_clk_fixed("ckih", href); - clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); - clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, - ARRAY_SIZE(mpll_sel_clks)); - clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, - ARRAY_SIZE(spll_sel_clks)); - clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); - clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0); - clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3); - clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); - clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); - clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6); - clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6); - clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6); - clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6); - clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); - clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); - clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); - clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); - clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); - clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); - clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); - clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); - clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); - clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); - clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); - clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); - clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); - clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); - clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); - clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); - clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); - clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3); - clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); - clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); - clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); - clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); - clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4); - clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); - clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); - clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); - clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); - clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); - clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); - clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25); - clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); - clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); - clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); - clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); - clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); - clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); - clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX21 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - clk_register_clkdev(clk[per1], "per1", NULL); - clk_register_clkdev(clk[per2], "per2", NULL); - clk_register_clkdev(clk[per3], "per3", NULL); - clk_register_clkdev(clk[per4], "per4", NULL); - clk_register_clkdev(clk[per1], "per", "imx21-uart.0"); - clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[per1], "per", "imx21-uart.1"); - clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[per1], "per", "imx21-uart.2"); - clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[per1], "per", "imx21-uart.3"); - clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[per1], "per", "imx-gpt.0"); - clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1"); - clk_register_clkdev(clk[per1], "per", "imx-gpt.1"); - clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2"); - clk_register_clkdev(clk[per1], "per", "imx-gpt.2"); - clk_register_clkdev(clk[pwm_ipg_gate], "pwm", "mxc_pwm.0"); - clk_register_clkdev(clk[per2], "per", "imx21-cspi.0"); - clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0"); - clk_register_clkdev(clk[per2], "per", "imx21-cspi.1"); - clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1"); - clk_register_clkdev(clk[per2], "per", "imx21-cspi.2"); - clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2"); - clk_register_clkdev(clk[per3], "per", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0"); - clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0"); - clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0"); - clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0"); - clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma"); - clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma"); - clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad"); - clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); - clk_register_clkdev(clk[brom_gate], "brom", NULL); - clk_register_clkdev(clk[emma_gate], "emma", NULL); - clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL); - clk_register_clkdev(clk[gpio_gate], "gpio", NULL); - clk_register_clkdev(clk[rtc_gate], "rtc", NULL); - clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL); - clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL); - clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL); - clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL); - clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL); - - mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1); - - return 0; -} diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c deleted file mode 100644 index 69858c78f40d..000000000000 --- a/arch/arm/mach-imx/clk-imx25.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (C) 2009 by Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/err.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include "clk.h" -#include "common.h" -#include "hardware.h" -#include "mx25.h" - -#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR) - -#define CCM_MPCTL 0x00 -#define CCM_UPCTL 0x04 -#define CCM_CCTL 0x08 -#define CCM_CGCR0 0x0C -#define CCM_CGCR1 0x10 -#define CCM_CGCR2 0x14 -#define CCM_PCDR0 0x18 -#define CCM_PCDR1 0x1C -#define CCM_PCDR2 0x20 -#define CCM_PCDR3 0x24 -#define CCM_RCSR 0x28 -#define CCM_CRDR 0x2C -#define CCM_DCVR0 0x30 -#define CCM_DCVR1 0x34 -#define CCM_DCVR2 0x38 -#define CCM_DCVR3 0x3c -#define CCM_LTR0 0x40 -#define CCM_LTR1 0x44 -#define CCM_LTR2 0x48 -#define CCM_LTR3 0x4c -#define CCM_MCR 0x64 - -#define ccm(x) (CRM_BASE + (x)) - -static struct clk_onecell_data clk_data; - -static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", }; -static const char *per_sel_clks[] = { "ahb", "upll", }; - -enum mx25_clks { - dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, - per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel, - per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel, - per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5, - per6, per7, per8, per9, per10, per11, per12, per13, per14, per15, - csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per, - gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per, - pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per, - uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb, - esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb, - reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg, - cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg, - reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9, - gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12, - iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg, - pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg, - sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg, - uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17, - wdt_ipg, clk_max -}; - -static struct clk *clk[clk_max]; - -static int __init __mx25_clocks_init(unsigned long osc_rate) -{ - int i; - - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[osc] = imx_clk_fixed("osc", osc_rate); - clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL)); - clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL)); - clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); - clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); - clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); - clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); - clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); - clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); - clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); - clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6); - clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6); - clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6); - clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6); - clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6); - clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6); - clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6); - clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6); - clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6); - clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6); - clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6); - clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6); - clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6); - clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6); - clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6); - clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6); - clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0); - clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1); - clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2); - clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3); - clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); - clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); - clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); - clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); - clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); - clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9); - clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10); - clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11); - clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12); - clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13); - clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14); - clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15); - clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); - /* CCM_CGCR0(17): reserved */ - clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); - clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); - clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); - clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); - clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22); - clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23); - clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24); - clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25); - clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26); - clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27); - clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28); - /* CCM_CGCR0(29-31): reserved */ - /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */ - clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); - clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); - clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); - clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5); - clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); - clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); - clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); - clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9); - clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10); - clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11); - /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */ - clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); - clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); - clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); - /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */ - /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */ - /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */ - clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19); - clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20); - clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21); - clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22); - /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */ - /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */ - /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */ - clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); - /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */ - /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */ - clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); - clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); - /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */ - clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); - clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0); - clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1); - clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2); - clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3); - /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */ - clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5); - clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6); - clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7); - clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8); - clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9); - clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10); - clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11); - clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12); - clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13); - clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14); - clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15); - clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16); - clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17); - clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18); - /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */ - clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX25 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - clk_prepare_enable(clk[emi_ahb]); - - /* Clock source for gpt must be derived from AHB */ - clk_set_parent(clk[per5_sel], clk[ahb]); - - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); - - return 0; -} - -int __init mx25_clocks_init(void) -{ - __mx25_clocks_init(24000000); - - /* i.mx25 has the i.mx21 type uart */ - clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0"); - /* i.mx25 has the i.mx35 type cspi */ - clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0"); - clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1"); - clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.0"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.1"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.2"); - clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3"); - clk_register_clkdev(clk[per10], "per", "mxc_pwm.3"); - clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad"); - clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc"); - clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0"); - clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0"); - clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0"); - clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0"); - clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); - clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); - clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); - clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1"); - clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1"); - clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1"); - clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0"); - clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0"); - clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0"); - clk_register_clkdev(clk[dummy], "audmux", NULL); - clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0"); - clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1"); - /* i.mx25 has the i.mx35 type sdma */ - clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma"); - clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); - clk_register_clkdev(clk[iim_ipg], "iim", NULL); - - mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); - - return 0; -} - -int __init mx25_clocks_init_dt(void) -{ - struct device_node *np; - void __iomem *base; - int irq; - unsigned long osc_rate = 24000000; - - /* retrieve the freqency of fixed clocks from device tree */ - for_each_compatible_node(np, NULL, "fixed-clock") { - u32 rate; - if (of_property_read_u32(np, "clock-frequency", &rate)) - continue; - - if (of_device_is_compatible(np, "fsl,imx-osc")) - osc_rate = rate; - } - - np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm"); - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - - __mx25_clocks_init(osc_rate); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - - mxc_timer_init(base, irq); - - return 0; -} diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c deleted file mode 100644 index c3cfa4116dc0..000000000000 --- a/arch/arm/mach-imx/clk-imx27.c +++ /dev/null @@ -1,316 +0,0 @@ -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/clkdev.h> -#include <linux/err.h> -#include <linux/clk-provider.h> -#include <linux/of.h> - -#include "clk.h" -#include "common.h" -#include "hardware.h" - -#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) - -/* Register offsets */ -#define CCM_CSCR IO_ADDR_CCM(0x0) -#define CCM_MPCTL0 IO_ADDR_CCM(0x4) -#define CCM_MPCTL1 IO_ADDR_CCM(0x8) -#define CCM_SPCTL0 IO_ADDR_CCM(0xc) -#define CCM_SPCTL1 IO_ADDR_CCM(0x10) -#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) -#define CCM_PCDR0 IO_ADDR_CCM(0x18) -#define CCM_PCDR1 IO_ADDR_CCM(0x1c) -#define CCM_PCCR0 IO_ADDR_CCM(0x20) -#define CCM_PCCR1 IO_ADDR_CCM(0x24) -#define CCM_CCSR IO_ADDR_CCM(0x28) -#define CCM_PMCTL IO_ADDR_CCM(0x2c) -#define CCM_PMCOUNT IO_ADDR_CCM(0x30) -#define CCM_WKGDCTL IO_ADDR_CCM(0x34) - -#define CCM_CSCR_UPDATE_DIS (1 << 31) -#define CCM_CSCR_SSI2 (1 << 23) -#define CCM_CSCR_SSI1 (1 << 22) -#define CCM_CSCR_VPU (1 << 21) -#define CCM_CSCR_MSHC (1 << 20) -#define CCM_CSCR_SPLLRES (1 << 19) -#define CCM_CSCR_MPLLRES (1 << 18) -#define CCM_CSCR_SP (1 << 17) -#define CCM_CSCR_MCU (1 << 16) -#define CCM_CSCR_OSC26MDIV (1 << 4) -#define CCM_CSCR_OSC26M (1 << 3) -#define CCM_CSCR_FPM (1 << 2) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN (1 << 0) - -/* i.MX27 TO 2+ */ -#define CCM_CSCR_ARM_SRC (1 << 15) - -#define CCM_SPCTL1_LF (1 << 15) -#define CCM_SPCTL1_BRMO (1 << 6) - -static const char *vpu_sel_clks[] = { "spll", "mpll_main2", }; -static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", }; -static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", }; -static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", }; -static const char *clko_sel_clks[] = { - "ckil", "fpm", "ckih", "ckih", - "ckih", "mpll", "spll", "cpu_div", - "ahb", "ipg", "per1_div", "per2_div", - "per3_div", "per4_div", "ssi1_div", "ssi2_div", - "nfc_div", "mshc_div", "vpu_div", "60m", - "32k", "usb_div", "dptc", -}; - -static const char *ssi_sel_clks[] = { "spll_gate", "mpll", }; - -enum mx27_clks { - dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, - per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel, - clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div, - clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate, - sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate, - rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate, - kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate, - gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate, - gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate, - emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate, - cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate, - vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate, - usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate, - vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate, - csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, - uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, - uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, - mpll_sel, spll_gate, clk_max -}; - -static struct clk *clk[clk_max]; -static struct clk_onecell_data clk_data; - -int __init mx27_clocks_init(unsigned long fref) -{ - int i; - struct device_node *np; - - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckih] = imx_clk_fixed("ckih", fref); - clk[ckil] = imx_clk_fixed("ckil", 32768); - clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); - clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3); - - clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, - mpll_osc_sel_clks, - ARRAY_SIZE(mpll_osc_sel_clks)); - clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, - ARRAY_SIZE(mpll_sel_clks)); - clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0); - clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0); - clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); - clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); - - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { - clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); - clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); - } else { - clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); - clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); - } - - clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); - clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); - clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); - clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); - clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); - clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); - clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); - clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); - clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); - clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); - if (mx27_revision() >= IMX_CHIP_REVISION_2_0) - clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); - else - clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); - clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); - clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); - clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); - clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); - clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); - clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); - clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); - clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); - clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); - clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); - clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); - clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); - clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); - clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); - clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); - clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); - clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); - clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); - clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); - clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); - clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); - clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); - clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); - clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); - clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); - clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); - clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); - clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); - clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); - clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); - clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); - clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); - clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); - clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); - clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); - clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); - clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); - clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); - clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); - clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); - clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); - clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); - clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); - clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); - clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); - clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); - clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); - clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); - clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); - clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); - clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); - clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); - clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); - clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); - clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); - clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); - clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); - clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); - clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); - clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); - clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); - clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); - clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX27 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); - if (np) { - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - } - - clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4"); - clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5"); - clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5"); - clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1"); - clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1"); - clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2"); - clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2"); - clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3"); - clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3"); - clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4"); - clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4"); - clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5"); - clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5"); - clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0"); - clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0"); - clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0"); - clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1"); - clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1"); - clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2"); - clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2"); - clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0"); - clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0"); - clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1"); - clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1"); - clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2"); - clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2"); - clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0"); - clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0"); - clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0"); - clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0"); - clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0"); - clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); - clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); - clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma"); - clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma"); - clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); - clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0"); - clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0"); - clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad"); - clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0"); - clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0"); - clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); - clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); - clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL); - clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL); - clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL); - clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL); - clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc"); - clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); - clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0"); - clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); - - mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); - - clk_prepare_enable(clk[emi_ahb_gate]); - - imx_print_silicon_rev("i.MX27", mx27_revision()); - - return 0; -} - -#ifdef CONFIG_OF -int __init mx27_clocks_init_dt(void) -{ - struct device_node *np; - u32 fref = 26000000; /* default */ - - for_each_compatible_node(np, NULL, "fixed-clock") { - if (!of_device_is_compatible(np, "fsl,imx-osc26m")) - continue; - - if (!of_property_read_u32(np, "clock-frequency", &fref)) - break; - } - - return mx27_clocks_init(fref); -} -#endif diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c deleted file mode 100644 index b5b65f3efaf1..000000000000 --- a/arch/arm/mach-imx/clk-imx31.c +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - */ - -#include <linux/module.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/of.h> - -#include "clk.h" -#include "common.h" -#include "crmregs-imx3.h" -#include "hardware.h" -#include "mx31.h" - -static const char *mcu_main_sel[] = { "spll", "mpll", }; -static const char *per_sel[] = { "per_div", "ipg", }; -static const char *csi_sel[] = { "upll", "spll", }; -static const char *fir_sel[] = { "mcu_main", "upll", "spll" }; - -enum mx31_clks { - dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, - per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, - fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate, - iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate, - uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate, - mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate, - sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, - uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate, - gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max -}; - -static struct clk *clk[clk_max]; -static struct clk_onecell_data clk_data; - -int __init mx31_clocks_init(unsigned long fref) -{ - void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); - int i; - struct device_node *np; - - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckih] = imx_clk_fixed("ckih", fref); - clk[ckil] = imx_clk_fixed("ckil", 32768); - clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); - clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL); - clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL); - clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); - clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); - clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); - clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); - clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); - clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); - clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); - clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); - clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); - clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); - clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); - clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); - clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); - clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); - clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); - clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); - clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); - clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); - clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); - clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); - clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); - clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); - clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); - clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); - clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); - clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); - clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); - clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); - clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); - clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); - clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); - clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); - clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); - clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); - clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); - clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); - clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); - clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); - clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); - clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); - clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); - clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); - clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); - clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); - clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); - clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); - clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); - clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); - clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); - clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); - clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); - clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); - clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("imx31 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); - - if (np) { - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - } - - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); - clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); - clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); - clk_register_clkdev(clk[pwm_gate], "pwm", NULL); - clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[rtc_gate], NULL, "imx21-rtc"); - clk_register_clkdev(clk[epit1_gate], "epit", NULL); - clk_register_clkdev(clk[epit2_gate], "epit", NULL); - clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); - clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); - clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); - clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); - /* i.mx31 has the i.mx21 type uart */ - clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); - clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); - clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); - clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[firi_gate], "firi", NULL); - clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); - clk_register_clkdev(clk[rtic_gate], "rtic", NULL); - clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); - clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); - clk_register_clkdev(clk[iim_gate], "iim", NULL); - - clk_set_parent(clk[csi], clk[upll]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[iim_gate]); - mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); - - mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); - - return 0; -} - -#ifdef CONFIG_OF -int __init mx31_clocks_init_dt(void) -{ - struct device_node *np; - u32 fref = 26000000; /* default */ - - for_each_compatible_node(np, NULL, "fixed-clock") { - if (!of_device_is_compatible(np, "fsl,imx-osc26m")) - continue; - - if (!of_property_read_u32(np, "clock-frequency", &fref)) - break; - } - - return mx31_clocks_init(fref); -} -#endif diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c deleted file mode 100644 index 2193c834f55c..000000000000 --- a/arch/arm/mach-imx/clk-imx35.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <linux/mm.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/of.h> -#include <linux/err.h> - -#include "crmregs-imx3.h" -#include "clk.h" -#include "common.h" -#include "hardware.h" - -struct arm_ahb_div { - unsigned char arm, ahb, sel; -}; - -static struct arm_ahb_div clk_consumer[] = { - { .arm = 1, .ahb = 4, .sel = 0}, - { .arm = 1, .ahb = 3, .sel = 1}, - { .arm = 2, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 1, .sel = 0}, - { .arm = 1, .ahb = 5, .sel = 0}, - { .arm = 1, .ahb = 8, .sel = 0}, - { .arm = 1, .ahb = 6, .sel = 1}, - { .arm = 2, .ahb = 4, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, - { .arm = 4, .ahb = 2, .sel = 0}, - { .arm = 0, .ahb = 0, .sel = 0}, -}; - -static char hsp_div_532[] = { 4, 8, 3, 0 }; -static char hsp_div_400[] = { 3, 6, 3, 0 }; - -static const char *std_sel[] = {"ppll", "arm"}; -static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; - -enum mx35_clks { - ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, - arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, - esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, - spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, - ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate, - audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate, - edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, - esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate, - gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate, - kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, - rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, - ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, - wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, - gpu2d_gate, clk_max -}; - -static struct clk *clk[clk_max]; - -int __init mx35_clocks_init(void) -{ - void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); - u32 pdr0, consumer_sel, hsp_sel; - struct arm_ahb_div *aad; - unsigned char *hsp_div; - u32 i; - - pdr0 = __raw_readl(base + MXC_CCM_PDR0); - consumer_sel = (pdr0 >> 16) & 0xf; - aad = &clk_consumer[consumer_sel]; - if (!aad->arm) { - pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); - /* - * We are basically stuck. Continue with a default entry and hope we - * get far enough to actually show the above message - */ - aad = &clk_consumer[0]; - } - - clk[ckih] = imx_clk_fixed("ckih", 24000000); - clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); - clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); - - clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); - - if (aad->sel) - clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); - else - clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); - - if (clk_get_rate(clk[arm]) > 400000000) - hsp_div = hsp_div_532; - else - hsp_div = hsp_div_400; - - hsp_sel = (pdr0 >> 20) & 0x3; - if (!hsp_div[hsp_sel]) { - pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); - hsp_sel = 0; - } - - clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); - - clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); - clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); - - clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); - clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); - clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); - - clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); - clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); - - clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); - clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); - clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); - clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); - - clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); - clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ - clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); - - clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); - clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); - clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); - clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); - clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); - - clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); - clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); - - clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); - - clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); - clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); - - clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); - clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); - clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); - clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); - clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); - clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); - clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); - clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); - clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); - clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); - clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); - clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); - clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); - clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); - clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); - clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); - - clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); - clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); - clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); - clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); - clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); - clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); - clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); - clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); - clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); - clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); - clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); - clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); - clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); - clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); - clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); - clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); - - clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); - clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); - clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); - clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); - clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); - clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); - clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); - clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); - clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); - clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); - clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); - clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); - clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); - clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); - clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); - - clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); - clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); - clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX35 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); - clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); - clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); - clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); - clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); - clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); - clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); - clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); - clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); - clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); - clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); - clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); - clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); - clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); - clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); - clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); - clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); - clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); - /* i.mx35 has the i.mx27 type fec */ - clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); - clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); - clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); - clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); - clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); - clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); - /* i.mx35 has the i.mx21 type uart */ - clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); - clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); - clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); - clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); - clk_register_clkdev(clk[admux_gate], "audmux", NULL); - - clk_prepare_enable(clk[spba_gate]); - clk_prepare_enable(clk[gpio1_gate]); - clk_prepare_enable(clk[gpio2_gate]); - clk_prepare_enable(clk[gpio3_gate]); - clk_prepare_enable(clk[iim_gate]); - clk_prepare_enable(clk[emi_gate]); - clk_prepare_enable(clk[max_gate]); - clk_prepare_enable(clk[iomuxc_gate]); - - /* - * SCC is needed to boot via mmc after a watchdog reset. The clock code - * before conversion to common clk also enabled UART1 (which isn't - * handled here and not needed for mmc) and IIM (which is enabled - * unconditionally above). - */ - clk_prepare_enable(clk[scc_gate]); - - imx_print_silicon_rev("i.MX35", mx35_revision()); - -#ifdef CONFIG_MXC_USE_EPIT - epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); -#else - mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); -#endif - - return 0; -} diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c deleted file mode 100644 index 9afac26fa1cc..000000000000 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ /dev/null @@ -1,580 +0,0 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <linux/mm.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/clkdev.h> -#include <linux/of.h> -#include <linux/err.h> - -#include "crm-regs-imx5.h" -#include "clk.h" -#include "common.h" -#include "hardware.h" - -/* Low-power Audio Playback Mode clock */ -static const char *lp_apm_sel[] = { "osc", }; - -/* This is used multiple times */ -static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", }; -static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", }; -static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", }; -static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", }; -static const char *per_root_sel[] = { "per_podf", "ipg", }; -static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; -static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", }; -static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", }; -static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", }; -static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", }; -static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", }; -static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; -static const char *emi_slow_sel[] = { "main_bus", "ahb", }; -static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; -static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; -static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; -static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; -static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; -static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; -static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; -static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; -static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; -static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", }; -static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; -static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; -static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" }; -static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", }; -static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", }; -static const char *mx53_cko1_sel[] = { - "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw", - "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy", - "di_pred", "dummy", "dummy", "ahb", - "ipg", "per_root", "ckil", "dummy",}; -static const char *mx53_cko2_sel[] = { - "dummy"/* dptc_core */, "dummy"/* dptc_perich */, - "dummy", "esdhc_a_podf", - "usboh3_podf", "dummy"/* wrck_clk_root */, - "ecspi_podf", "dummy"/* pll1_ref_clk */, - "esdhc_b_podf", "dummy"/* ddr_clk_root */, - "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */, - "vpu_sel", "ipu_sel", - "osc", "ckih1", - "dummy", "esdhc_c_sel", - "ssi1_root_podf", "ssi2_root_podf", - "dummy", "dummy", - "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */, - "dummy"/* tve_out */, "usb_phy_sel", - "tve_sel", "lp_apm", - "uart_root", "dummy"/* spdif0_clk_root */, - "dummy", "dummy", }; -static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", }; -static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", }; -static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", }; -static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", }; -static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", }; - - -enum imx5_clks { - dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, - uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s, - emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred, - usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, tve_di_unused, - tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate, - uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate, - gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate, - gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate, - esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate, - ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate, - ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s, - ipu_gate, nfc_gate, ipu_di1_gate, vpu_s, vpu_gate, - vpu_reference_gate, uart4_ipg_gate, uart4_per_gate, uart5_ipg_gate, - uart5_per_gate, tve_gate, tve_pred, esdhc1_per_gate, esdhc2_per_gate, - esdhc3_per_gate, esdhc4_per_gate, usb_phy_gate, hsi2c_gate, - mipi_hsc1_gate, mipi_hsc2_gate, mipi_esc_gate, mipi_hsp_gate, - ldb_di1_div_3_5, ldb_di1_div, ldb_di0_div_3_5, ldb_di0_div, - ldb_di1_gate, can2_serial_gate, can2_ipg_gate, i2c3_gate, lp_apm, - periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2, - tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf, - esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel, iim_gate, - usboh3_gate, emi_fast_gate, ipu_di0_gate,gpc_dvfs, pll1_sw, pll2_sw, - pll3_sw, ipu_di0_sel, ipu_di1_sel, tve_ext_sel, mx51_mipi, pll4_sw, - ldb_di1_sel, di_pll4_podf, ldb_di0_sel, ldb_di0_gate, usb_phy1_gate, - usb_phy2_gate, per_lp_apm, per_pred1, per_pred2, per_podf, per_root, - ssi_apm, ssi1_root_sel, ssi2_root_sel, ssi3_root_sel, ssi_ext1_sel, - ssi_ext2_sel, ssi_ext1_com_sel, ssi_ext2_com_sel, ssi1_root_pred, - ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred, - ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate, - ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, - epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, - can_sel, can1_serial_gate, can1_ipg_gate, - owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, - cko1_sel, cko1_podf, cko1, - cko2_sel, cko2_podf, cko2, - srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, - spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, - spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, - clk_max -}; - -static struct clk *clk[clk_max]; -static struct clk_onecell_data clk_data; - -static void __init mx5_clocks_common_init(unsigned long rate_ckil, - unsigned long rate_osc, unsigned long rate_ckih1, - unsigned long rate_ckih2) -{ - int i; - - of_clk_init(NULL); - - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil); - clk[osc] = imx_obtain_fixed_clock("osc", rate_osc); - clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1); - clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2); - - clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, - lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); - clk[periph_apm] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, - periph_apm_sel, ARRAY_SIZE(periph_apm_sel)); - clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, - main_bus_sel, ARRAY_SIZE(main_bus_sel)); - clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, - per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel)); - clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); - clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); - clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); - clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, - per_root_sel, ARRAY_SIZE(per_root_sel)); - clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); - clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); - clk[aips_tz1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); - clk[aips_tz2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); - clk[tmax1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); - clk[tmax2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); - clk[tmax3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); - clk[spba] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); - clk[ipg] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); - clk[axi_a] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); - clk[axi_b] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); - clk[uart_sel] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); - clk[uart_root] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); - - clk[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); - clk[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); - clk[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); - clk[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); - clk[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); - clk[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); - - clk[emi_sel] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, - emi_slow_sel, ARRAY_SIZE(emi_slow_sel)); - clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); - clk[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); - clk[ecspi_sel] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); - clk[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); - clk[usboh3_sel] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, - standard_pll_sel, ARRAY_SIZE(standard_pll_sel)); - clk[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); - clk[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); - clk[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); - clk[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); - clk[usb_phy_sel] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, - usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str)); - clk[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", MXC_CCM_CACRR, 0, 3); - clk[di_pred] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); - clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); - clk[uart1_ipg_gate] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); - clk[uart1_per_gate] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); - clk[uart2_ipg_gate] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); - clk[uart2_per_gate] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); - clk[uart3_ipg_gate] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); - clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); - clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); - clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); - clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); - clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); - clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); - clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); - clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); - clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); - clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); - clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); - clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); - clk[esdhc1_ipg_gate] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); - clk[esdhc2_ipg_gate] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); - clk[esdhc3_ipg_gate] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); - clk[esdhc4_ipg_gate] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); - clk[ssi1_ipg_gate] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); - clk[ssi2_ipg_gate] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); - clk[ssi3_ipg_gate] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); - clk[ecspi1_ipg_gate] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); - clk[ecspi1_per_gate] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); - clk[ecspi2_ipg_gate] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); - clk[ecspi2_per_gate] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); - clk[cspi_ipg_gate] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); - clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); - clk[emi_fast_gate] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); - clk[emi_slow_gate] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); - clk[ipu_s] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); - clk[ipu_gate] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); - clk[nfc_gate] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); - clk[ipu_di0_gate] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); - clk[ipu_di1_gate] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); - clk[gpu3d_s] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); - clk[gpu2d_s] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); - clk[gpu3d_gate] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); - clk[garb_gate] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); - clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); - clk[vpu_s] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); - clk[vpu_gate] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); - clk[vpu_reference_gate] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); - clk[uart4_ipg_gate] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); - clk[uart4_per_gate] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); - clk[uart5_ipg_gate] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); - clk[uart5_per_gate] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); - clk[gpc_dvfs] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); - - clk[ssi_apm] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); - clk[ssi1_root_sel] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi2_root_sel] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi3_root_sel] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); - clk[ssi_ext1_sel] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi_ext2_sel] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); - clk[ssi_ext1_com_sel] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); - clk[ssi_ext2_com_sel] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); - clk[ssi1_root_pred] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); - clk[ssi1_root_podf] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); - clk[ssi2_root_pred] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); - clk[ssi2_root_podf] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); - clk[ssi_ext1_pred] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); - clk[ssi_ext1_podf] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); - clk[ssi_ext2_pred] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); - clk[ssi_ext2_podf] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); - clk[ssi1_root_gate] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); - clk[ssi2_root_gate] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); - clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); - clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); - clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); - clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); - clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); - clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); - clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); - clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); - clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); - clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); - clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); - clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); - clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); - clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, - spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); - clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); - clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX5 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); - clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); - clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0"); - clk_register_clkdev(clk[uart2_per_gate], "per", "imx21-uart.1"); - clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1"); - clk_register_clkdev(clk[uart3_per_gate], "per", "imx21-uart.2"); - clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2"); - clk_register_clkdev(clk[uart4_per_gate], "per", "imx21-uart.3"); - clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3"); - clk_register_clkdev(clk[uart5_per_gate], "per", "imx21-uart.4"); - clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4"); - clk_register_clkdev(clk[ecspi1_per_gate], "per", "imx51-ecspi.0"); - clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0"); - clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1"); - clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1"); - clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2"); - clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0"); - clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1"); - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.0"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.0"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.0"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.1"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.1"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.1"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "mxc-ehci.2"); - clk_register_clkdev(clk[usboh3_per_gate], "per", "imx-udc-mx51"); - clk_register_clkdev(clk[usboh3_gate], "ipg", "imx-udc-mx51"); - clk_register_clkdev(clk[usboh3_gate], "ahb", "imx-udc-mx51"); - clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand"); - clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); - clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); - clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); - clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0"); - clk_register_clkdev(clk[iim_gate], "iim", NULL); - clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); - clk_register_clkdev(clk[dummy], NULL, "imx-keypad"); - clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0"); - clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL); - clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0"); - clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0"); - clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1"); - clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1"); - - /* Set SDHC parents to be PLL2 */ - clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]); - clk_set_parent(clk[esdhc_b_sel], clk[pll2_sw]); - - /* move usb phy clk to 24MHz */ - clk_set_parent(clk[usb_phy_sel], clk[osc]); - - clk_prepare_enable(clk[gpc_dvfs]); - clk_prepare_enable(clk[ahb_max]); /* esdhc3 */ - clk_prepare_enable(clk[aips_tz1]); - clk_prepare_enable(clk[aips_tz2]); /* fec */ - clk_prepare_enable(clk[spba]); - clk_prepare_enable(clk[emi_fast_gate]); /* fec */ - clk_prepare_enable(clk[emi_slow_gate]); /* eim */ - clk_prepare_enable(clk[mipi_hsc1_gate]); - clk_prepare_enable(clk[mipi_hsc2_gate]); - clk_prepare_enable(clk[mipi_esc_gate]); - clk_prepare_enable(clk[mipi_hsp_gate]); - clk_prepare_enable(clk[tmax1]); - clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ - clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ -} - -int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) -{ - int i; - u32 val; - struct device_node *np; - - clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); - clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE); - clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE); - clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, - mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel)); - clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, - mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel)); - clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, - mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT); - clk[tve_s] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, - mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel)); - clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); - clk[tve_pred] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); - clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); - clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); - clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); - clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); - clk[usb_phy_gate] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); - clk[hsi2c_gate] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); - clk[mipi_hsc1_gate] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); - clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); - clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); - clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); - clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, - mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); - clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, - spdif_sel, ARRAY_SIZE(spdif_sel)); - clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); - clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); - clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, - mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); - clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX51 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm"); - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - - mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); - - clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL); - clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0"); - clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); - clk_register_clkdev(clk[usb_phy_gate], "phy", "mxc-ehci.0"); - clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx51.0"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.0"); - clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx51.0"); - clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx51.1"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.1"); - clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx51.1"); - clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx51.2"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.2"); - clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx51.2"); - clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3"); - clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3"); - - /* set the usboh3 parent to pll2_sw */ - clk_set_parent(clk[usboh3_sel], clk[pll2_sw]); - - /* set SDHC root clock to 166.25MHZ*/ - clk_set_rate(clk[esdhc_a_podf], 166250000); - clk_set_rate(clk[esdhc_b_podf], 166250000); - - /* System timer */ - mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT); - - clk_prepare_enable(clk[iim_gate]); - imx_print_silicon_rev("i.MX51", mx51_revision()); - clk_disable_unprepare(clk[iim_gate]); - - /* - * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no - * longer supported. Set to one for better power saving. - * - * The effect of not setting these bits is that MIPI clocks can't be - * enabled without the IPU clock being enabled aswell. - */ - val = readl(MXC_CCM_CCDR); - val |= 1 << 18; - writel(val, MXC_CCM_CCDR); - - val = readl(MXC_CCM_CLPCR); - val |= 1 << 23; - writel(val, MXC_CCM_CLPCR); - - return 0; -} - -int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, - unsigned long rate_ckih1, unsigned long rate_ckih2) -{ - int i; - unsigned long r; - struct device_node *np; - - clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); - clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); - clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE); - clk[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE); - - clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clk[ldb_di1_div] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); - clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, - mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT); - clk[di_pll4_podf] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); - clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clk[ldb_di0_div] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); - clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, - mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT); - clk[ldb_di0_gate] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); - clk[ldb_di1_gate] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); - clk[ipu_di0_sel] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, - mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel)); - clk[ipu_di1_sel] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, - mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel)); - clk[tve_ext_sel] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, - mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT); - clk[tve_gate] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); - clk[tve_pred] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); - clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); - clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); - clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); - clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); - clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); - clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); - clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, - mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); - clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); - clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); - clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); - clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); - clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); - clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); - - clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, - mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); - clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); - clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); - - clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, - mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); - clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); - clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); - clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, - mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX53 clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm"); - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - - mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2); - - clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0"); - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); - clk_register_clkdev(clk[fec_gate], NULL, "imx25-fec.0"); - clk_register_clkdev(clk[usb_phy1_gate], "usb_phy1", "mxc-ehci.0"); - clk_register_clkdev(clk[esdhc1_ipg_gate], "ipg", "sdhci-esdhc-imx53.0"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.0"); - clk_register_clkdev(clk[esdhc1_per_gate], "per", "sdhci-esdhc-imx53.0"); - clk_register_clkdev(clk[esdhc2_ipg_gate], "ipg", "sdhci-esdhc-imx53.1"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.1"); - clk_register_clkdev(clk[esdhc2_per_gate], "per", "sdhci-esdhc-imx53.1"); - clk_register_clkdev(clk[esdhc3_ipg_gate], "ipg", "sdhci-esdhc-imx53.2"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.2"); - clk_register_clkdev(clk[esdhc3_per_gate], "per", "sdhci-esdhc-imx53.2"); - clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3"); - clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3"); - clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3"); - - /* set SDHC root clock to 200MHZ*/ - clk_set_rate(clk[esdhc_a_podf], 200000000); - clk_set_rate(clk[esdhc_b_podf], 200000000); - - /* System timer */ - mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT); - - clk_prepare_enable(clk[iim_gate]); - imx_print_silicon_rev("i.MX53", mx53_revision()); - clk_disable_unprepare(clk[iim_gate]); - - r = clk_round_rate(clk[usboh3_per_gate], 54000000); - clk_set_rate(clk[usboh3_per_gate], r); - - return 0; -} - -int __init mx51_clocks_init_dt(void) -{ - return mx51_clocks_init(0, 0, 0, 0); -} - -int __init mx53_clocks_init_dt(void) -{ - return mx53_clocks_init(0, 0, 0, 0); -} diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c deleted file mode 100644 index 4282e99f5ca1..000000000000 --- a/arch/arm/mach-imx/clk-imx6q.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/types.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> - -#include "clk.h" -#include "common.h" -#include "hardware.h" - -#define CCR 0x0 -#define BM_CCR_WB_COUNT (0x7 << 16) -#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) -#define BM_CCR_RBC_EN (0x1 << 27) - -#define CCGR0 0x68 -#define CCGR1 0x6c -#define CCGR2 0x70 -#define CCGR3 0x74 -#define CCGR4 0x78 -#define CCGR5 0x7c -#define CCGR6 0x80 -#define CCGR7 0x84 - -#define CLPCR 0x54 -#define BP_CLPCR_LPM 0 -#define BM_CLPCR_LPM (0x3 << 0) -#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) -#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define BM_CLPCR_SBYOS (0x1 << 6) -#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define BM_CLPCR_VSTBY (0x1 << 8) -#define BP_CLPCR_STBY_COUNT 9 -#define BM_CLPCR_STBY_COUNT (0x3 << 9) -#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) -#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) -#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) -#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) -#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) -#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) -#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) -#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) -#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) -#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) - -#define CGPR 0x64 -#define BM_CGPR_CHICKEN_BIT (0x1 << 17) - -static void __iomem *ccm_base; - -void imx6q_set_chicken_bit(void) -{ - u32 val = readl_relaxed(ccm_base + CGPR); - - val |= BM_CGPR_CHICKEN_BIT; - writel_relaxed(val, ccm_base + CGPR); -} - -static void imx6q_enable_rbc(bool enable) -{ - u32 val; - static bool last_rbc_mode; - - if (last_rbc_mode == enable) - return; - /* - * need to mask all interrupts in GPC before - * operating RBC configurations - */ - imx_gpc_mask_all(); - - /* configure RBC enable bit */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_EN; - val |= enable ? BM_CCR_RBC_EN : 0; - writel_relaxed(val, ccm_base + CCR); - - /* configure RBC count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_RBC_BYPASS_COUNT; - val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; - writel(val, ccm_base + CCR); - - /* - * need to delay at least 2 cycles of CKIL(32K) - * due to hardware design requirement, which is - * ~61us, here we use 65us for safe - */ - udelay(65); - - /* restore GPC interrupt mask settings */ - imx_gpc_restore_all(); - - last_rbc_mode = enable; -} - -static void imx6q_enable_wb(bool enable) -{ - u32 val; - static bool last_wb_mode; - - if (last_wb_mode == enable) - return; - - /* configure well bias enable bit */ - val = readl_relaxed(ccm_base + CLPCR); - val &= ~BM_CLPCR_WB_PER_AT_LPM; - val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; - writel_relaxed(val, ccm_base + CLPCR); - - /* configure well bias count */ - val = readl_relaxed(ccm_base + CCR); - val &= ~BM_CCR_WB_COUNT; - val |= enable ? BM_CCR_WB_COUNT : 0; - writel_relaxed(val, ccm_base + CCR); - - last_wb_mode = enable; -} - -int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -{ - u32 val = readl_relaxed(ccm_base + CLPCR); - - val &= ~BM_CLPCR_LPM; - switch (mode) { - case WAIT_CLOCKED: - imx6q_enable_wb(false); - imx6q_enable_rbc(false); - break; - case WAIT_UNCLOCKED: - val |= 0x1 << BP_CLPCR_LPM; - val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; - break; - case STOP_POWER_ON: - val |= 0x2 << BP_CLPCR_LPM; - break; - case WAIT_UNCLOCKED_POWER_OFF: - val |= 0x1 << BP_CLPCR_LPM; - val &= ~BM_CLPCR_VSTBY; - val &= ~BM_CLPCR_SBYOS; - break; - case STOP_POWER_OFF: - val |= 0x2 << BP_CLPCR_LPM; - val |= 0x3 << BP_CLPCR_STBY_COUNT; - val |= BM_CLPCR_VSTBY; - val |= BM_CLPCR_SBYOS; - imx6q_enable_wb(true); - imx6q_enable_rbc(true); - break; - default: - return -EINVAL; - } - - writel_relaxed(val, ccm_base + CLPCR); - - return 0; -} - -static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; -static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; -static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; -static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; -static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; -static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; -static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; -static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; -static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; -static const char *gpu_axi_sels[] = { "axi", "ahb", }; -static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; -static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; -static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; -static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; -static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; -static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; -static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; -static const char *pcie_axi_sels[] = { "axi", "ahb", }; -static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; -static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; -static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *vdo_axi_sels[] = { "axi", "ahb", }; -static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", - "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", - "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; - -enum mx6q_clks { - dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, - pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, - pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, - periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, - esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, - gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, - ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, - ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, - ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, - usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, - emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, - periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, - asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root, - gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, - ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre, - ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf, - ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf, - usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf, - emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, - mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial, - can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, - esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, - hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, - ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, - mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, - gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, - ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, - usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, - pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, - sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, - usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max -}; - -static struct clk *clk[clk_max]; -static struct clk_onecell_data clk_data; - -static enum mx6q_clks const clks_init_on[] __initconst = { - mmdc_ch0_axi, rom, pll1_sys, -}; - -static struct clk_div_table clk_enet_ref_table[] = { - { .val = 0, .div = 20, }, - { .val = 1, .div = 10, }, - { .val = 2, .div = 5, }, - { .val = 3, .div = 4, }, -}; - -static struct clk_div_table post_div_table[] = { - { .val = 2, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 0, .div = 4, }, - { } -}; - -static struct clk_div_table video_div_table[] = { - { .val = 0, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 2, .div = 1, }, - { .val = 3, .div = 4, }, - { } -}; - -static void __init imx6q_clocks_init(struct device_node *ccm_node) -{ - struct device_node *np; - void __iomem *base; - int i, irq; - - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckil] = imx_obtain_fixed_clock("ckil", 0); - clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); - clk[osc] = imx_obtain_fixed_clock("osc", 0); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); - base = of_iomap(np, 0); - WARN_ON(!base); - - /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ - if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) { - post_div_table[1].div = 1; - post_div_table[2].div = 1; - video_div_table[1].div = 1; - video_div_table[2].div = 1; - }; - - /* type name parent_name base div_mask */ - clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); - clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); - clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); - clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); - clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); - clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); - clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); - - /* - * Bit 20 is the reserved and read-only bit, we do this only for: - * - Do nothing for usbphy clk_enable/disable - * - Keep refcount when do usbphy clk_enable/disable, in that case, - * the clk framework may need to enable/disable usbphy's parent - */ - clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); - clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); - - /* - * usbphy*_gate needs to be on after system boots up, and software - * never needs to control it anymore. - */ - clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); - clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); - - clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); - clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); - - clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); - clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); - - clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, - base + 0xe0, 0, 2, 0, clk_enet_ref_table, - &imx_ccm_lock); - - /* name parent_name reg idx */ - clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); - clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); - clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); - clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); - clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); - clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); - clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); - - /* name parent_name mult div */ - clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); - clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); - clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); - clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); - clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); - - clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); - clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); - clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); - - np = ccm_node; - base = of_iomap(np, 0); - WARN_ON(!base); - ccm_base = base; - - /* name reg shift width parent_names num_parents */ - clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); - clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); - clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); - clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); - clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); - clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); - clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); - clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); - clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); - clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); - clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); - clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); - clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); - clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); - clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); - clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); - clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); - clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); - clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels)); - clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); - clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); - clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); - - /* name reg shift width busy: reg, shift parent_names num_parents */ - clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); - clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); - - /* name parent_name reg shift width */ - clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); - clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); - clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); - clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); - clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); - clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); - clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); - clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); - clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); - clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); - clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); - clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); - clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); - clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); - clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); - clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); - clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); - clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); - clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); - clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); - clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); - clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); - clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); - clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); - clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); - clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); - clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); - clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); - clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); - clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); - clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); - clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); - clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); - clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); - clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); - clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); - clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); - clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); - clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); - clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); - clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); - - /* name parent_name reg shift width busy: reg, shift */ - clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); - clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); - clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); - clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); - clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); - - /* name parent_name reg shift */ - clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); - clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); - clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); - clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); - clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); - clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); - clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); - clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); - clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); - clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); - clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); - clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); - clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); - clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); - clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); - if (cpu_is_imx6dl()) - /* - * The multiplexer and divider of imx6q clock gpu3d_shader get - * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. - */ - clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); - else - clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); - clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); - clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); - clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); - clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); - clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); - clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); - clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); - clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); - clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); - clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); - clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); - clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); - clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); - clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); - clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); - clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); - clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); - if (cpu_is_imx6dl()) - /* - * The multiplexer and divider of the imx6q clock gpu2d get - * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. - */ - clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); - else - clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); - clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); - clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); - clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); - clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); - clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); - clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); - clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); - clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); - clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); - clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); - clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); - clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); - clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); - clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); - clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); - clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); - clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); - clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); - clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); - clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); - clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); - clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); - clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); - clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); - clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); - clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); - clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); - clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); - clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); - clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); - clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); - clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); - - for (i = 0; i < ARRAY_SIZE(clk); i++) - if (IS_ERR(clk[i])) - pr_err("i.MX6q clk %d: register failed with %ld\n", - i, PTR_ERR(clk[i])); - - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - - clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); - clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); - clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); - clk_register_clkdev(clk[ahb], "ahb", NULL); - clk_register_clkdev(clk[cko1], "cko1", NULL); - clk_register_clkdev(clk[arm], NULL, "cpu0"); - clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); - clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); - - if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { - clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); - clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); - } - - /* - * The gpmi needs 100MHz frequency in the EDO/Sync mode, - * We can not get the 100MHz from the pll2_pfd0_352m. - * So choose pll2_pfd2_396m as enfc_sel's parent. - */ - clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); - - for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) - clk_prepare_enable(clk[clks_init_on[i]]); - - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clk[usbphy1_gate]); - clk_prepare_enable(clk[usbphy2_gate]); - } - - /* Set initial power mode */ - imx6q_set_lpm(WAIT_CLOCKED); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); -} -CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c deleted file mode 100644 index a307ac22dffe..000000000000 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/err.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <dt-bindings/clock/imx6sl-clock.h> - -#include "clk.h" -#include "common.h" - -static const char const *step_sels[] = { "osc", "pll2_pfd2", }; -static const char const *pll1_sw_sels[] = { "pll1_sys", "step", }; -static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", }; -static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", }; -static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", }; -static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; -static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; -static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", }; -static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", }; -static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", }; -static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", }; -static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", }; -static const char const *perclk_sels[] = { "ipg", "osc", }; -static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", }; -static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", }; -static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", }; -static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", }; -static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", }; -static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", }; -static const char const *ecspi_sels[] = { "pll3_60m", "osc", }; -static const char const *uart_sels[] = { "pll3_80m", "osc", }; - -static struct clk_div_table clk_enet_ref_table[] = { - { .val = 0, .div = 20, }, - { .val = 1, .div = 10, }, - { .val = 2, .div = 5, }, - { .val = 3, .div = 4, }, - { } -}; - -static struct clk_div_table post_div_table[] = { - { .val = 2, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 0, .div = 4, }, - { } -}; - -static struct clk_div_table video_div_table[] = { - { .val = 0, .div = 1, }, - { .val = 1, .div = 2, }, - { .val = 2, .div = 1, }, - { .val = 3, .div = 4, }, - { } -}; - -static struct clk *clks[IMX6SL_CLK_CLK_END]; -static struct clk_onecell_data clk_data; - -static void __init imx6sl_clocks_init(struct device_node *ccm_node) -{ - struct device_node *np; - void __iomem *base; - int irq; - int i; - - clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); - clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); - base = of_iomap(np, 0); - WARN_ON(!base); - - /* type name parent base div_mask */ - clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f); - clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1); - clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3); - clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f); - clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); - clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); - clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3); - - /* - * usbphy1 and usbphy2 are implemented as dummy gates using reserve - * bit 20. They are used by phy driver to keep the refcount of - * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be - * turned on during boot, and software will not need to control it - * anymore after that. - */ - clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); - clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); - clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); - clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); - - /* dev name parent_name flags reg shift width div: flags, div_table lock */ - clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); - clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); - clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); - clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); - - /* name parent_name reg idx */ - clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0); - clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1); - clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2); - clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0); - clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1); - clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2); - clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3); - - /* name parent_name mult div */ - clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2); - clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); - clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); - clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); - - np = ccm_node; - base = of_iomap(np, 0); - WARN_ON(!base); - - /* name reg shift width parent_names num_parents */ - clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); - clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels)); - clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels)); - clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); - clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); - clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); - clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); - clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); - clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); - clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); - clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); - clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); - clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); - clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); - clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels)); - clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels)); - clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels)); - clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); - clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); - - /* name reg shift width busy: reg, shift parent_names num_parents */ - clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); - clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); - - /* name parent_name reg shift width */ - clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3); - clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3); - clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3); - clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); - clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); - clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3); - clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); - clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); - clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); - clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); - clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); - clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); - clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); - clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); - clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); - clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); - clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); - clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); - clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); - clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); - clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); - clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); - clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); - clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3); - clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); - clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); - clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); - clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); - clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); - clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3); - clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3); - clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); - clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6); - - /* name parent_name reg shift width busy: reg, shift */ - clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); - clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2); - clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); - - /* name parent_name reg shift */ - clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); - clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); - clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); - clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); - clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); - clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); - clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); - clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20); - clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22); - clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26); - clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); - clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); - clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); - clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); - clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0); - clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2); - clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4); - clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6); - clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8); - clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10); - clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28); - clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); - clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); - clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); - clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); - clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6); - clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14); - clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18); - clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20); - clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22); - clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24); - clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26); - clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); - clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); - clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); - clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); - clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); - - for (i = 0; i < ARRAY_SIZE(clks); i++) - if (IS_ERR(clks[i])) - pr_err("i.MX6SL clk %d: register failed with %ld\n", - i, PTR_ERR(clks[i])); - - clk_data.clks = clks; - clk_data.clk_num = ARRAY_SIZE(clks); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - - clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0"); - clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0"); - - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]); - clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]); - } - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); - base = of_iomap(np, 0); - WARN_ON(!base); - irq = irq_of_parse_and_map(np, 0); - mxc_timer_init(base, irq); -} -CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c deleted file mode 100644 index e2ed4160f329..000000000000 --- a/arch/arm/mach-imx/clk-pfd.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/err.h> -#include "clk.h" - -/** - * struct clk_pfd - IMX PFD clock - * @clk_hw: clock source - * @reg: PFD register address - * @idx: the index of PFD encoded in the register - * - * PFD clock found on i.MX6 series. Each register for PFD has 4 clk_pfd - * data encoded, and member idx is used to specify the one. And each - * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc. - */ -struct clk_pfd { - struct clk_hw hw; - void __iomem *reg; - u8 idx; -}; - -#define to_clk_pfd(_hw) container_of(_hw, struct clk_pfd, hw) - -#define SET 0x4 -#define CLR 0x8 -#define OTG 0xc - -static int clk_pfd_enable(struct clk_hw *hw) -{ - struct clk_pfd *pfd = to_clk_pfd(hw); - - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); - - return 0; -} - -static void clk_pfd_disable(struct clk_hw *hw) -{ - struct clk_pfd *pfd = to_clk_pfd(hw); - - writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); -} - -static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pfd *pfd = to_clk_pfd(hw); - u64 tmp = parent_rate; - u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; - - tmp *= 18; - do_div(tmp, frac); - - return tmp; -} - -static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - u64 tmp = *prate; - u8 frac; - - tmp = tmp * 18 + rate / 2; - do_div(tmp, rate); - frac = tmp; - if (frac < 12) - frac = 12; - else if (frac > 35) - frac = 35; - tmp = *prate; - tmp *= 18; - do_div(tmp, frac); - - return tmp; -} - -static int clk_pfd_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_pfd *pfd = to_clk_pfd(hw); - u64 tmp = parent_rate; - u8 frac; - - tmp = tmp * 18 + rate / 2; - do_div(tmp, rate); - frac = tmp; - if (frac < 12) - frac = 12; - else if (frac > 35) - frac = 35; - - writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); - writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); - - return 0; -} - -static const struct clk_ops clk_pfd_ops = { - .enable = clk_pfd_enable, - .disable = clk_pfd_disable, - .recalc_rate = clk_pfd_recalc_rate, - .round_rate = clk_pfd_round_rate, - .set_rate = clk_pfd_set_rate, -}; - -struct clk *imx_clk_pfd(const char *name, const char *parent_name, - void __iomem *reg, u8 idx) -{ - struct clk_pfd *pfd; - struct clk *clk; - struct clk_init_data init; - - pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); - if (!pfd) - return ERR_PTR(-ENOMEM); - - pfd->reg = reg; - pfd->idx = idx; - - init.name = name; - init.ops = &clk_pfd_ops; - init.flags = 0; - init.parent_names = &parent_name; - init.num_parents = 1; - - pfd->hw.init = &init; - - clk = clk_register(NULL, &pfd->hw); - if (IS_ERR(clk)) - kfree(pfd); - - return clk; -} diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c deleted file mode 100644 index c1eaee346954..000000000000 --- a/arch/arm/mach-imx/clk-pllv1.c +++ /dev/null @@ -1,111 +0,0 @@ -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/kernel.h> -#include <linux/err.h> - -#include "clk.h" -#include "common.h" -#include "hardware.h" - -/** - * pll v1 - * - * @clk_hw clock source - * @parent the parent clock name - * @base base address of pll registers - * - * PLL clock version 1, found on i.MX1/21/25/27/31/35 - */ -struct clk_pllv1 { - struct clk_hw hw; - void __iomem *base; -}; - -#define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk)) - -static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pllv1 *pll = to_clk_pllv1(hw); - long long ll; - int mfn_abs; - unsigned int mfi, mfn, mfd, pd; - u32 reg; - unsigned long rate; - - reg = readl(pll->base); - - /* - * Get the resulting clock rate from a PLL register value and the input - * frequency. PLLs with this register layout can be found on i.MX1, - * i.MX21, i.MX27 and i,MX31 - * - * mfi + mfn / (mfd + 1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ - - mfi = (reg >> 10) & 0xf; - mfn = reg & 0x3ff; - mfd = (reg >> 16) & 0x3ff; - pd = (reg >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - mfn_abs = mfn; - - /* - * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit - * 2's complements number - */ - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - mfn_abs = 0x400 - mfn; - - rate = parent_rate * 2; - rate /= pd + 1; - - ll = (unsigned long long)rate * mfn_abs; - - do_div(ll, mfd + 1); - - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - ll = -ll; - - ll = (rate * mfi) + ll; - - return ll; -} - -static struct clk_ops clk_pllv1_ops = { - .recalc_rate = clk_pllv1_recalc_rate, -}; - -struct clk *imx_clk_pllv1(const char *name, const char *parent, - void __iomem *base) -{ - struct clk_pllv1 *pll; - struct clk *clk; - struct clk_init_data init; - - pll = kmalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) - return ERR_PTR(-ENOMEM); - - pll->base = base; - - init.name = name; - init.ops = &clk_pllv1_ops; - init.flags = 0; - init.parent_names = &parent; - init.num_parents = 1; - - pll->hw.init = &init; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) - kfree(pll); - - return clk; -} diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c deleted file mode 100644 index 20889d59b44d..000000000000 --- a/arch/arm/mach-imx/clk-pllv2.c +++ /dev/null @@ -1,266 +0,0 @@ -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/errno.h> -#include <linux/delay.h> -#include <linux/slab.h> -#include <linux/err.h> - -#include <asm/div64.h> - -#include "clk.h" - -#define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk)) - -/* PLL Register Offsets */ -#define MXC_PLL_DP_CTL 0x00 -#define MXC_PLL_DP_CONFIG 0x04 -#define MXC_PLL_DP_OP 0x08 -#define MXC_PLL_DP_MFD 0x0C -#define MXC_PLL_DP_MFN 0x10 -#define MXC_PLL_DP_MFNMINUS 0x14 -#define MXC_PLL_DP_MFNPLUS 0x18 -#define MXC_PLL_DP_HFS_OP 0x1C -#define MXC_PLL_DP_HFS_MFD 0x20 -#define MXC_PLL_DP_HFS_MFN 0x24 -#define MXC_PLL_DP_MFN_TOGC 0x28 -#define MXC_PLL_DP_DESTAT 0x2c - -/* PLL Register Bit definitions */ -#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 -#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 -#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 -#define MXC_PLL_DP_CTL_ADE 0x800 -#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 -#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) -#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 -#define MXC_PLL_DP_CTL_HFSM 0x80 -#define MXC_PLL_DP_CTL_PRE 0x40 -#define MXC_PLL_DP_CTL_UPEN 0x20 -#define MXC_PLL_DP_CTL_RST 0x10 -#define MXC_PLL_DP_CTL_RCP 0x8 -#define MXC_PLL_DP_CTL_PLM 0x4 -#define MXC_PLL_DP_CTL_BRM0 0x2 -#define MXC_PLL_DP_CTL_LRF 0x1 - -#define MXC_PLL_DP_CONFIG_BIST 0x8 -#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 -#define MXC_PLL_DP_CONFIG_AREN 0x2 -#define MXC_PLL_DP_CONFIG_LDREQ 0x1 - -#define MXC_PLL_DP_OP_MFI_OFFSET 4 -#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) -#define MXC_PLL_DP_OP_PDF_OFFSET 0 -#define MXC_PLL_DP_OP_PDF_MASK 0xF - -#define MXC_PLL_DP_MFD_OFFSET 0 -#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF - -#define MXC_PLL_DP_MFN_OFFSET 0x0 -#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF - -#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) -#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) -#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 -#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF - -#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) -#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF - -#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ - -struct clk_pllv2 { - struct clk_hw hw; - void __iomem *base; -}; - -static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, - u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn) -{ - long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; - unsigned long dbl; - s64 temp; - - dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; - - pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; - mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; - mfi = (mfi <= 5) ? 5 : mfi; - mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; - mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; - /* Sign extend to 32-bits */ - if (mfn >= 0x04000000) { - mfn |= 0xFC000000; - mfn_abs = -mfn; - } - - ref_clk = 2 * parent_rate; - if (dbl != 0) - ref_clk *= 2; - - ref_clk /= (pdf + 1); - temp = (u64) ref_clk * mfn_abs; - do_div(temp, mfd + 1); - if (mfn < 0) - temp = -temp; - temp = (ref_clk * mfi) + temp; - - return temp; -} - -static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - u32 dp_op, dp_mfd, dp_mfn, dp_ctl; - void __iomem *pllbase; - struct clk_pllv2 *pll = to_clk_pllv2(hw); - - pllbase = pll->base; - - dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); - dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); - dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); - dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); - - return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn); -} - -static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate, - u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn) -{ - u32 reg; - long mfi, pdf, mfn, mfd = 999999; - s64 temp64; - unsigned long quad_parent_rate; - - quad_parent_rate = 4 * parent_rate; - pdf = mfi = -1; - while (++pdf < 16 && mfi < 5) - mfi = rate * (pdf+1) / quad_parent_rate; - if (mfi > 15) - return -EINVAL; - pdf--; - - temp64 = rate * (pdf + 1) - quad_parent_rate * mfi; - do_div(temp64, quad_parent_rate / 1000000); - mfn = (long)temp64; - - reg = mfi << 4 | pdf; - - *dp_op = reg; - *dp_mfd = mfd; - *dp_mfn = mfn; - - return 0; -} - -static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_pllv2 *pll = to_clk_pllv2(hw); - void __iomem *pllbase; - u32 dp_ctl, dp_op, dp_mfd, dp_mfn; - int ret; - - pllbase = pll->base; - - - ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn); - if (ret) - return ret; - - dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); - /* use dpdck0_2 */ - __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); - - __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP); - __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD); - __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN); - - return 0; -} - -static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - u32 dp_op, dp_mfd, dp_mfn; - - __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn); - return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN, - dp_op, dp_mfd, dp_mfn); -} - -static int clk_pllv2_prepare(struct clk_hw *hw) -{ - struct clk_pllv2 *pll = to_clk_pllv2(hw); - u32 reg; - void __iomem *pllbase; - int i = 0; - - pllbase = pll->base; - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); - - /* Wait for lock */ - do { - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); - if (reg & MXC_PLL_DP_CTL_LRF) - break; - - udelay(1); - } while (++i < MAX_DPLL_WAIT_TRIES); - - if (i == MAX_DPLL_WAIT_TRIES) { - pr_err("MX5: pll locking failed\n"); - return -EINVAL; - } - - return 0; -} - -static void clk_pllv2_unprepare(struct clk_hw *hw) -{ - struct clk_pllv2 *pll = to_clk_pllv2(hw); - u32 reg; - void __iomem *pllbase; - - pllbase = pll->base; - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); -} - -static struct clk_ops clk_pllv2_ops = { - .prepare = clk_pllv2_prepare, - .unprepare = clk_pllv2_unprepare, - .recalc_rate = clk_pllv2_recalc_rate, - .round_rate = clk_pllv2_round_rate, - .set_rate = clk_pllv2_set_rate, -}; - -struct clk *imx_clk_pllv2(const char *name, const char *parent, - void __iomem *base) -{ - struct clk_pllv2 *pll; - struct clk *clk; - struct clk_init_data init; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) - return ERR_PTR(-ENOMEM); - - pll->base = base; - - init.name = name; - init.ops = &clk_pllv2_ops; - init.flags = 0; - init.parent_names = &parent; - init.num_parents = 1; - - pll->hw.init = &init; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) - kfree(pll); - - return clk; -} diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c deleted file mode 100644 index a9fad5f8d340..000000000000 --- a/arch/arm/mach-imx/clk-pllv3.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/jiffies.h> -#include <linux/err.h> -#include "clk.h" - -#define PLL_NUM_OFFSET 0x10 -#define PLL_DENOM_OFFSET 0x20 - -#define BM_PLL_POWER (0x1 << 12) -#define BM_PLL_ENABLE (0x1 << 13) -#define BM_PLL_BYPASS (0x1 << 16) -#define BM_PLL_LOCK (0x1 << 31) - -/** - * struct clk_pllv3 - IMX PLL clock version 3 - * @clk_hw: clock source - * @base: base address of PLL registers - * @powerup_set: set POWER bit to power up the PLL - * @div_mask: mask of divider bits - * - * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 - * is actually a multiplier, and always sits at bit 0. - */ -struct clk_pllv3 { - struct clk_hw hw; - void __iomem *base; - bool powerup_set; - u32 div_mask; -}; - -#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) - -static int clk_pllv3_prepare(struct clk_hw *hw) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long timeout = jiffies + msecs_to_jiffies(10); - u32 val; - - val = readl_relaxed(pll->base); - val &= ~BM_PLL_BYPASS; - if (pll->powerup_set) - val |= BM_PLL_POWER; - else - val &= ~BM_PLL_POWER; - writel_relaxed(val, pll->base); - - /* Wait for PLL to lock */ - while (!(readl_relaxed(pll->base) & BM_PLL_LOCK)) - if (time_after(jiffies, timeout)) - return -ETIMEDOUT; - - return 0; -} - -static void clk_pllv3_unprepare(struct clk_hw *hw) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; - - val = readl_relaxed(pll->base); - val |= BM_PLL_BYPASS; - if (pll->powerup_set) - val &= ~BM_PLL_POWER; - else - val |= BM_PLL_POWER; - writel_relaxed(val, pll->base); -} - -static int clk_pllv3_enable(struct clk_hw *hw) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; - - val = readl_relaxed(pll->base); - val |= BM_PLL_ENABLE; - writel_relaxed(val, pll->base); - - return 0; -} - -static void clk_pllv3_disable(struct clk_hw *hw) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val; - - val = readl_relaxed(pll->base); - val &= ~BM_PLL_ENABLE; - writel_relaxed(val, pll->base); -} - -static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 div = readl_relaxed(pll->base) & pll->div_mask; - - return (div == 1) ? parent_rate * 22 : parent_rate * 20; -} - -static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long parent_rate = *prate; - - return (rate >= parent_rate * 22) ? parent_rate * 22 : - parent_rate * 20; -} - -static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 val, div; - - if (rate == parent_rate * 22) - div = 1; - else if (rate == parent_rate * 20) - div = 0; - else - return -EINVAL; - - val = readl_relaxed(pll->base); - val &= ~pll->div_mask; - val |= div; - writel_relaxed(val, pll->base); - - return 0; -} - -static const struct clk_ops clk_pllv3_ops = { - .prepare = clk_pllv3_prepare, - .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, - .recalc_rate = clk_pllv3_recalc_rate, - .round_rate = clk_pllv3_round_rate, - .set_rate = clk_pllv3_set_rate, -}; - -static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 div = readl_relaxed(pll->base) & pll->div_mask; - - return parent_rate * div / 2; -} - -static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long parent_rate = *prate; - unsigned long min_rate = parent_rate * 54 / 2; - unsigned long max_rate = parent_rate * 108 / 2; - u32 div; - - if (rate > max_rate) - rate = max_rate; - else if (rate < min_rate) - rate = min_rate; - div = rate * 2 / parent_rate; - - return parent_rate * div / 2; -} - -static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long min_rate = parent_rate * 54 / 2; - unsigned long max_rate = parent_rate * 108 / 2; - u32 val, div; - - if (rate < min_rate || rate > max_rate) - return -EINVAL; - - div = rate * 2 / parent_rate; - val = readl_relaxed(pll->base); - val &= ~pll->div_mask; - val |= div; - writel_relaxed(val, pll->base); - - return 0; -} - -static const struct clk_ops clk_pllv3_sys_ops = { - .prepare = clk_pllv3_prepare, - .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, - .recalc_rate = clk_pllv3_sys_recalc_rate, - .round_rate = clk_pllv3_sys_round_rate, - .set_rate = clk_pllv3_sys_set_rate, -}; - -static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); - u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET); - u32 div = readl_relaxed(pll->base) & pll->div_mask; - - return (parent_rate * div) + ((parent_rate / mfd) * mfn); -} - -static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - unsigned long parent_rate = *prate; - unsigned long min_rate = parent_rate * 27; - unsigned long max_rate = parent_rate * 54; - u32 div; - u32 mfn, mfd = 1000000; - s64 temp64; - - if (rate > max_rate) - rate = max_rate; - else if (rate < min_rate) - rate = min_rate; - - div = rate / parent_rate; - temp64 = (u64) (rate - div * parent_rate); - temp64 *= mfd; - do_div(temp64, parent_rate); - mfn = temp64; - - return parent_rate * div + parent_rate / mfd * mfn; -} - -static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long min_rate = parent_rate * 27; - unsigned long max_rate = parent_rate * 54; - u32 val, div; - u32 mfn, mfd = 1000000; - s64 temp64; - - if (rate < min_rate || rate > max_rate) - return -EINVAL; - - div = rate / parent_rate; - temp64 = (u64) (rate - div * parent_rate); - temp64 *= mfd; - do_div(temp64, parent_rate); - mfn = temp64; - - val = readl_relaxed(pll->base); - val &= ~pll->div_mask; - val |= div; - writel_relaxed(val, pll->base); - writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); - writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); - - return 0; -} - -static const struct clk_ops clk_pllv3_av_ops = { - .prepare = clk_pllv3_prepare, - .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, - .recalc_rate = clk_pllv3_av_recalc_rate, - .round_rate = clk_pllv3_av_round_rate, - .set_rate = clk_pllv3_av_set_rate, -}; - -static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - return 500000000; -} - -static const struct clk_ops clk_pllv3_enet_ops = { - .prepare = clk_pllv3_prepare, - .unprepare = clk_pllv3_unprepare, - .enable = clk_pllv3_enable, - .disable = clk_pllv3_disable, - .recalc_rate = clk_pllv3_enet_recalc_rate, -}; - -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, - u32 div_mask) -{ - struct clk_pllv3 *pll; - const struct clk_ops *ops; - struct clk *clk; - struct clk_init_data init; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) - return ERR_PTR(-ENOMEM); - - switch (type) { - case IMX_PLLV3_SYS: - ops = &clk_pllv3_sys_ops; - break; - case IMX_PLLV3_USB: - ops = &clk_pllv3_ops; - pll->powerup_set = true; - break; - case IMX_PLLV3_AV: - ops = &clk_pllv3_av_ops; - break; - case IMX_PLLV3_ENET: - ops = &clk_pllv3_enet_ops; - break; - default: - ops = &clk_pllv3_ops; - } - pll->base = base; - pll->div_mask = div_mask; - - init.name = name; - init.ops = ops; - init.flags = 0; - init.parent_names = &parent_name; - init.num_parents = 1; - - pll->hw.init = &init; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) - kfree(pll); - - return clk; -} diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c deleted file mode 100644 index d617c0b7c809..000000000000 --- a/arch/arm/mach-imx/clk-vf610.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright 2012-2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - */ - -#include <linux/of_address.h> -#include <linux/clk.h> -#include <dt-bindings/clock/vf610-clock.h> - -#include "clk.h" - -#define CCM_CCR (ccm_base + 0x00) -#define CCM_CSR (ccm_base + 0x04) -#define CCM_CCSR (ccm_base + 0x08) -#define CCM_CACRR (ccm_base + 0x0c) -#define CCM_CSCMR1 (ccm_base + 0x10) -#define CCM_CSCDR1 (ccm_base + 0x14) -#define CCM_CSCDR2 (ccm_base + 0x18) -#define CCM_CSCDR3 (ccm_base + 0x1c) -#define CCM_CSCMR2 (ccm_base + 0x20) -#define CCM_CSCDR4 (ccm_base + 0x24) -#define CCM_CLPCR (ccm_base + 0x2c) -#define CCM_CISR (ccm_base + 0x30) -#define CCM_CIMR (ccm_base + 0x34) -#define CCM_CGPR (ccm_base + 0x3c) -#define CCM_CCGR0 (ccm_base + 0x40) -#define CCM_CCGR1 (ccm_base + 0x44) -#define CCM_CCGR2 (ccm_base + 0x48) -#define CCM_CCGR3 (ccm_base + 0x4c) -#define CCM_CCGR4 (ccm_base + 0x50) -#define CCM_CCGR5 (ccm_base + 0x54) -#define CCM_CCGR6 (ccm_base + 0x58) -#define CCM_CCGR7 (ccm_base + 0x5c) -#define CCM_CCGR8 (ccm_base + 0x60) -#define CCM_CCGR9 (ccm_base + 0x64) -#define CCM_CCGR10 (ccm_base + 0x68) -#define CCM_CCGR11 (ccm_base + 0x6c) -#define CCM_CMEOR0 (ccm_base + 0x70) -#define CCM_CMEOR1 (ccm_base + 0x74) -#define CCM_CMEOR2 (ccm_base + 0x78) -#define CCM_CMEOR3 (ccm_base + 0x7c) -#define CCM_CMEOR4 (ccm_base + 0x80) -#define CCM_CMEOR5 (ccm_base + 0x84) -#define CCM_CPPDSR (ccm_base + 0x88) -#define CCM_CCOWR (ccm_base + 0x8c) -#define CCM_CCPGR0 (ccm_base + 0x90) -#define CCM_CCPGR1 (ccm_base + 0x94) -#define CCM_CCPGR2 (ccm_base + 0x98) -#define CCM_CCPGR3 (ccm_base + 0x9c) - -#define CCM_CCGRx_CGn(n) ((n) * 2) - -#define PFD_PLL1_BASE (anatop_base + 0x2b0) -#define PFD_PLL2_BASE (anatop_base + 0x100) -#define PFD_PLL3_BASE (anatop_base + 0xf0) - -static void __iomem *anatop_base; -static void __iomem *ccm_base; - -/* sources for multiplexer clocks, this is used multiple times */ -static const char const *fast_sels[] = { "firc", "fxosc", }; -static const char const *slow_sels[] = { "sirc_32k", "sxosc", }; -static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", }; -static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", }; -static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", }; -static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", }; -static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", }; -static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", }; -static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; -static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", }; -static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", }; -static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", }; -static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", }; -static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", }; -static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", }; -static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", }; -/* FTM counter clock source, not module clock */ -static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", }; -static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", }; - -static struct clk_div_table pll4_main_div_table[] = { - { .val = 0, .div = 1 }, - { .val = 1, .div = 2 }, - { .val = 2, .div = 6 }, - { .val = 3, .div = 8 }, - { .val = 4, .div = 10 }, - { .val = 5, .div = 12 }, - { .val = 6, .div = 14 }, - { .val = 7, .div = 16 }, - { } -}; - -static struct clk *clk[VF610_CLK_END]; -static struct clk_onecell_data clk_data; - -static void __init vf610_clocks_init(struct device_node *ccm_node) -{ - struct device_node *np; - - clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); - clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); - clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); - clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); - - clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0); - clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0); - clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0); - clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0); - - clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); - - np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop"); - anatop_base = of_iomap(np, 0); - BUG_ON(!anatop_base); - - np = ccm_node; - ccm_base = of_iomap(np, 0); - BUG_ON(!ccm_base); - - clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); - clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); - - clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1); - clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0); - clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1); - clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2); - clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3); - - clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1); - clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0); - clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1); - clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2); - clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3); - - clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1); - clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0); - clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1); - clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2); - clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3); - - clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1); - /* Enet pll: fixed 50Mhz */ - clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6); - /* pll6: default 960Mhz */ - clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1); - clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); - clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); - clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); - clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); - clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3); - clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); - clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); - - clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1); - clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock); - clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1); - - clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4)); - clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4)); - - clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); - clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); - clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2); - clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); - clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); - clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4)); - - clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4); - clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12); - clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2); - clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); - clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); - clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); - - clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10); - clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20); - clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); - clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); - clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); - clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); - - clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); - - clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); - clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); - clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); - clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); - - clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); - clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); - - clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); - clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); - clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); - clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); - - clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); - - clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); - clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28); - clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4); - clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); - - clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4); - clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29); - clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4); - clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); - - /* - * ftm_ext_clk and ftm_fix_clk are FTM timer counter's - * selectable clock sources, both use a common enable bit - * in CCM_CSCDR1, selecting "dummy" clock as parent of - * "ftm0_ext_fix" make it serve only for enable/disable. - */ - clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); - clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); - clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25); - clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); - clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); - clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26); - clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); - clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); - clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27); - clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); - clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); - clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28); - - /* ftm(n)_clk are FTM module operation clock */ - clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); - clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); - clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); - clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); - - clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); - clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); - clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); - clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); - clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); - clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); - clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); - clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); - - clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); - clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); - clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); - clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); - - clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); - clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); - clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); - clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15)); - - clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); - clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); - clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); - clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0)); - - clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); - clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); - clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); - clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1)); - - clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); - clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); - clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); - clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2)); - - clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); - clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9); - clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3); - clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); - clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); - - clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2); - clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10); - clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15)); - - clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3); - clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22); - clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2); - clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); - clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); - - clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); - clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); - clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); - clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); - - clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); - - clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0)); - clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4)); - - clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); - clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); - clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); - - clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); - clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); - - /* Add the clocks to provider list */ - clk_data.clks = clk; - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -} -CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init); diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c deleted file mode 100644 index 55bc80a00666..000000000000 --- a/arch/arm/mach-imx/clk.c +++ /dev/null @@ -1,39 +0,0 @@ -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/of.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include "clk.h" - -DEFINE_SPINLOCK(imx_ccm_lock); - -static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) -{ - struct of_phandle_args phandle; - struct clk *clk = ERR_PTR(-ENODEV); - char *path; - - path = kasprintf(GFP_KERNEL, "/clocks/%s", name); - if (!path) - return ERR_PTR(-ENOMEM); - - phandle.np = of_find_node_by_path(path); - kfree(path); - - if (phandle.np) { - clk = of_clk_get_from_provider(&phandle); - of_node_put(phandle.np); - } - return clk; -} - -struct clk * __init imx_obtain_fixed_clock( - const char *name, unsigned long rate) -{ - struct clk *clk; - - clk = imx_obtain_fixed_clock_from_dt(name); - if (IS_ERR(clk)) - clk = imx_clk_fixed(name, rate); - return clk; -} diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h deleted file mode 100644 index 0e4e8bb261b9..000000000000 --- a/arch/arm/mach-imx/clk.h +++ /dev/null @@ -1,102 +0,0 @@ -#ifndef __MACH_IMX_CLK_H -#define __MACH_IMX_CLK_H - -#include <linux/spinlock.h> -#include <linux/clk-provider.h> - -extern spinlock_t imx_ccm_lock; - -struct clk *imx_clk_pllv1(const char *name, const char *parent, - void __iomem *base); - -struct clk *imx_clk_pllv2(const char *name, const char *parent, - void __iomem *base); - -enum imx_pllv3_type { - IMX_PLLV3_GENERIC, - IMX_PLLV3_SYS, - IMX_PLLV3_USB, - IMX_PLLV3_AV, - IMX_PLLV3_ENET, -}; - -struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, - const char *parent_name, void __iomem *base, u32 div_mask); - -struct clk *clk_register_gate2(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - void __iomem *reg, u8 bit_idx, - u8 clk_gate_flags, spinlock_t *lock); - -struct clk * imx_obtain_fixed_clock( - const char *name, unsigned long rate); - -static inline struct clk *imx_clk_gate2(const char *name, const char *parent, - void __iomem *reg, u8 shift) -{ - return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, - shift, 0, &imx_ccm_lock); -} - -struct clk *imx_clk_pfd(const char *name, const char *parent_name, - void __iomem *reg, u8 idx); - -struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, - void __iomem *reg, u8 shift, u8 width, - void __iomem *busy_reg, u8 busy_shift); - -struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, - u8 width, void __iomem *busy_reg, u8 busy_shift, - const char **parent_names, int num_parents); - -static inline struct clk *imx_clk_fixed(const char *name, int rate) -{ - return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); -} - -static inline struct clk *imx_clk_divider(const char *name, const char *parent, - void __iomem *reg, u8 shift, u8 width) -{ - return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, - reg, shift, width, 0, &imx_ccm_lock); -} - -static inline struct clk *imx_clk_divider_flags(const char *name, - const char *parent, void __iomem *reg, u8 shift, u8 width, - unsigned long flags) -{ - return clk_register_divider(NULL, name, parent, flags, - reg, shift, width, 0, &imx_ccm_lock); -} - -static inline struct clk *imx_clk_gate(const char *name, const char *parent, - void __iomem *reg, u8 shift) -{ - return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, - shift, 0, &imx_ccm_lock); -} - -static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, - u8 shift, u8 width, const char **parents, int num_parents) -{ - return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift, - width, 0, &imx_ccm_lock); -} - -static inline struct clk *imx_clk_mux_flags(const char *name, - void __iomem *reg, u8 shift, u8 width, const char **parents, - int num_parents, unsigned long flags) -{ - return clk_register_mux(NULL, name, parents, num_parents, - flags, reg, shift, width, 0, - &imx_ccm_lock); -} - -static inline struct clk *imx_clk_fixed_factor(const char *name, - const char *parent, unsigned int mult, unsigned int div) -{ - return clk_register_fixed_factor(NULL, name, parent, - CLK_SET_RATE_PARENT, mult, div); -} - -#endif diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index cb6c838b63ed..45c1a2a7b35f 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -1,86 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ #ifndef __ASM_ARCH_MXC_COMMON_H__ #define __ASM_ARCH_MXC_COMMON_H__ #include <linux/reboot.h> +struct irq_data; struct platform_device; struct pt_regs; struct clk; +struct device_node; enum mxc_cpu_pwr_mode; - -extern void mx1_map_io(void); -extern void mx21_map_io(void); -extern void mx25_map_io(void); -extern void mx27_map_io(void); -extern void mx31_map_io(void); -extern void mx35_map_io(void); -extern void mx51_map_io(void); -extern void mx53_map_io(void); -extern void imx1_init_early(void); -extern void imx21_init_early(void); -extern void imx25_init_early(void); -extern void imx27_init_early(void); -extern void imx31_init_early(void); -extern void imx35_init_early(void); -extern void imx51_init_early(void); -extern void imx53_init_early(void); -extern void mxc_init_irq(void __iomem *); -extern void tzic_init_irq(void __iomem *); -extern void mx1_init_irq(void); -extern void mx21_init_irq(void); -extern void mx25_init_irq(void); -extern void mx27_init_irq(void); -extern void mx31_init_irq(void); -extern void mx35_init_irq(void); -extern void mx51_init_irq(void); -extern void mx53_init_irq(void); -extern void imx1_soc_init(void); -extern void imx21_soc_init(void); -extern void imx25_soc_init(void); -extern void imx27_soc_init(void); -extern void imx31_soc_init(void); -extern void imx35_soc_init(void); -extern void imx51_soc_init(void); -extern void imx51_init_late(void); -extern void imx53_init_late(void); -extern void epit_timer_init(void __iomem *base, int irq); -extern void mxc_timer_init(void __iomem *, int); -extern int mx1_clocks_init(unsigned long fref); -extern int mx21_clocks_init(unsigned long lref, unsigned long fref); -extern int mx25_clocks_init(void); -extern int mx27_clocks_init(unsigned long fref); -extern int mx31_clocks_init(unsigned long fref); -extern int mx35_clocks_init(void); -extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); -extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, - unsigned long ckih1, unsigned long ckih2); -extern int mx25_clocks_init_dt(void); -extern int mx27_clocks_init_dt(void); -extern int mx31_clocks_init_dt(void); -extern int mx51_clocks_init_dt(void); -extern int mx53_clocks_init_dt(void); -extern struct platform_device *mxc_register_gpio(char *name, int id, - resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); -extern void mxc_set_cpu_type(unsigned int type); -extern void mxc_restart(enum reboot_mode, const char *); -extern void mxc_arch_reset_init(void __iomem *); -extern void mxc_arch_reset_init_dt(void); -extern int mx53_revision(void); -extern int imx6q_revision(void); -extern int mx53_display_revision(void); -extern void imx_set_aips(void __iomem *); -extern int mxc_device_init(void); +struct of_device_id; + +void mx31_map_io(void); +void mx35_map_io(void); +void imx21_init_early(void); +void imx31_init_early(void); +void imx35_init_early(void); +void mx31_init_irq(void); +void mx35_init_irq(void); +void mxc_set_cpu_type(unsigned int type); +void mxc_restart(enum reboot_mode, const char *); +void mxc_arch_reset_init(void __iomem *); +void imx1_reset_init(void __iomem *); +void imx_set_aips(void __iomem *); +void imx_aips_allow_unprivileged_access(const char *compat); +int mxc_device_init(void); +void imx_set_soc_revision(unsigned int rev); +void imx_init_revision_from_anatop(void); +void imx6_enable_rbc(bool enable); +void imx_gpc_check_dt(void); +void imx_gpc_set_arm_power_in_lpm(bool power_off); +void imx_gpc_set_l2_mem_power_in_lpm(bool power_off); +void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw); +void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw); +void imx25_pm_init(void); +void imx27_pm_init(void); +void imx5_pmu_init(void); enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ @@ -90,77 +51,89 @@ enum mxc_cpu_pwr_mode { STOP_POWER_OFF, /* STOP + SRPG */ }; -enum mx3_cpu_pwr_mode { - MX3_RUN, - MX3_WAIT, - MX3_DOZE, - MX3_SLEEP, +enum ulp_cpu_pwr_mode { + ULP_PM_HSRUN, /* High speed run mode */ + ULP_PM_RUN, /* Run mode */ + ULP_PM_WAIT, /* Wait mode */ + ULP_PM_STOP, /* Stop mode */ + ULP_PM_VLPS, /* Very low power stop mode */ + ULP_PM_VLLS, /* very low leakage stop mode */ }; -extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); -extern void imx_print_silicon_rev(const char *cpu, int srev); - -void avic_handle_irq(struct pt_regs *); -void tzic_handle_irq(struct pt_regs *); - -#define imx1_handle_irq avic_handle_irq -#define imx21_handle_irq avic_handle_irq -#define imx25_handle_irq avic_handle_irq -#define imx27_handle_irq avic_handle_irq -#define imx31_handle_irq avic_handle_irq -#define imx35_handle_irq avic_handle_irq -#define imx51_handle_irq tzic_handle_irq -#define imx53_handle_irq tzic_handle_irq - -extern void imx_enable_cpu(int cpu, bool enable); -extern void imx_set_cpu_jump(int cpu, void *jump_addr); -extern u32 imx_get_cpu_arg(int cpu); -extern void imx_set_cpu_arg(int cpu, u32 arg); -extern void v7_cpu_resume(void); +void imx_enable_cpu(int cpu, bool enable); +void imx_set_cpu_jump(int cpu, void *jump_addr); +u32 imx_get_cpu_arg(int cpu); +void imx_set_cpu_arg(int cpu, u32 arg); #ifdef CONFIG_SMP -extern void v7_secondary_startup(void); -extern void imx_scu_map_io(void); -extern void imx_smp_prepare(void); -extern void imx_scu_standby_enable(void); +void v7_secondary_startup(void); +void imx_scu_map_io(void); +void imx_smp_prepare(void); #else static inline void imx_scu_map_io(void) {} static inline void imx_smp_prepare(void) {} -static inline void imx_scu_standby_enable(void) {} #endif -extern void imx_src_init(void); -extern void imx_src_prepare_restart(void); -extern void imx_gpc_init(void); -extern void imx_gpc_pre_suspend(void); -extern void imx_gpc_post_resume(void); -extern void imx_gpc_mask_all(void); -extern void imx_gpc_restore_all(void); -extern void imx_anatop_init(void); -extern void imx_anatop_pre_suspend(void); -extern void imx_anatop_post_resume(void); -extern void imx_anatop_usb_chrg_detect_disable(void); -extern u32 imx_anatop_get_digprog(void); -extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_set_chicken_bit(void); - -extern void imx_cpu_die(unsigned int cpu); -extern int imx_cpu_kill(unsigned int cpu); +void imx_src_init(void); +void imx7_src_init(void); +void imx_gpc_pre_suspend(bool arm_power_off); +void imx_gpc_post_resume(void); +void imx_gpc_mask_all(void); +void imx_gpc_restore_all(void); +void imx_gpc_hwirq_mask(unsigned int hwirq); +void imx_gpc_hwirq_unmask(unsigned int hwirq); +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn); +void imx_anatop_init(void); +void imx_anatop_pre_suspend(void); +void imx_anatop_post_resume(void); +int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); +void imx6_set_int_mem_clk_lpm(bool enable); +int imx_mmdc_get_ddr_type(void); +int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode); + +void imx_cpu_die(unsigned int cpu); +int imx_cpu_kill(unsigned int cpu); + +#ifdef CONFIG_SUSPEND +void imx53_suspend(void __iomem *ocram_vbase); +extern const u32 imx53_suspend_sz; +void imx6_suspend(void __iomem *ocram_vbase); +#else +static inline void imx53_suspend(void __iomem *ocram_vbase) {} +static __maybe_unused const u32 imx53_suspend_sz; +static inline void imx6_suspend(void __iomem *ocram_vbase) {} +#endif + +void v7_cpu_resume(void); + +void imx6_pm_ccm_init(const char *ccm_compat); +void imx6q_pm_init(void); +void imx6dl_pm_init(void); +void imx6sl_pm_init(void); +void imx6sx_pm_init(void); +void imx6ul_pm_init(void); +void imx7ulp_pm_init(void); #ifdef CONFIG_PM -extern void imx6q_pm_init(void); -extern void imx51_pm_init(void); -extern void imx53_pm_init(void); +void imx51_pm_init(void); +void imx53_pm_init(void); #else -static inline void imx6q_pm_init(void) {} static inline void imx51_pm_init(void) {} static inline void imx53_pm_init(void) {} #endif #ifdef CONFIG_NEON -extern int mx51_neon_fixup(void); +int mx51_neon_fixup(void); #else static inline int mx51_neon_fixup(void) { return 0; } #endif -extern struct smp_operations imx_smp_ops; +#ifdef CONFIG_CACHE_L2X0 +void imx_init_l2cache(void); +#else +static inline void imx_init_l2cache(void) {} +#endif + +extern const struct smp_operations imx_smp_ops; +extern const struct smp_operations imx7_smp_ops; +extern const struct smp_operations ls1021a_smp_ops; #endif diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c index 96ec64b5ff7d..cc86977d0a34 100644 --- a/arch/arm/mach-imx/cpu-imx25.c +++ b/arch/arm/mach-imx/cpu-imx25.c @@ -1,16 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * MX25 CPU type detection * * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #include <linux/module.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> #include "iim.h" #include "hardware.h" @@ -20,13 +18,23 @@ static int mx25_cpu_rev = -1; static int mx25_read_cpu_rev(void) { u32 rev; + void __iomem *iim_base; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx25-iim"); + iim_base = of_iomap(np, 0); + of_node_put(np); + BUG_ON(!iim_base); + rev = readl(iim_base + MXC_IIMSREV); + iounmap(iim_base); - rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); switch (rev) { case 0x00: return IMX_CHIP_REVISION_1_0; case 0x01: return IMX_CHIP_REVISION_1_1; + case 0x02: + return IMX_CHIP_REVISION_1_2; default: return IMX_CHIP_REVISION_UNKNOWN; } diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index fe8d36f7e30e..1d2893908368 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -1,20 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ /* @@ -22,6 +9,7 @@ */ #include <linux/io.h> +#include <linux/of_address.h> #include <linux/module.h> #include "hardware.h" @@ -30,17 +18,24 @@ static int mx27_cpu_rev = -1; static int mx27_cpu_partnumber; #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ +#define SYSCTRL_OFFSET 0x800 /* Offset from CCM base address */ static int mx27_read_cpu_rev(void) { + void __iomem *ccm_base; + struct device_node *np; u32 val; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); + ccm_base = of_iomap(np, 0); + of_node_put(np); + BUG_ON(!ccm_base); /* * now we have access to the IO registers. As we need * the silicon revision very early we read it here to * avoid any further hooks */ - val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR - + SYS_CHIP_ID)); + val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID); mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c index fde1860a2521..35c544924e50 100644 --- a/arch/arm/mach-imx/cpu-imx31.c +++ b/arch/arm/mach-imx/cpu-imx31.c @@ -1,15 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * MX31 CPU type detection * * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #include <linux/module.h> +#include <linux/of_address.h> #include <linux/io.h> #include "common.h" @@ -36,10 +33,17 @@ static struct { static int mx31_read_cpu_rev(void) { + void __iomem *iim_base; + struct device_node *np; u32 i, srev; + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim"); + iim_base = of_iomap(np, 0); + of_node_put(np); + BUG_ON(!iim_base); + /* read SREV register from IIM module */ - srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); + srev = imx_readl(iim_base + MXC_IIMSREV); srev &= 0xff; for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c index ec3aaa098c17..1fe75b39c2d9 100644 --- a/arch/arm/mach-imx/cpu-imx35.c +++ b/arch/arm/mach-imx/cpu-imx35.c @@ -1,14 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * MX35 CPU type detection * * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #include <linux/module.h> +#include <linux/of_address.h> #include <linux/io.h> #include "hardware.h" @@ -18,9 +15,16 @@ static int mx35_cpu_rev = -1; static int mx35_read_cpu_rev(void) { + void __iomem *iim_base; + struct device_node *np; u32 rev; - rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); + np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim"); + iim_base = of_iomap(np, 0); + of_node_put(np); + BUG_ON(!iim_base); + + rev = imx_readl(iim_base + MXC_IIMSREV); switch (rev) { case 0x00: return IMX_CHIP_REVISION_1_0; diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index c1c99a72c6a1..a67c89bf155d 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -1,13 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * * This file contains the CPU initialization code. */ @@ -16,6 +10,8 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> #include "hardware.h" #include "common.h" @@ -24,10 +20,27 @@ static int mx5_cpu_rev = -1; #define IIM_SREV 0x24 +static u32 imx5_read_srev_reg(const char *compat) +{ + void __iomem *iim_base; + struct device_node *np; + u32 srev; + + np = of_find_compatible_node(NULL, NULL, compat); + iim_base = of_iomap(np, 0); + of_node_put(np); + WARN_ON(!iim_base); + + srev = readl(iim_base + IIM_SREV) & 0xff; + + iounmap(iim_base); + + return srev; +} + static int get_mx51_srev(void) { - void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); - u32 rev = readl(iim_base + IIM_SREV) & 0xff; + u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); switch (rev) { case 0x0: @@ -42,13 +55,9 @@ static int get_mx51_srev(void) /* * Returns: * the silicon revision of the cpu - * -EINVAL - not a mx51 */ int mx51_revision(void) { - if (!cpu_is_mx51()) - return -EINVAL; - if (mx5_cpu_rev == -1) mx5_cpu_rev = get_mx51_srev(); @@ -77,8 +86,7 @@ int __init mx51_neon_fixup(void) static int get_mx53_srev(void) { - void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); - u32 rev = readl(iim_base + IIM_SREV) & 0xff; + u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); switch (rev) { case 0x0: @@ -95,16 +103,57 @@ static int get_mx53_srev(void) /* * Returns: * the silicon revision of the cpu - * -EINVAL - not a mx53 */ int mx53_revision(void) { - if (!cpu_is_mx53()) - return -EINVAL; - if (mx5_cpu_rev == -1) mx5_cpu_rev = get_mx53_srev(); return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); + +#define ARM_GPC 0x4 +#define DBGEN BIT(16) + +/* + * This enables the DBGEN bit in ARM_GPC register, which is + * required for accessing some performance counter features. + * Technically it is only required while perf is used, but to + * keep the source code simple we just enable it all the time + * when the kernel configuration allows using the feature. + */ +void __init imx5_pmu_init(void) +{ + void __iomem *tigerp_base; + struct device_node *np; + u32 gpc; + + if (!IS_ENABLED(CONFIG_ARM_PMU)) + return; + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); + if (!np) + return; + + if (!of_property_read_bool(np, "secure-reg-access")) + goto exit; + + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp"); + if (!np) + return; + + tigerp_base = of_iomap(np, 0); + if (!tigerp_base) + goto exit; + + gpc = readl_relaxed(tigerp_base + ARM_GPC); + gpc |= DBGEN; + writel_relaxed(gpc, tigerp_base + ARM_GPC); + iounmap(tigerp_base); +exit: + of_node_put(np); + +} diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index e70e3acbf9bd..65c7224f5250 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -1,18 +1,31 @@ - +// SPDX-License-Identifier: GPL-2.0 +#include <linux/err.h> #include <linux/module.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> #include "hardware.h" #include "common.h" unsigned int __mxc_cpu_type; -EXPORT_SYMBOL(__mxc_cpu_type); +static unsigned int imx_soc_revision; void mxc_set_cpu_type(unsigned int type) { __mxc_cpu_type = type; } +void imx_set_soc_revision(unsigned int rev) +{ + imx_soc_revision = rev; +} + +unsigned int imx_get_soc_revision(void) +{ + return imx_soc_revision; +} + void imx_print_silicon_rev(const char *cpu, int srev) { if (srev == IMX_CHIP_REVISION_UNKNOWN) @@ -29,18 +42,31 @@ void __init imx_set_aips(void __iomem *base) * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - __raw_writel(0x77777777, base + 0x0); - __raw_writel(0x77777777, base + 0x4); + imx_writel(0x77777777, base + 0x0); + imx_writel(0x77777777, base + 0x4); /* * Set all OPACRx to be non-bufferable, to not require * supervisor privilege level for access, allow for * write access and untrusted master access. */ - __raw_writel(0x0, base + 0x40); - __raw_writel(0x0, base + 0x44); - __raw_writel(0x0, base + 0x48); - __raw_writel(0x0, base + 0x4C); - reg = __raw_readl(base + 0x50) & 0x00FFFFFF; - __raw_writel(reg, base + 0x50); + imx_writel(0x0, base + 0x40); + imx_writel(0x0, base + 0x44); + imx_writel(0x0, base + 0x48); + imx_writel(0x0, base + 0x4C); + reg = imx_readl(base + 0x50) & 0x00FFFFFF; + imx_writel(reg, base + 0x50); +} + +void __init imx_aips_allow_unprivileged_access( + const char *compat) +{ + void __iomem *aips_base_addr; + struct device_node *np; + + for_each_compatible_node(np, NULL, compat) { + aips_base_addr = of_iomap(np, 0); + WARN_ON(!aips_base_addr); + imx_set_aips(aips_base_addr); + } } diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c index 5a47e3c6172f..5ad9f2f533cd 100644 --- a/arch/arm/mach-imx/cpuidle-imx5.c +++ b/arch/arm/mach-imx/cpuidle-imx5.c @@ -1,17 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/cpuidle.h> #include <linux/module.h> #include <asm/system_misc.h> +#include "cpuidle.h" -static int imx5_cpuidle_enter(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) +static __cpuidle int imx5_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) { arm_pm_idle(); return index; @@ -24,7 +22,6 @@ static struct cpuidle_driver imx5_cpuidle_driver = { .enter = imx5_cpuidle_enter, .exit_latency = 2, .target_residency = 1, - .flags = CPUIDLE_FLAG_TIME_VALID, .name = "IMX5 SRPG", .desc = "CPU state retained,powered off", }, diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c index 23ddfb693b2d..2b0d3160f993 100644 --- a/arch/arm/mach-imx/cpuidle-imx6q.c +++ b/arch/arm/mach-imx/cpuidle-imx6q.c @@ -1,43 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ +#include <linux/context_tracking.h> #include <linux/cpuidle.h> #include <linux/module.h> #include <asm/cpuidle.h> -#include <asm/proc-fns.h> + +#include <soc/imx/cpuidle.h> #include "common.h" #include "cpuidle.h" +#include "hardware.h" -static atomic_t master = ATOMIC_INIT(0); -static DEFINE_SPINLOCK(master_lock); +static int num_idle_cpus = 0; +static DEFINE_RAW_SPINLOCK(cpuidle_lock); -static int imx6q_enter_wait(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) +static __cpuidle int imx6q_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) { - if (atomic_inc_return(&master) == num_online_cpus()) { - /* - * With this lock, we prevent other cpu to exit and enter - * this function again and become the master. - */ - if (!spin_trylock(&master_lock)) - goto idle; - imx6q_set_lpm(WAIT_UNCLOCKED); - cpu_do_idle(); - imx6q_set_lpm(WAIT_CLOCKED); - spin_unlock(&master_lock); - goto done; - } + raw_spin_lock(&cpuidle_lock); + if (++num_idle_cpus == num_online_cpus()) + imx6_set_lpm(WAIT_UNCLOCKED); + raw_spin_unlock(&cpuidle_lock); -idle: + ct_cpuidle_enter(); cpu_do_idle(); -done: - atomic_dec(&master); + ct_cpuidle_exit(); + + raw_spin_lock(&cpuidle_lock); + if (num_idle_cpus-- == num_online_cpus()) + imx6_set_lpm(WAIT_CLOCKED); + raw_spin_unlock(&cpuidle_lock); return index; } @@ -52,8 +47,7 @@ static struct cpuidle_driver imx6q_cpuidle_driver = { { .exit_latency = 50, .target_residency = 75, - .flags = CPUIDLE_FLAG_TIME_VALID | - CPUIDLE_FLAG_TIMER_STOP, + .flags = CPUIDLE_FLAG_TIMER_STOP | CPUIDLE_FLAG_RCU_IDLE, .enter = imx6q_enter_wait, .name = "WAIT", .desc = "Clock off", @@ -63,13 +57,28 @@ static struct cpuidle_driver imx6q_cpuidle_driver = { .safe_state_index = 0, }; -int __init imx6q_cpuidle_init(void) +/* + * i.MX6 Q/DL has an erratum (ERR006687) that prevents the FEC from waking the + * CPUs when they are in wait(unclocked) state. As the hardware workaround isn't + * applicable to all boards, disable the deeper idle state when the workaround + * isn't present and the FEC is in use. + */ +void imx6q_cpuidle_fec_irqs_used(void) { - /* Need to enable SCU standby for entering WAIT modes */ - imx_scu_standby_enable(); + cpuidle_driver_state_disabled(&imx6q_cpuidle_driver, 1, true); +} +EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_used); - /* Set chicken bit to get a reliable WAIT mode support */ - imx6q_set_chicken_bit(); +void imx6q_cpuidle_fec_irqs_unused(void) +{ + cpuidle_driver_state_disabled(&imx6q_cpuidle_driver, 1, false); +} +EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused); + +int __init imx6q_cpuidle_init(void) +{ + /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */ + imx6_set_int_mem_clk_lpm(true); return cpuidle_register(&imx6q_cpuidle_driver, NULL); } diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c new file mode 100644 index 000000000000..b49cd6302dce --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#include <linux/clk/imx.h> +#include <linux/cpuidle.h> +#include <linux/module.h> +#include <asm/cpuidle.h> + +#include "common.h" +#include "cpuidle.h" + +static __cpuidle int imx6sl_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + imx6_set_lpm(WAIT_UNCLOCKED); + /* + * Software workaround for ERR005311, see function + * description for details. + */ + imx6sl_set_wait_clk(true); + cpu_do_idle(); + imx6sl_set_wait_clk(false); + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sl_cpuidle_driver = { + .name = "imx6sl_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = imx6sl_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + }, + .state_count = 2, + .safe_state_index = 0, +}; + +int __init imx6sl_cpuidle_init(void) +{ + return cpuidle_register(&imx6sl_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c new file mode 100644 index 000000000000..83c5cbd3748e --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + */ + +#include <linux/cpuidle.h> +#include <linux/cpu_pm.h> +#include <linux/module.h> +#include <asm/cacheflush.h> +#include <asm/cpuidle.h> +#include <asm/suspend.h> + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +static int imx6sx_idle_finish(unsigned long val) +{ + /* + * for Cortex-A7 which has an internal L2 + * cache, need to flush it before powering + * down ARM platform, since flushing L1 cache + * here again has very small overhead, compared + * to adding conditional code for L2 cache type, + * just call flush_cache_all() is fine. + */ + flush_cache_all(); + cpu_do_idle(); + + return 0; +} + +static __cpuidle int imx6sx_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + imx6_set_lpm(WAIT_UNCLOCKED); + + switch (index) { + case 1: + cpu_do_idle(); + break; + case 2: + imx6_enable_rbc(true); + imx_gpc_set_arm_power_in_lpm(true); + imx_set_cpu_jump(0, v7_cpu_resume); + /* Need to notify there is a cpu pm operation. */ + cpu_pm_enter(); + cpu_cluster_pm_enter(); + + ct_cpuidle_enter(); + cpu_suspend(0, imx6sx_idle_finish); + ct_cpuidle_exit(); + + cpu_cluster_pm_exit(); + cpu_pm_exit(); + imx_gpc_set_arm_power_in_lpm(false); + imx6_enable_rbc(false); + break; + default: + break; + } + + imx6_set_lpm(WAIT_CLOCKED); + + return index; +} + +static struct cpuidle_driver imx6sx_cpuidle_driver = { + .name = "imx6sx_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .flags = CPUIDLE_FLAG_TIMER_STOP, + .enter = imx6sx_enter_wait, + .name = "WAIT", + .desc = "Clock off", + }, + /* WAIT + ARM power off */ + { + /* + * ARM gating 31us * 5 + RBC clear 65us + * and some margin for SW execution, here set it + * to 300us. + */ + .exit_latency = 300, + .target_residency = 500, + .flags = CPUIDLE_FLAG_TIMER_STOP | + CPUIDLE_FLAG_RCU_IDLE, + .enter = imx6sx_enter_wait, + .name = "LOW-POWER-IDLE", + .desc = "ARM power off", + }, + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx6sx_cpuidle_init(void) +{ + imx6_set_int_mem_clk_lpm(true); + imx6_enable_rbc(false); + imx_gpc_set_l2_mem_power_in_lpm(false); + /* + * set ARM power up/down timing to the fastest, + * sw2iso and sw can be set to one 32K cycle = 31us + * except for power up sw2iso which need to be + * larger than LDO ramp up time. + */ + imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1); + imx_gpc_set_arm_power_down_timing(1, 1); + + return cpuidle_register(&imx6sx_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c b/arch/arm/mach-imx/cpuidle-imx7ulp.c new file mode 100644 index 000000000000..f55ed74acfae --- /dev/null +++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Anson Huang <Anson.Huang@nxp.com> + */ + +#include <linux/cpuidle.h> +#include <linux/module.h> +#include <asm/cpuidle.h> + +#include "common.h" +#include "cpuidle.h" + +static __cpuidle int imx7ulp_enter_wait(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + if (index == 1) + imx7ulp_set_lpm(ULP_PM_WAIT); + else + imx7ulp_set_lpm(ULP_PM_STOP); + + cpu_do_idle(); + + imx7ulp_set_lpm(ULP_PM_RUN); + + return index; +} + +static struct cpuidle_driver imx7ulp_cpuidle_driver = { + .name = "imx7ulp_cpuidle", + .owner = THIS_MODULE, + .states = { + /* WFI */ + ARM_CPUIDLE_WFI_STATE, + /* WAIT */ + { + .exit_latency = 50, + .target_residency = 75, + .enter = imx7ulp_enter_wait, + .name = "WAIT", + .desc = "PSTOP2", + }, + /* STOP */ + { + .exit_latency = 100, + .target_residency = 150, + .enter = imx7ulp_enter_wait, + .name = "STOP", + .desc = "PSTOP1", + }, + }, + .state_count = 3, + .safe_state_index = 0, +}; + +int __init imx7ulp_cpuidle_init(void) +{ + return cpuidle_register(&imx7ulp_cpuidle_driver, NULL); +} diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h index 786f98ecc145..ce552c096cae 100644 --- a/arch/arm/mach-imx/cpuidle.h +++ b/arch/arm/mach-imx/cpuidle.h @@ -1,18 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2012 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #ifdef CONFIG_CPU_IDLE extern int imx5_cpuidle_init(void); extern int imx6q_cpuidle_init(void); +extern int imx6sl_cpuidle_init(void); +extern int imx6sx_cpuidle_init(void); +extern int imx7ulp_cpuidle_init(void); #else static inline int imx5_cpuidle_init(void) { @@ -22,4 +19,16 @@ static inline int imx6q_cpuidle_init(void) { return 0; } +static inline int imx6sl_cpuidle_init(void) +{ + return 0; +} +static inline int imx6sx_cpuidle_init(void) +{ + return 0; +} +static inline int imx7ulp_cpuidle_init(void) +{ + return 0; +} #endif diff --git a/arch/arm/mach-imx/crm-regs-imx5.h b/arch/arm/mach-imx/crm-regs-imx5.h deleted file mode 100644 index 5e3f1f0f4cab..000000000000 --- a/arch/arm/mach-imx/crm-regs-imx5.h +++ /dev/null @@ -1,600 +0,0 @@ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) -#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) -#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) -#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) -#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) -#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) - -/*MX53*/ -#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) -#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) -#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) -#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) -#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR) - -/* PLL Register Offsets */ -#define MXC_PLL_DP_CTL 0x00 -#define MXC_PLL_DP_CONFIG 0x04 -#define MXC_PLL_DP_OP 0x08 -#define MXC_PLL_DP_MFD 0x0C -#define MXC_PLL_DP_MFN 0x10 -#define MXC_PLL_DP_MFNMINUS 0x14 -#define MXC_PLL_DP_MFNPLUS 0x18 -#define MXC_PLL_DP_HFS_OP 0x1C -#define MXC_PLL_DP_HFS_MFD 0x20 -#define MXC_PLL_DP_HFS_MFN 0x24 -#define MXC_PLL_DP_MFN_TOGC 0x28 -#define MXC_PLL_DP_DESTAT 0x2c - -/* PLL Register Bit definitions */ -#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 -#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 -#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 -#define MXC_PLL_DP_CTL_ADE 0x800 -#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 -#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) -#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 -#define MXC_PLL_DP_CTL_HFSM 0x80 -#define MXC_PLL_DP_CTL_PRE 0x40 -#define MXC_PLL_DP_CTL_UPEN 0x20 -#define MXC_PLL_DP_CTL_RST 0x10 -#define MXC_PLL_DP_CTL_RCP 0x8 -#define MXC_PLL_DP_CTL_PLM 0x4 -#define MXC_PLL_DP_CTL_BRM0 0x2 -#define MXC_PLL_DP_CTL_LRF 0x1 - -#define MXC_PLL_DP_CONFIG_BIST 0x8 -#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 -#define MXC_PLL_DP_CONFIG_AREN 0x2 -#define MXC_PLL_DP_CONFIG_LDREQ 0x1 - -#define MXC_PLL_DP_OP_MFI_OFFSET 4 -#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) -#define MXC_PLL_DP_OP_PDF_OFFSET 0 -#define MXC_PLL_DP_OP_PDF_MASK 0xF - -#define MXC_PLL_DP_MFD_OFFSET 0 -#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF - -#define MXC_PLL_DP_MFN_OFFSET 0x0 -#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF - -#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) -#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) -#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 -#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF - -#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) -#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF - -/* Register addresses of CCM*/ -#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) -#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) -#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) -#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) -#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) -#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) -#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) -#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) -#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) -#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) -#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) -#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) -#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) -#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) -#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) -#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) -#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) -#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) -#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) -#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) -#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) -#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) -#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) -#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) -#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) -#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) -#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) -#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) -#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) -#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) -#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) -#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) -#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) -#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84) - -#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) - -/* Define the bits in register CCR */ -#define MXC_CCM_CCR_COSC_EN (1 << 12) -#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) -#define MXC_CCM_CCR_CAMP2_EN (1 << 10) -#define MXC_CCM_CCR_CAMP1_EN (1 << 9) -#define MXC_CCM_CCR_FPM_EN (1 << 8) -#define MXC_CCM_CCR_OSCNT_OFFSET (0) -#define MXC_CCM_CCR_OSCNT_MASK (0xFF) - -/* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) -#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) -#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) - -/* Define the bits in register CSR */ -#define MXC_CCM_CSR_COSR_READY (1 << 5) -#define MXC_CCM_CSR_LVS_VALUE (1 << 4) -#define MXC_CCM_CSR_CAMP2_READY (1 << 3) -#define MXC_CCM_CSR_CAMP1_READY (1 << 2) -#define MXC_CCM_CSR_FPM_READY (1 << 1) -#define MXC_CCM_CSR_REF_EN_B (1 << 0) - -/* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) -#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) -#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) -#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 -#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ -#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 -#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 -#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) -#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) -#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) -#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) -#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, - 1: step_clk */ -#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) -#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) -#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) -#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) -#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) -#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) -#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) -#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) -#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) -#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) -#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) - -/* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) -#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) -#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) -#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) -#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) -#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) -#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) -#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) -#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) -#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) -#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) -#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) -#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) -#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) -#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) -#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) - -/* Define the bits in register CS1CDR and CS2CDR */ -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) - -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) -#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CDCDR */ -#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) -#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) -#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) -#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) -#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) -#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) - -/* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) -#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) -#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) -#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) -#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) - -/* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CSCDR4 */ -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) -#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) -#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) - -/* Define the bits in register CDHIPR */ -#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) -#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) -#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) -#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) -#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) -#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) -#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) -#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) -#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) - -/* Define the bits in register CDCR */ -#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) -#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) -#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) - -/* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) -#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) -#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) -#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) -#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) -#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) -#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) -#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) -#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) -#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) -#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) -#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) -#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) -#define MXC_CCM_CLPCR_LPM_OFFSET (0) -#define MXC_CCM_CLPCR_LPM_MASK (0x3) - -/* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) -#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) -#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) -#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) -#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) -#define MXC_CCM_CISR_COSC_READY (0x1 << 6) -#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) -#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) -#define MXC_CCM_CISR_FPM_READY (0x1 << 3) -#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) -#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) -#define MXC_CCM_CISR_LRF_PLL1 (0x1) - -/* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) -#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) -#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) -#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) -#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) -#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) -#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) -#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) -#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) -#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) -#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) - -/* Define the bits in register CCOSR */ -#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) -#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) -#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) -#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) -#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) - -/* Define the bits in registers CGPR */ -#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) -#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) -#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) -#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) - -/* Define the bits in registers CCGRx */ -#define MXC_CCM_CCGRx_CG_MASK 0x3 -#define MXC_CCM_CCGRx_MOD_OFF 0x0 -#define MXC_CCM_CCGRx_MOD_ON 0x3 -#define MXC_CCM_CCGRx_MOD_IDLE 0x1 - -#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) -#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) -#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) -#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) -#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) -#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) -#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) -#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) -#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) -#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) -#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) -#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) -#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) -#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) - -#define MXC_CCM_CCGRx_CG15_OFFSET 30 -#define MXC_CCM_CCGRx_CG14_OFFSET 28 -#define MXC_CCM_CCGRx_CG13_OFFSET 26 -#define MXC_CCM_CCGRx_CG12_OFFSET 24 -#define MXC_CCM_CCGRx_CG11_OFFSET 22 -#define MXC_CCM_CCGRx_CG10_OFFSET 20 -#define MXC_CCM_CCGRx_CG9_OFFSET 18 -#define MXC_CCM_CCGRx_CG8_OFFSET 16 -#define MXC_CCM_CCGRx_CG7_OFFSET 14 -#define MXC_CCM_CCGRx_CG6_OFFSET 12 -#define MXC_CCM_CCGRx_CG5_OFFSET 10 -#define MXC_CCM_CCGRx_CG4_OFFSET 8 -#define MXC_CCM_CCGRx_CG3_OFFSET 6 -#define MXC_CCM_CCGRx_CG2_OFFSET 4 -#define MXC_CCM_CCGRx_CG1_OFFSET 2 -#define MXC_CCM_CCGRx_CG0_OFFSET 0 - -#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) -#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) -#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) -#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) -#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) -#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) -#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) -#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) -#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) -#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) -#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) -#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) -#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) - -/* CORTEXA8 platform */ -#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) - -/* DVFS CORE */ -#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) -#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) -#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) -#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) -#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) -#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) -#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) -#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) -#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) -#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) -#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) -#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) -#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) -#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) -#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) -#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) -#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) - -/* GPC */ -#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) -#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) -#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) -#define MXC_GPC_PGR_ARMPG_OFFSET 8 -#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) - -/* PGC */ -#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) -#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) -#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) -#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) -#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) -#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) - -#define MXC_PGCR_PCR 1 -#define MXC_SRPGCR_PCR 1 -#define MXC_EMPGCR_PCR 1 -#define MXC_PGSR_PSR 1 - - -#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) -#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) - -/* SRPG */ -#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) -#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) -#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) - -#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) -#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) -#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) - -#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) -#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) -#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) - -#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) -#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) -#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) - -#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) -#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) -#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) - -#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) -#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) -#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/mach-imx/crmregs-imx3.h b/arch/arm/mach-imx/crmregs-imx3.h index a1dfde53e335..3e6951eee51c 100644 --- a/arch/arm/mach-imx/crmregs-imx3.h +++ b/arch/arm/mach-imx/crmregs-imx3.h @@ -1,20 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h deleted file mode 100644 index f9b5afc6bcd1..000000000000 --- a/arch/arm/mach-imx/devices-imx1.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_imx_fb_data imx1_imx_fb_data; -#define imx1_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx1_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx1_imx_i2c_data; -#define imx1_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) - -extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[]; -#define imx1_add_imx_uart(id, pdata) \ - imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) -#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) -#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) - -extern const struct imx_spi_imx_data imx1_cspi_data[]; -#define imx1_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx1_cspi_data[id], pdata) - -#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata) -#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata) diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h deleted file mode 100644 index bd9393280159..000000000000 --- a/arch/arm/mach-imx/devices-imx21.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data; -#define imx21_add_imx21_hcd(pdata) \ - imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) - -extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; -#define imx21_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx21_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx21_imx_fb_data; -#define imx21_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx21_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx21_imx_i2c_data; -#define imx21_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) - -extern const struct imx_imx_keypad_data imx21_imx_keypad_data; -#define imx21_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx21_imx_ssi_data[]; -#define imx21_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[]; -#define imx21_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) -#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) -#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata) -#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) -#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) - -extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[]; -#define imx21_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx21_mxc_nand_data; -#define imx21_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx21_mxc_w1_data; -#define imx21_add_mxc_w1() \ - imx_add_mxc_w1(&imx21_mxc_w1_data) - -extern const struct imx_spi_imx_data imx21_cspi_data[]; -#define imx21_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx21_cspi_data[id], pdata) -#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) -#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata) diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h deleted file mode 100644 index 769563fdeaa0..000000000000 --- a/arch/arm/mach-imx/devices-imx25.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx25_fec_data; -#define imx25_add_fec(pdata) \ - imx_add_fec(&imx25_fec_data, pdata) - -extern const struct imx_flexcan_data imx25_flexcan_data[]; -#define imx25_add_flexcan(id) \ - imx_add_flexcan(&imx25_flexcan_data[id]) -#define imx25_add_flexcan0() imx25_add_flexcan(0) -#define imx25_add_flexcan1() imx25_add_flexcan(1) - -extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data; -#define imx25_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) - -extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; -#define imx25_add_imxdi_rtc() \ - imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) - -extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; -#define imx25_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx25_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx25_imx_fb_data; -#define imx25_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx25_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx25_imx_i2c_data[]; -#define imx25_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata) -#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata) -#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) -#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx25_imx_keypad_data; -#define imx25_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx25_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx25_imx_ssi_data[]; -#define imx25_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[]; -#define imx25_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata) -#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata) -#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata) -#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata) -#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) -#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) - -extern const struct imx_mx2_camera_data imx25_mx2_camera_data; -#define imx25_add_mx2_camera(pdata) \ - imx_add_mx2_camera(&imx25_mx2_camera_data, pdata) - -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data; -#define imx25_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data; -#define imx25_add_mxc_ehci_hs(pdata) \ - imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata) - -extern const struct imx_mxc_nand_data imx25_mxc_nand_data; -#define imx25_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[]; -#define imx25_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx25_cspi_data[]; -#define imx25_add_spi_imx(id, pdata) \ - imx_add_spi_imx(&imx25_cspi_data[id], pdata) -#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) -#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) -#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) - -extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[]; -#define imx25_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx25_mxc_pwm_data[id]) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h deleted file mode 100644 index 130962519751..000000000000 --- a/arch/arm/mach-imx/devices-imx27.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx27_fec_data; -#define imx27_add_fec(pdata) \ - imx_add_fec(&imx27_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; -#define imx27_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx27_coda_data imx27_coda_data; -#define imx27_add_coda() \ - imx_add_imx27_coda(&imx27_coda_data) - -extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; -#define imx27_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx27_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx27_imx_fb_data; -#define imx27_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx27_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx27_imx_i2c_data[]; -#define imx27_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) - -extern const struct imx_imx_keypad_data imx27_imx_keypad_data; -#define imx27_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx27_imx_ssi_data[]; -#define imx27_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[]; -#define imx27_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) -#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) -#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata) -#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata) -#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata) -#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) -#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) - -extern const struct imx_mx2_camera_data imx27_mx2_camera_data; -#define imx27_add_mx2_camera(pdata) \ - imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) - -extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data; -#define imx27_add_mx2_emmaprp() \ - imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data) - -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; -#define imx27_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[]; -#define imx27_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[]; -#define imx27_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx27_mxc_nand_data; -#define imx27_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx27_mxc_w1_data; -#define imx27_add_mxc_w1() \ - imx_add_mxc_w1(&imx27_mxc_w1_data) - -extern const struct imx_spi_imx_data imx27_cspi_data[]; -#define imx27_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx27_cspi_data[id], pdata) -#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata) -#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata) -#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata) - -extern const struct imx_pata_imx_data imx27_pata_imx_data; -#define imx27_add_pata_imx() \ - imx_add_pata_imx(&imx27_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h deleted file mode 100644 index e8d1611bbc8e..000000000000 --- a/arch/arm/mach-imx/devices-imx31.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data; -#define imx31_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; -#define imx31_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx31_imx2_wdt_data) - -extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; -#define imx31_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) -#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) -#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) -#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx31_imx_keypad_data; -#define imx31_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx31_imx_ssi_data[]; -#define imx31_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[]; -#define imx31_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) -#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) -#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata) -#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata) -#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) -#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) - -extern const struct imx_ipu_core_data imx31_ipu_core_data; -#define imx31_add_ipu_core() \ - imx_add_ipu_core(&imx31_ipu_core_data) -#define imx31_alloc_mx3_camera(pdata) \ - imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata) -#define imx31_add_mx3_sdc_fb(pdata) \ - imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata) - -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data; -#define imx31_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[]; -#define imx31_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[]; -#define imx31_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx31_mxc_nand_data; -#define imx31_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) - -extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; -#define imx31_add_mxc_rtc() \ - imx_add_mxc_rtc(&imx31_mxc_rtc_data) - -extern const struct imx_mxc_w1_data imx31_mxc_w1_data; -#define imx31_add_mxc_w1() \ - imx_add_mxc_w1(&imx31_mxc_w1_data) - -extern const struct imx_spi_imx_data imx31_cspi_data[]; -#define imx31_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx31_cspi_data[id], pdata) -#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata) -#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata) -#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata) - -extern const struct imx_pata_imx_data imx31_pata_imx_data; -#define imx31_add_pata_imx() \ - imx_add_pata_imx(&imx31_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h deleted file mode 100644 index 780d8240281b..000000000000 --- a/arch/arm/mach-imx/devices-imx35.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx35_fec_data; -#define imx35_add_fec(pdata) \ - imx_add_fec(&imx35_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data; -#define imx35_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) - -extern const struct imx_flexcan_data imx35_flexcan_data[]; -#define imx35_add_flexcan(id) \ - imx_add_flexcan(&imx35_flexcan_data[id]) -#define imx35_add_flexcan0() imx35_add_flexcan(0) -#define imx35_add_flexcan1() imx35_add_flexcan(1) - -extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; -#define imx35_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx35_imx2_wdt_data) - -extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; -#define imx35_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) -#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) -#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) -#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx35_imx_keypad_data; -#define imx35_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx35_imx_ssi_data[]; -#define imx35_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[]; -#define imx35_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) -#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) -#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) -#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) - -extern const struct imx_ipu_core_data imx35_ipu_core_data; -#define imx35_add_ipu_core() \ - imx_add_ipu_core(&imx35_ipu_core_data) -#define imx35_alloc_mx3_camera(pdata) \ - imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata) -#define imx35_add_mx3_sdc_fb(pdata) \ - imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata) - -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data; -#define imx35_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data; -#define imx35_add_mxc_ehci_hs(pdata) \ - imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) - -extern const struct imx_mxc_nand_data imx35_mxc_nand_data; -#define imx35_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) - -extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data; -#define imx35_add_mxc_rtc() \ - imx_add_mxc_rtc(&imx35_mxc_rtc_data) - -extern const struct imx_mxc_w1_data imx35_mxc_w1_data; -#define imx35_add_mxc_w1() \ - imx_add_mxc_w1(&imx35_mxc_w1_data) - -extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; -#define imx35_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx35_cspi_data[]; -#define imx35_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx35_cspi_data[id], pdata) -#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) -#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) - -extern const struct imx_pata_imx_data imx35_pata_imx_data; -#define imx35_add_pata_imx() \ - imx_add_pata_imx(&imx35_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h deleted file mode 100644 index deee5baee88c..000000000000 --- a/arch/arm/mach-imx/devices-imx51.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx51_fec_data; -#define imx51_add_fec(pdata) \ - imx_add_fec(&imx51_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data; -#define imx51_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx_i2c_data imx51_imx_i2c_data[]; -#define imx51_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) -#define imx51_add_hsi2c(pdata) \ - imx51_add_imx_i2c(2, pdata) - -extern const struct imx_imx_ssi_data imx51_imx_ssi_data[]; -#define imx51_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[]; -#define imx51_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) - -extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data; -#define imx51_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[]; -#define imx51_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_nand_data imx51_mxc_nand_data; -#define imx51_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) - -extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[]; -#define imx51_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx51_cspi_data; -#define imx51_add_cspi(pdata) \ - imx_add_spi_imx(&imx51_cspi_data, pdata) - -extern const struct imx_spi_imx_data imx51_ecspi_data[]; -#define imx51_add_ecspi(id, pdata) \ - imx_add_spi_imx(&imx51_ecspi_data[id], pdata) - -extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; -#define imx51_add_imx2_wdt(id) \ - imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) - -extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; -#define imx51_add_mxc_pwm(id) \ - imx_add_mxc_pwm(&imx51_mxc_pwm_data[id]) - -extern const struct imx_imx_keypad_data imx51_imx_keypad_data; -#define imx51_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx51_imx_keypad_data, pdata) - -extern const struct imx_pata_imx_data imx51_pata_imx_data; -#define imx51_add_pata_imx() \ - imx_add_pata_imx(&imx51_pata_imx_data) diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig deleted file mode 100644 index 68c74fb0373c..000000000000 --- a/arch/arm/mach-imx/devices/Kconfig +++ /dev/null @@ -1,87 +0,0 @@ -config IMX_HAVE_PLATFORM_FEC - bool - default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53 - -config IMX_HAVE_PLATFORM_FLEXCAN - bool - -config IMX_HAVE_PLATFORM_FSL_USB2_UDC - bool - -config IMX_HAVE_PLATFORM_GPIO_KEYS - bool - default y if SOC_IMX51 - -config IMX_HAVE_PLATFORM_IMX21_HCD - bool - -config IMX_HAVE_PLATFORM_IMX27_CODA - bool - default y if SOC_IMX27 - -config IMX_HAVE_PLATFORM_IMX2_WDT - bool - -config IMX_HAVE_PLATFORM_IMXDI_RTC - bool - -config IMX_HAVE_PLATFORM_IMX_FB - bool - -config IMX_HAVE_PLATFORM_IMX_I2C - bool - -config IMX_HAVE_PLATFORM_IMX_KEYPAD - bool - -config IMX_HAVE_PLATFORM_PATA_IMX - bool - -config IMX_HAVE_PLATFORM_IMX_SSI - bool - -config IMX_HAVE_PLATFORM_IMX_UART - bool - -config IMX_HAVE_PLATFORM_IMX_UDC - bool - -config IMX_HAVE_PLATFORM_IPU_CORE - bool - -config IMX_HAVE_PLATFORM_MX1_CAMERA - bool - -config IMX_HAVE_PLATFORM_MX2_CAMERA - bool - -config IMX_HAVE_PLATFORM_MX2_EMMA - bool - -config IMX_HAVE_PLATFORM_MXC_EHCI - bool - -config IMX_HAVE_PLATFORM_MXC_MMC - bool - -config IMX_HAVE_PLATFORM_MXC_NAND - bool - -config IMX_HAVE_PLATFORM_MXC_PWM - bool - -config IMX_HAVE_PLATFORM_MXC_RNGA - bool - select ARCH_HAS_RNGA - -config IMX_HAVE_PLATFORM_MXC_RTC - bool - -config IMX_HAVE_PLATFORM_MXC_W1 - bool - -config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - bool - -config IMX_HAVE_PLATFORM_SPI_IMX - bool diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile deleted file mode 100644 index 67416fb1dc69..000000000000 --- a/arch/arm/mach-imx/devices/Makefile +++ /dev/null @@ -1,32 +0,0 @@ -obj-y := devices.o - -obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o -obj-y += platform-gpio-mxc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o -obj-y += platform-imx-dma.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h deleted file mode 100644 index c13b76b9f6b3..000000000000 --- a/arch/arm/mach-imx/devices/devices-common.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/init.h> -#include <linux/platform_data/dma-imx-sdma.h> - -extern struct device mxc_aips_bus; -extern struct device mxc_ahb_bus; - -static inline struct platform_device *imx_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask) -{ - struct platform_device_info pdevinfo = { - .name = name, - .id = id, - .res = res, - .num_res = num_resources, - .data = data, - .size_data = size_data, - .dma_mask = dmamask, - }; - return platform_device_register_full(&pdevinfo); -} - -static inline struct platform_device *imx_add_platform_device( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) -{ - return imx_add_platform_device_dmamask( - name, id, res, num_resources, data, size_data, 0); -} - -#include <linux/fec.h> -struct imx_fec_data { - const char *devid; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_fec( - const struct imx_fec_data *data, - const struct fec_platform_data *pdata); - -struct imx_flexcan_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_flexcan( - const struct imx_flexcan_data *data); - -#include <linux/fsl_devices.h> -struct imx_fsl_usb2_udc_data { - const char *devid; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_fsl_usb2_udc( - const struct imx_fsl_usb2_udc_data *data, - const struct fsl_usb2_platform_data *pdata); - -#include <linux/gpio_keys.h> -struct platform_device *__init imx_add_gpio_keys( - const struct gpio_keys_platform_data *pdata); - -#include <linux/platform_data/usb-mx2.h> -struct imx_imx21_hcd_data { - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx21_hcd( - const struct imx_imx21_hcd_data *data, - const struct mx21_usbh_platform_data *pdata); - -struct imx_imx27_coda_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx27_coda( - const struct imx_imx27_coda_data *data); - -struct imx_imx2_wdt_data { - int id; - resource_size_t iobase; - resource_size_t iosize; -}; -struct platform_device *__init imx_add_imx2_wdt( - const struct imx_imx2_wdt_data *data); - -struct imx_imxdi_rtc_data { - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imxdi_rtc( - const struct imx_imxdi_rtc_data *data); - -#include <linux/platform_data/video-imxfb.h> -struct imx_imx_fb_data { - const char *devid; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_fb( - const struct imx_imx_fb_data *data, - const struct imx_fb_platform_data *pdata); - -#include <linux/platform_data/i2c-imx.h> -struct imx_imx_i2c_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_i2c( - const struct imx_imx_i2c_data *data, - const struct imxi2c_platform_data *pdata); - -#include <linux/input/matrix_keypad.h> -struct imx_imx_keypad_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_keypad( - const struct imx_imx_keypad_data *data, - const struct matrix_keymap_data *pdata); - -#include <linux/platform_data/asoc-imx-ssi.h> -struct imx_imx_ssi_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; - resource_size_t dmatx0; - resource_size_t dmarx0; - resource_size_t dmatx1; - resource_size_t dmarx1; -}; -struct platform_device *__init imx_add_imx_ssi( - const struct imx_imx_ssi_data *data, - const struct imx_ssi_platform_data *pdata); - -#include <linux/platform_data/serial-imx.h> -struct imx_imx_uart_3irq_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irqrx; - resource_size_t irqtx; - resource_size_t irqrts; -}; -struct platform_device *__init imx_add_imx_uart_3irq( - const struct imx_imx_uart_3irq_data *data, - const struct imxuart_platform_data *pdata); - -struct imx_imx_uart_1irq_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_uart_1irq( - const struct imx_imx_uart_1irq_data *data, - const struct imxuart_platform_data *pdata); - -#include <linux/platform_data/usb-imx_udc.h> -struct imx_imx_udc_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq0; - resource_size_t irq1; - resource_size_t irq2; - resource_size_t irq3; - resource_size_t irq4; - resource_size_t irq5; - resource_size_t irq6; -}; -struct platform_device *__init imx_add_imx_udc( - const struct imx_imx_udc_data *data, - const struct imxusb_platform_data *pdata); - -#include <linux/platform_data/video-mx3fb.h> -#include <linux/platform_data/camera-mx3.h> -struct imx_ipu_core_data { - resource_size_t iobase; - resource_size_t synirq; - resource_size_t errirq; -}; -struct platform_device *__init imx_add_ipu_core( - const struct imx_ipu_core_data *data); -struct platform_device *__init imx_alloc_mx3_camera( - const struct imx_ipu_core_data *data, - const struct mx3_camera_pdata *pdata); -struct platform_device *__init imx_add_mx3_sdc_fb( - const struct imx_ipu_core_data *data, - struct mx3fb_platform_data *pdata); - -#include <linux/platform_data/camera-mx1.h> -struct imx_mx1_camera_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mx1_camera( - const struct imx_mx1_camera_data *data, - const struct mx1_camera_pdata *pdata); - -#include <linux/platform_data/camera-mx2.h> -struct imx_mx2_camera_data { - const char *devid; - resource_size_t iobasecsi; - resource_size_t iosizecsi; - resource_size_t irqcsi; - resource_size_t iobaseemmaprp; - resource_size_t iosizeemmaprp; - resource_size_t irqemmaprp; -}; -struct platform_device *__init imx_add_mx2_camera( - const struct imx_mx2_camera_data *data, - const struct mx2_camera_platform_data *pdata); - - -struct imx_mx2_emma_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mx2_emmaprp( - const struct imx_mx2_emma_data *data); - -#include <linux/platform_data/usb-ehci-mxc.h> -struct imx_mxc_ehci_data { - int id; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_ehci( - const struct imx_mxc_ehci_data *data, - const struct mxc_usbh_platform_data *pdata); - -#include <linux/platform_data/mmc-mxcmmc.h> -struct imx_mxc_mmc_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; - resource_size_t dmareq; -}; -struct platform_device *__init imx_add_mxc_mmc( - const struct imx_mxc_mmc_data *data, - const struct imxmmc_platform_data *pdata); - -#include <linux/platform_data/mtd-mxc_nand.h> -struct imx_mxc_nand_data { - const char *devid; - /* - * id is traditionally 0, but -1 is more appropriate. We use -1 for new - * machines but don't change existing devices as the nand device usually - * appears in the kernel command line to pass its partitioning. - */ - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t axibase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_nand( - const struct imx_mxc_nand_data *data, - const struct mxc_nand_platform_data *pdata); - -struct imx_pata_imx_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_pata_imx( - const struct imx_pata_imx_data *data); - -struct imx_mxc_pwm_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_pwm( - const struct imx_mxc_pwm_data *data); - -/* mxc_rtc */ -struct imx_mxc_rtc_data { - const char *devid; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_rtc( - const struct imx_mxc_rtc_data *data); - -/* mxc_w1 */ -struct imx_mxc_w1_data { - resource_size_t iobase; -}; -struct platform_device *__init imx_add_mxc_w1( - const struct imx_mxc_w1_data *data); - -#include <linux/platform_data/mmc-esdhc-imx.h> -struct imx_sdhci_esdhc_imx_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_sdhci_esdhc_imx( - const struct imx_sdhci_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata); - -#include <linux/platform_data/spi-imx.h> -struct imx_spi_imx_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - int irq; -}; -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata); - -struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase, - int irq, int irq_err); -struct platform_device *imx_add_imx_sdma(char *name, - resource_size_t iobase, int irq, struct sdma_platform_data *pdata); diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c deleted file mode 100644 index 1b4366a0e7c0..000000000000 --- a/arch/arm/mach-imx/devices/devices.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/platform_device.h> - -struct device mxc_aips_bus = { - .init_name = "mxc_aips", - .parent = &platform_bus, -}; - -struct device mxc_ahb_bus = { - .init_name = "mxc_ahb", - .parent = &platform_bus, -}; - -int __init mxc_device_init(void) -{ - int ret; - - ret = device_register(&mxc_aips_bus); - if (ret < 0) - goto done; - - ret = device_register(&mxc_ahb_bus); - -done: - return ret; -} diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c deleted file mode 100644 index 63eba08f87b1..000000000000 --- a/arch/arm/mach-imx/devices/platform-fec.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> -#include <asm/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_fec_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobase = soc ## _FEC_BASE_ADDR, \ - .irq = soc ## _INT_FEC, \ - } - -#ifdef CONFIG_SOC_IMX25 -const struct imx_fec_data imx25_fec_data __initconst = - imx_fec_data_entry_single(MX25, "imx25-fec"); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_fec_data imx27_fec_data __initconst = - imx_fec_data_entry_single(MX27, "imx27-fec"); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX35 -/* i.mx35 has the i.mx27 type fec */ -const struct imx_fec_data imx35_fec_data __initconst = - imx_fec_data_entry_single(MX35, "imx27-fec"); -#endif - -#ifdef CONFIG_SOC_IMX51 -/* i.mx51 has the i.mx27 type fec */ -const struct imx_fec_data imx51_fec_data __initconst = - imx_fec_data_entry_single(MX51, "imx27-fec"); -#endif - -#ifdef CONFIG_SOC_IMX53 -/* i.mx53 has the i.mx25 type fec */ -const struct imx_fec_data imx53_fec_data __initconst = - imx_fec_data_entry_single(MX53, "imx25-fec"); -#endif - -struct platform_device *__init imx_add_fec( - const struct imx_fec_data *data, - const struct fec_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device_dmamask(data->devid, 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c deleted file mode 100644 index 55d61eaf63c6..000000000000 --- a/arch/arm/mach-imx/devices/platform-flexcan.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_CAN ## _hwid, \ - } - -#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX25 -const struct imx_flexcan_data imx25_flexcan_data[] __initconst = { -#define imx25_flexcan_data_entry(_id, _hwid) \ - imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_flexcan_data_entry(0, 1), - imx25_flexcan_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { -#define imx35_flexcan_data_entry(_id, _hwid) \ - imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) - imx35_flexcan_data_entry(0, 1), - imx35_flexcan_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_flexcan( - const struct imx_flexcan_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("flexcan", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c deleted file mode 100644 index 3c06bd96e9cc..000000000000 --- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobase = soc ## _USB_OTG_BASE_ADDR, \ - .irq = soc ## _INT_USB_OTG, \ - } - -#ifdef CONFIG_SOC_IMX25 -const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX25, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51"); -#endif - -struct platform_device *__init imx_add_fsl_usb2_udc( - const struct imx_fsl_usb2_udc_data *data, - const struct fsl_usb2_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask(data->devid, -1, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c deleted file mode 100644 index 26483fa94b75..000000000000 --- a/arch/arm/mach-imx/devices/platform-gpio-mxc.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Linaro Limited - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices-common.h" - -struct platform_device *__init mxc_register_gpio(char *name, int id, - resource_size_t iobase, resource_size_t iosize, int irq, int irq_high) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, { - .start = irq_high, - .end = irq_high, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxc_aips_bus, - name, id, res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-gpio_keys.c b/arch/arm/mach-imx/devices/platform-gpio_keys.c deleted file mode 100644 index 486282539c76..000000000000 --- a/arch/arm/mach-imx/devices/platform-gpio_keys.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ -#include <asm/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -struct platform_device *__init imx_add_gpio_keys( - const struct gpio_keys_platform_data *pdata) -{ - return imx_add_platform_device("gpio-keys", -1, NULL, - 0, pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-dma.c b/arch/arm/mach-imx/devices/platform-imx-dma.c deleted file mode 100644 index ccdb5dc4ddbd..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-dma.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "devices-common.h" - -struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name, - resource_size_t iobase, int irq, int irq_err) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, { - .start = irq_err, - .end = irq_err, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxc_ahb_bus, - name, -1, res, ARRAY_SIZE(res), NULL, 0); -} - -struct platform_device __init __maybe_unused *imx_add_imx_sdma(char *name, - resource_size_t iobase, int irq, struct sdma_platform_data *pdata) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxc_ahb_bus, name, - -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c deleted file mode 100644 index 25a47c616b2d..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-fb.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_fb_data_entry_single(soc, _devid, _size) \ - { \ - .devid = _devid, \ - .iobase = soc ## _LCDC_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_LCDC, \ - } - -#ifdef CONFIG_SOC_IMX1 -const struct imx_imx_fb_data imx1_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX1, "imx1-fb", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX1 */ - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_fb_data imx21_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_fb_data imx25_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX25, "imx21-fb", SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_fb_data imx27_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -struct platform_device *__init imx_add_imx_fb( - const struct imx_imx_fb_data *data, - const struct imx_fb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask(data->devid, 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c deleted file mode 100644 index 57d342e85c2f..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-i2c.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_I2C ## _hwid, \ - } - -#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \ - [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX1 -const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst = - imx_imx_i2c_data_entry_single(MX1, "imx1-i2c", 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX1 */ - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = - imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { -#define imx25_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX25, "imx21-i2c", _id, _hwid, SZ_16K) - imx25_imx_i2c_data_entry(0, 1), - imx25_imx_i2c_data_entry(1, 2), - imx25_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { -#define imx27_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K) - imx27_imx_i2c_data_entry(0, 1), - imx27_imx_i2c_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { -#define imx31_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K) - imx31_imx_i2c_data_entry(0, 1), - imx31_imx_i2c_data_entry(1, 2), - imx31_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { -#define imx35_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K) - imx35_imx_i2c_data_entry(0, 1), - imx35_imx_i2c_data_entry(1, 2), - imx35_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { -#define imx51_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K) - imx51_imx_i2c_data_entry(0, 1), - imx51_imx_i2c_data_entry(1, 2), - { - .devid = "imx21-i2c", - .id = 2, - .iobase = MX51_HSI2C_DMA_BASE_ADDR, - .iosize = SZ_16K, - .irq = MX51_INT_HS_I2C, - }, -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = { -#define imx53_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K) - imx53_imx_i2c_data_entry(0, 1), - imx53_imx_i2c_data_entry(1, 2), - imx53_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_imx_i2c( - const struct imx_imx_i2c_data *data, - const struct imxi2c_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c deleted file mode 100644 index 8f22a4c98a4c..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-keypad.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_keypad_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _KPP_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_KPP, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX21, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX25, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX27, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX31, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX35, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX51, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX53, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_imx_keypad( - const struct imx_imx_keypad_data *data, - const struct matrix_keymap_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imx-keypad", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c deleted file mode 100644 index bfcb8f3dfa8d..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-ssi.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_SSI ## _hwid, \ - .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \ - .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \ - .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \ - .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { -#define imx21_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K) - imx21_imx_ssi_data_entry(0, 1), - imx21_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { -#define imx25_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) - imx25_imx_ssi_data_entry(0, 1), - imx25_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { -#define imx27_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_ssi_data_entry(0, 1), - imx27_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { -#define imx31_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_ssi_data_entry(0, 1), - imx31_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { -#define imx35_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) - imx35_imx_ssi_data_entry(0, 1), - imx35_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { -#define imx51_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K) - imx51_imx_ssi_data_entry(0, 1), - imx51_imx_ssi_data_entry(1, 2), - imx51_imx_ssi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = { -#define imx53_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K) - imx53_imx_ssi_data_entry(0, 1), - imx53_imx_ssi_data_entry(1, 2), - imx53_imx_ssi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_imx_ssi( - const struct imx_imx_ssi_data *data, - const struct imx_ssi_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, -#define DMARES(_name) { \ - .name = #_name, \ - .start = data->dma ## _name, \ - .end = data->dma ## _name, \ - .flags = IORESOURCE_DMA, \ -} - DMARES(tx0), - DMARES(rx0), - DMARES(tx1), - DMARES(rx1), - }; - - return imx_add_platform_device("imx-ssi", data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c deleted file mode 100644 index faac4aa6ca6d..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-uart.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irqrx = soc ## _INT_UART ## _hwid ## RX, \ - .irqtx = soc ## _INT_UART ## _hwid ## TX, \ - .irqrts = soc ## _INT_UART ## _hwid ## RTS, \ - } - -#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_UART ## _hwid, \ - } - -#ifdef CONFIG_SOC_IMX1 -const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = { -#define imx1_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0) - imx1_imx_uart_data_entry(0, 1), - imx1_imx_uart_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX1 */ - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { -#define imx21_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) - imx21_imx_uart_data_entry(0, 1), - imx21_imx_uart_data_entry(1, 2), - imx21_imx_uart_data_entry(2, 3), - imx21_imx_uart_data_entry(3, 4), -}; -#endif - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { -#define imx25_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_imx_uart_data_entry(0, 1), - imx25_imx_uart_data_entry(1, 2), - imx25_imx_uart_data_entry(2, 3), - imx25_imx_uart_data_entry(3, 4), - imx25_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { -#define imx27_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_uart_data_entry(0, 1), - imx27_imx_uart_data_entry(1, 2), - imx27_imx_uart_data_entry(2, 3), - imx27_imx_uart_data_entry(3, 4), - imx27_imx_uart_data_entry(4, 5), - imx27_imx_uart_data_entry(5, 6), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { -#define imx31_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_uart_data_entry(0, 1), - imx31_imx_uart_data_entry(1, 2), - imx31_imx_uart_data_entry(2, 3), - imx31_imx_uart_data_entry(3, 4), - imx31_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { -#define imx35_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K) - imx35_imx_uart_data_entry(0, 1), - imx35_imx_uart_data_entry(1, 2), - imx35_imx_uart_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { -#define imx51_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) - imx51_imx_uart_data_entry(0, 1), - imx51_imx_uart_data_entry(1, 2), - imx51_imx_uart_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = { -#define imx53_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K) - imx53_imx_uart_data_entry(0, 1), - imx53_imx_uart_data_entry(1, 2), - imx53_imx_uart_data_entry(2, 3), - imx53_imx_uart_data_entry(3, 4), - imx53_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_imx_uart_3irq( - const struct imx_imx_uart_3irq_data *data, - const struct imxuart_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irqrx, - .end = data->irqrx, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irqtx, - .end = data->irqtx, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irqrts, - .end = data->irqrx, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imx1-uart", data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} - -struct platform_device *__init imx_add_imx_uart_1irq( - const struct imx_imx_uart_1irq_data *data, - const struct imxuart_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - /* i.mx21 type uart runs on all i.mx except i.mx1 */ - return imx_add_platform_device("imx21-uart", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c deleted file mode 100644 index ec75d6413686..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - } -#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = { -#define imx51_imx2_wdt_data_entry(_id, _hwid) \ - imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K) - imx51_imx2_wdt_data_entry(0, 1), - imx51_imx2_wdt_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = { -#define imx53_imx2_wdt_data_entry(_id, _hwid) \ - imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K) - imx53_imx2_wdt_data_entry(0, 1), - imx53_imx2_wdt_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_imx2_wdt( - const struct imx_imx2_wdt_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, - }; - return imx_add_platform_device("imx2-wdt", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c deleted file mode 100644 index 30c81616a9a1..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx21-hcd.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx21_hcd_data_entry_single(soc) \ - { \ - .iobase = soc ## _USBOTG_BASE_ADDR, \ - .irq = soc ## _INT_USBHOST, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = - imx_imx21_hcd_data_entry_single(MX21); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -struct platform_device *__init imx_add_imx21_hcd( - const struct imx_imx21_hcd_data *data, - const struct mx21_usbh_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("imx21-hcd", 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx27-coda.c b/arch/arm/mach-imx/devices/platform-imx27-coda.c deleted file mode 100644 index 25bebc29e546..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx27-coda.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2012 Vista Silicon - * Javier Martin <javier.martin@vista-silicon.com> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include "../hardware.h" -#include "devices-common.h" - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx27_coda_data imx27_coda_data __initconst = { - .iobase = MX27_VPU_BASE_ADDR, - .iosize = SZ_512, - .irq = MX27_INT_VPU, -}; -#endif - -struct platform_device *__init imx_add_imx27_coda( - const struct imx_imx27_coda_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL, - 0, DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx_udc.c b/arch/arm/mach-imx/devices/platform-imx_udc.c deleted file mode 100644 index 5ced7e4e2c71..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx_udc.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_udc_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _USBD_BASE_ADDR, \ - .iosize = _size, \ - .irq0 = soc ## _INT_USBD0, \ - .irq1 = soc ## _INT_USBD1, \ - .irq2 = soc ## _INT_USBD2, \ - .irq3 = soc ## _INT_USBD3, \ - .irq4 = soc ## _INT_USBD4, \ - .irq5 = soc ## _INT_USBD5, \ - .irq6 = soc ## _INT_USBD6, \ - } - -#define imx_imx_udc_data_entry(soc, _size) \ - [_id] = imx_imx_udc_data_entry_single(soc, _size) - -#ifdef CONFIG_SOC_IMX1 -const struct imx_imx_udc_data imx1_imx_udc_data __initconst = - imx_imx_udc_data_entry_single(MX1, SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX1 */ - -struct platform_device *__init imx_add_imx_udc( - const struct imx_imx_udc_data *data, - const struct imxusb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq0, - .end = data->irq0, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq1, - .end = data->irq1, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq2, - .end = data->irq2, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq3, - .end = data->irq3, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq4, - .end = data->irq4, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq5, - .end = data->irq5, - .flags = IORESOURCE_IRQ, - }, { - .start = data->irq6, - .end = data->irq6, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imx_udc", 0, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c b/arch/arm/mach-imx/devices/platform-imxdi_rtc.c deleted file mode 100644 index 5bb490d556ea..000000000000 --- a/arch/arm/mach-imx/devices/platform-imxdi_rtc.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imxdi_rtc_data_entry_single(soc) \ - { \ - .iobase = soc ## _DRYICE_BASE_ADDR, \ - .irq = soc ## _INT_DRYICE, \ - } - -#ifdef CONFIG_SOC_IMX25 -const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst = - imx_imxdi_rtc_data_entry_single(MX25); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -struct platform_device *__init imx_add_imxdi_rtc( - const struct imx_imxdi_rtc_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imxdi_rtc", 0, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c deleted file mode 100644 index fc4dd7cedc11..000000000000 --- a/arch/arm/mach-imx/devices/platform-ipu-core.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) 2011 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_ipu_core_entry_single(soc) \ -{ \ - .iobase = soc ## _IPU_CTRL_BASE_ADDR, \ - .synirq = soc ## _INT_IPU_SYN, \ - .errirq = soc ## _INT_IPU_ERR, \ -} - -#ifdef CONFIG_SOC_IMX31 -const struct imx_ipu_core_data imx31_ipu_core_data __initconst = - imx_ipu_core_entry_single(MX31); -#endif - -#ifdef CONFIG_SOC_IMX35 -const struct imx_ipu_core_data imx35_ipu_core_data __initconst = - imx_ipu_core_entry_single(MX35); -#endif - -static struct platform_device *imx_ipu_coredev __initdata; - -struct platform_device *__init imx_add_ipu_core( - const struct imx_ipu_core_data *data) -{ - /* The resource order is important! */ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + 0x5f, - .flags = IORESOURCE_MEM, - }, { - .start = data->iobase + 0x88, - .end = data->iobase + 0xb3, - .flags = IORESOURCE_MEM, - }, { - .start = data->synirq, - .end = data->synirq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->errirq, - .end = data->errirq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1, - res, ARRAY_SIZE(res), NULL, 0); -} - -struct platform_device *__init imx_alloc_mx3_camera( - const struct imx_ipu_core_data *data, - const struct mx3_camera_pdata *pdata) -{ - struct resource res[] = { - { - .start = data->iobase + 0x60, - .end = data->iobase + 0x87, - .flags = IORESOURCE_MEM, - }, - }; - int ret = -ENOMEM; - struct platform_device *pdev; - - if (IS_ERR_OR_NULL(imx_ipu_coredev)) - return ERR_PTR(-ENODEV); - - pdev = platform_device_alloc("mx3-camera", 0); - if (!pdev) - goto err; - - pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); - if (!pdev->dev.dma_mask) - goto err; - - *pdev->dev.dma_mask = DMA_BIT_MASK(32); - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); - if (ret) - goto err; - - if (pdata) { - struct mx3_camera_pdata *copied_pdata; - - ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); - if (ret) { -err: - kfree(pdev->dev.dma_mask); - platform_device_put(pdev); - return ERR_PTR(-ENODEV); - } - copied_pdata = dev_get_platdata(&pdev->dev); - copied_pdata->dma_dev = &imx_ipu_coredev->dev; - } - - return pdev; -} - -struct platform_device *__init imx_add_mx3_sdc_fb( - const struct imx_ipu_core_data *data, - struct mx3fb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase + 0xb4, - .end = data->iobase + 0x1bf, - .flags = IORESOURCE_MEM, - }, - }; - - if (IS_ERR_OR_NULL(imx_ipu_coredev)) - return ERR_PTR(-ENODEV); - - pdata->dma_dev = &imx_ipu_coredev->dev; - - return imx_add_platform_device_dmamask("mx3_sdc_fb", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), - DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mx1-camera.c b/arch/arm/mach-imx/devices/platform-mx1-camera.c deleted file mode 100644 index 2c6788131080..000000000000 --- a/arch/arm/mach-imx/devices/platform-mx1-camera.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mx1_camera_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _CSI ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_CSI, \ - } - -#ifdef CONFIG_SOC_IMX1 -const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst = - imx_mx1_camera_data_entry_single(MX1, 10); -#endif /* ifdef CONFIG_SOC_IMX1 */ - -struct platform_device *__init imx_add_mx1_camera( - const struct imx_mx1_camera_data *data, - const struct mx1_camera_pdata *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("mx1-camera", 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c deleted file mode 100644 index b53e1f348f51..000000000000 --- a/arch/arm/mach-imx/devices/platform-mx2-camera.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mx2_camera_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobasecsi = soc ## _CSI_BASE_ADDR, \ - .iosizecsi = SZ_4K, \ - .irqcsi = soc ## _INT_CSI, \ - } -#define imx_mx2_camera_data_entry_single_emma(soc, _devid) \ - { \ - .devid = _devid, \ - .iobasecsi = soc ## _CSI_BASE_ADDR, \ - .iosizecsi = SZ_32, \ - .irqcsi = soc ## _INT_CSI, \ - .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ - .iosizeemmaprp = SZ_32, \ - .irqemmaprp = soc ## _INT_EMMAPRP, \ - } - -#ifdef CONFIG_SOC_IMX25 -const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst = - imx_mx2_camera_data_entry_single(MX25, "imx25-camera"); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = - imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera"); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -struct platform_device *__init imx_add_mx2_camera( - const struct imx_mx2_camera_data *data, - const struct mx2_camera_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobasecsi, - .end = data->iobasecsi + data->iosizecsi - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irqcsi, - .end = data->irqcsi, - .flags = IORESOURCE_IRQ, - }, { - .start = data->iobaseemmaprp, - .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irqemmaprp, - .end = data->irqemmaprp, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask(data->devid, 0, - res, data->iobaseemmaprp ? 4 : 2, - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} - diff --git a/arch/arm/mach-imx/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c deleted file mode 100644 index 11bd01d402f2..000000000000 --- a/arch/arm/mach-imx/devices/platform-mx2-emma.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mx2_emmaprp_data_entry_single(soc) \ - { \ - .iobase = soc ## _EMMAPRP_BASE_ADDR, \ - .iosize = SZ_32, \ - .irq = soc ## _INT_EMMAPRP, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mx2_emma_data imx27_mx2_emmaprp_data __initconst = - imx_mx2_emmaprp_data_entry_single(MX27); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -struct platform_device *__init imx_add_mx2_emmaprp( - const struct imx_mx2_emma_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("m2m-emmaprp", 0, - res, 2, NULL, 0, DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c deleted file mode 100644 index 5d4bbbfde641..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ - { \ - .id = _id, \ - .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ - .irq = soc ## _INT_USB_ ## hs, \ - } - -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX25, 0, OTG); -const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst = - imx_mxc_ehci_data_entry_single(MX25, 1, HS); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX27, 0, OTG); -const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { - imx_mxc_ehci_data_entry_single(MX27, 1, HS1), - imx_mxc_ehci_data_entry_single(MX27, 2, HS2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX31, 0, OTG); -const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { - imx_mxc_ehci_data_entry_single(MX31, 1, HS1), - imx_mxc_ehci_data_entry_single(MX31, 2, HS2), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX35, 0, OTG); -const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = - imx_mxc_ehci_data_entry_single(MX35, 1, HS); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX51, 0, OTG); -const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = { - imx_mxc_ehci_data_entry_single(MX51, 1, HS1), - imx_mxc_ehci_data_entry_single(MX51, 2, HS2), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -struct platform_device *__init imx_add_mxc_ehci( - const struct imx_mxc_ehci_data *data, - const struct mxc_usbh_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("mxc-ehci", data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c deleted file mode 100644 index b8203c760c8f..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc-mmc.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_SDHC ## _hwid, \ - .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ - } -#define imx_mxc_mmc_data_entry(soc, _devid, _id, _hwid, _size) \ - [_id] = imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { -#define imx21_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K) - imx21_mxc_mmc_data_entry(0, 1), - imx21_mxc_mmc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { -#define imx27_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K) - imx27_mxc_mmc_data_entry(0, 1), - imx27_mxc_mmc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { -#define imx31_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX31, "imx31-mmc", _id, _hwid, SZ_16K) - imx31_mxc_mmc_data_entry(0, 1), - imx31_mxc_mmc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -struct platform_device *__init imx_add_mxc_mmc( - const struct imx_mxc_mmc_data *data, - const struct imxmmc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->dmareq, - .end = data->dmareq, - .flags = IORESOURCE_DMA, - }, - }; - return imx_add_platform_device_dmamask(data->devid, data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c deleted file mode 100644 index 7af1c53e42b5..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_nand.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include <asm/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_nand_data_entry_single(soc, _devid, _size) \ - { \ - .devid = _devid, \ - .iobase = soc ## _NFC_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_NFC \ - } - -#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size) \ - { \ - .devid = _devid, \ - .id = -1, \ - .iobase = soc ## _NFC_BASE_ADDR, \ - .iosize = _size, \ - .axibase = soc ## _NFC_AXI_BASE_ADDR, \ - .irq = soc ## _INT_NFC \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K); -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K); -#endif - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K); -#endif - -#ifdef CONFIG_SOC_IMX51 -const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = - imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K); -#endif - -struct platform_device *__init imx_add_mxc_nand( - const struct imx_mxc_nand_data *data, - const struct mxc_nand_platform_data *pdata) -{ - /* AXI has to come first, that's how the mxc_nand driver expect it */ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->axibase, - .end = data->axibase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - }; - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res) - !data->axibase, - pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_pwm.c b/arch/arm/mach-imx/devices/platform-mxc_pwm.c deleted file mode 100644 index dcd289777687..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_pwm.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_PWM ## _hwid, \ - } -#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX25 -const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = { -#define imx25_mxc_pwm_data_entry(_id, _hwid) \ - imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K) - imx25_mxc_pwm_data_entry(0, 1), - imx25_mxc_pwm_data_entry(1, 2), - imx25_mxc_pwm_data_entry(2, 3), - imx25_mxc_pwm_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst = - imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst = { -#define imx51_mxc_pwm_data_entry(_id, _hwid) \ - imx_mxc_pwm_data_entry(MX51, _id, _hwid, SZ_16K) - imx51_mxc_pwm_data_entry(0, 1), - imx51_mxc_pwm_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -struct platform_device *__init imx_add_mxc_pwm( - const struct imx_mxc_pwm_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("mxc_pwm", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c deleted file mode 100644 index c58404badb59..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -struct imx_mxc_rnga_data { - resource_size_t iobase; -}; - -#define imx_mxc_rnga_data_entry_single(soc) \ - { \ - .iobase = soc ## _RNGA_BASE_ADDR, \ - } - -#ifdef CONFIG_SOC_IMX31 -static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = - imx_mxc_rnga_data_entry_single(MX31); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -static struct platform_device *__init imx_add_mxc_rnga( - const struct imx_mxc_rnga_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - }; - return imx_add_platform_device("mxc_rnga", -1, - res, ARRAY_SIZE(res), NULL, 0); -} - -static int __init imxXX_add_mxc_rnga(void) -{ - struct platform_device *ret; - -#if defined(CONFIG_SOC_IMX31) - if (cpu_is_mx31()) - ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); - else -#endif /* if defined(CONFIG_SOC_IMX31) */ - ret = ERR_PTR(-ENODEV); - - if (IS_ERR(ret)) - return PTR_ERR(ret); - - return 0; -} -arch_initcall(imxXX_add_mxc_rnga); diff --git a/arch/arm/mach-imx/devices/platform-mxc_rtc.c b/arch/arm/mach-imx/devices/platform-mxc_rtc.c deleted file mode 100644 index c7fffaadf847..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_rtc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2010-2011 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_rtc_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobase = soc ## _RTC_BASE_ADDR, \ - .irq = soc ## _INT_RTC, \ - } - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = - imx_mxc_rtc_data_entry_single(MX31, "imx21-rtc"); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst = - imx_mxc_rtc_data_entry_single(MX35, "imx21-rtc"); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_mxc_rtc( - const struct imx_mxc_rtc_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device(data->devid, -1, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c deleted file mode 100644 index 88c18b720d63..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_w1.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_w1_data_entry_single(soc) \ - { \ - .iobase = soc ## _OWIRE_BASE_ADDR, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX21); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX27); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX31); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX35); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_mxc_w1( - const struct imx_mxc_w1_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - }; - - return imx_add_platform_device("mxc_w1", 0, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c deleted file mode 100644 index e4ec11c8ce55..000000000000 --- a/arch/arm/mach-imx/devices/platform-pata_imx.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_pata_imx_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _ATA_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_ATA, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_pata_imx_data imx27_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX27, SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_pata_imx_data imx31_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX31, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_pata_imx_data imx35_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX35, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_pata_imx_data imx51_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX51, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_pata_imx_data imx53_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX53, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_pata_imx( - const struct imx_pata_imx_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device("pata_imx", -1, - res, ARRAY_SIZE(res), NULL, 0); -} - diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c deleted file mode 100644 index e66a4e316311..000000000000 --- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <linux/platform_data/mmc-esdhc-imx.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_ESDHC ## hwid, \ - } - -#define imx_sdhci_esdhc_imx_data_entry(soc, devid, id, hwid) \ - [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, devid, id, hwid) - -#ifdef CONFIG_SOC_IMX25 -const struct imx_sdhci_esdhc_imx_data -imx25_sdhci_esdhc_imx_data[] __initconst = { -#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \ - imx_sdhci_esdhc_imx_data_entry(MX25, "sdhci-esdhc-imx25", _id, _hwid) - imx25_sdhci_esdhc_imx_data_entry(0, 1), - imx25_sdhci_esdhc_imx_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_sdhci_esdhc_imx_data -imx35_sdhci_esdhc_imx_data[] __initconst = { -#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ - imx_sdhci_esdhc_imx_data_entry(MX35, "sdhci-esdhc-imx35", _id, _hwid) - imx35_sdhci_esdhc_imx_data_entry(0, 1), - imx35_sdhci_esdhc_imx_data_entry(1, 2), - imx35_sdhci_esdhc_imx_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -const struct imx_sdhci_esdhc_imx_data -imx51_sdhci_esdhc_imx_data[] __initconst = { -#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \ - imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid) - imx51_sdhci_esdhc_imx_data_entry(0, 1), - imx51_sdhci_esdhc_imx_data_entry(1, 2), - imx51_sdhci_esdhc_imx_data_entry(2, 3), - imx51_sdhci_esdhc_imx_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -const struct imx_sdhci_esdhc_imx_data -imx53_sdhci_esdhc_imx_data[] __initconst = { -#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid) \ - imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid) - imx53_sdhci_esdhc_imx_data_entry(0, 1), - imx53_sdhci_esdhc_imx_data_entry(1, 2), - imx53_sdhci_esdhc_imx_data_entry(2, 3), - imx53_sdhci_esdhc_imx_data_entry(3, 4), -}; -#endif /* ifdef CONFIG_SOC_IMX53 */ - -static const struct esdhc_platform_data default_esdhc_pdata __initconst = { - .wp_type = ESDHC_WP_NONE, - .cd_type = ESDHC_CD_NONE, -}; - -struct platform_device *__init imx_add_sdhci_esdhc_imx( - const struct imx_sdhci_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - /* - * If machine does not provide pdata, use the default one - * which means no WP/CD support - */ - if (!pdata) - pdata = &default_esdhc_pdata; - - return imx_add_platform_device(data->devid, data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c deleted file mode 100644 index 8880bcb11e05..000000000000 --- a/arch/arm/mach-imx/devices/platform-spi_imx.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_ ## type ## hwid, \ - } - -#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ - [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) - -#ifdef CONFIG_SOC_IMX1 -const struct imx_spi_imx_data imx1_cspi_data[] __initconst = { -#define imx1_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K) - imx1_cspi_data_entry(0, 1), - imx1_cspi_data_entry(1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX21 -const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { -#define imx21_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K) - imx21_cspi_data_entry(0, 1), - imx21_cspi_data_entry(1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX25 -/* i.mx25 has the i.mx35 type cspi */ -const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { -#define imx25_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX25, CSPI, "imx35-cspi", _id, _hwid, SZ_16K) - imx25_cspi_data_entry(0, 1), - imx25_cspi_data_entry(1, 2), - imx25_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX25 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { -#define imx27_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K) - imx27_cspi_data_entry(0, 1), - imx27_cspi_data_entry(1, 2), - imx27_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { -#define imx31_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) - imx31_cspi_data_entry(0, 1), - imx31_cspi_data_entry(1, 2), - imx31_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { -#define imx35_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) - imx35_cspi_data_entry(0, 1), - imx35_cspi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -#ifdef CONFIG_SOC_IMX51 -/* i.mx51 has the i.mx35 type cspi */ -const struct imx_spi_imx_data imx51_cspi_data __initconst = - imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K); - -const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = { -#define imx51_ecspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) - imx51_ecspi_data_entry(0, 1), - imx51_ecspi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX51 */ - -#ifdef CONFIG_SOC_IMX53 -/* i.mx53 has the i.mx35 type cspi */ -const struct imx_spi_imx_data imx53_cspi_data __initconst = - imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K); - -/* i.mx53 has the i.mx51 type ecspi */ -const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = { -#define imx53_ecspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K) - imx53_ecspi_data_entry(0, 1), - imx53_ecspi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX53 */ - -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, - const struct spi_imx_master *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c deleted file mode 100644 index 134c190e3003..000000000000 --- a/arch/arm/mach-imx/ehci-imx25.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX25_OTG_SIC_SHIFT 29 -#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) -#define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) - -#define MX25_H1_SIC_SHIFT 21 -#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) -#define MX25_H1_PM_BIT (1 << 16) -#define MX25_H1_IPPUE_UP_BIT (1 << 7) -#define MX25_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX25_H1_TLL_BIT (1 << 5) -#define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) - -int mx25_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | - MX25_OTG_OCPOL_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_OTG_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_OTG_OCPOL_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | - MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT | - MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX25_H1_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_H1_OCPOL_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX25_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX25_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX25_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX25_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} - diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c deleted file mode 100644 index 448d9115539d..000000000000 --- a/arch/arm/mach-imx/ehci-imx27.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX27_OTG_SIC_SHIFT 29 -#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT) -#define MX27_OTG_PM_BIT (1 << 24) - -#define MX27_H2_SIC_SHIFT 21 -#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT) -#define MX27_H2_PM_BIT (1 << 16) -#define MX27_H2_DT_BIT (1 << 5) - -#define MX27_H1_SIC_SHIFT 13 -#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT) -#define MX27_H1_PM_BIT (1 << 8) -#define MX27_H1_DT_BIT (1 << 4) - -int mx27_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_OTG_PM_BIT; - break; - case 1: /* H1 port */ - v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX27_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX27_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} - diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c deleted file mode 100644 index 05de4e1e39d7..000000000000 --- a/arch/arm/mach-imx/ehci-imx31.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -int mx31_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c deleted file mode 100644 index 554e7cccff53..000000000000 --- a/arch/arm/mach-imx/ehci-imx35.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) - -int mx35_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | - MX35_OTG_OCPOL_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_OTG_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_OTG_OCPOL_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | - MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | - MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_H1_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_H1_OCPOL_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX35_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX35_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX35_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX35_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c deleted file mode 100644 index e49710b10c68..000000000000 --- a/arch/arm/mach-imx/ehci-imx5.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "hardware.h" - -#define MXC_OTG_OFFSET 0 -#define MXC_H1_OFFSET 0x200 -#define MXC_H2_OFFSET 0x400 - -/* USB_CTRL */ -#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ -#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ -#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ -#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ - -/* USB_PHY_CTRL_FUNC */ -#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ -#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ -#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ -#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ -#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ - -/* USBH2CTRL */ -#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) -#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) -#define MXC_H2_UCTRL_H2PM_BIT (1 << 4) - -#define MXC_USBCMD_OFFSET 0x140 - -/* USBCMD */ -#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ - -int mx51_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - void __iomem *usb_base; - void __iomem *usbotg_base; - void __iomem *usbother_base; - int ret = 0; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) { - printk(KERN_ERR "%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - switch (port) { - case 0: /* OTG port */ - usbotg_base = usb_base + MXC_OTG_OFFSET; - break; - case 1: /* Host 1 port */ - usbotg_base = usb_base + MXC_H1_OFFSET; - break; - case 2: /* Host 2 port */ - usbotg_base = usb_base + MXC_H2_OFFSET; - break; - default: - printk(KERN_ERR"%s no such port %d\n", __func__, port); - ret = -ENOENT; - goto error; - } - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - switch (port) { - case 0: /*OTG port */ - if (flags & MXC_EHCI_INTERNAL_PHY) { - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) - v |= MXC_OTG_PHYCTRL_OC_POL_BIT; - else - v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; - if (flags & MXC_EHCI_POWER_PINS_ENABLED) { - /* OC/USBPWR is used */ - v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; - } else { - /* OC/USBPWR is not used */ - v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; - } - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; - else - v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) - v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ - else - v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_OTG_UCTRL_OPM_BIT; - else - v |= MXC_OTG_UCTRL_OPM_BIT; - __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); - } - break; - case 1: /* Host 1 */ - /*Host ULPI */ - v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) { - /* HOST1 wakeup/ULPI intr enable */ - v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); - } else { - /* HOST1 wakeup/ULPI intr disable */ - v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT); - } - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/ - else - v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ - __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); - - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) - v |= MXC_H1_OC_POL_BIT; - else - v &= ~MXC_H1_OC_POL_BIT; - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ - else - v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - - v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); - if (flags & MXC_EHCI_ITC_NO_THRESHOLD) - /* Interrupt Threshold Control:Immediate (no threshold) */ - v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; - __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); - break; - case 2: /* Host 2 ULPI */ - v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); - if (flags & MXC_EHCI_WAKEUP_ENABLED) { - /* HOST1 wakeup/ULPI intr enable */ - v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); - } else { - /* HOST1 wakeup/ULPI intr disable */ - v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT); - } - - if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/ - else - v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ - __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); - break; - } - -error: - iounmap(usb_base); - return ret; -} - diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c deleted file mode 100644 index e02de188ae83..000000000000 --- a/arch/arm/mach-imx/epit.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/epit.c - * - * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#define EPITCR 0x00 -#define EPITSR 0x04 -#define EPITLR 0x08 -#define EPITCMPR 0x0c -#define EPITCNR 0x10 - -#define EPITCR_EN (1 << 0) -#define EPITCR_ENMOD (1 << 1) -#define EPITCR_OCIEN (1 << 2) -#define EPITCR_RLD (1 << 3) -#define EPITCR_PRESC(x) (((x) & 0xfff) << 4) -#define EPITCR_SWR (1 << 16) -#define EPITCR_IOVW (1 << 17) -#define EPITCR_DBGEN (1 << 18) -#define EPITCR_WAITEN (1 << 19) -#define EPITCR_RES (1 << 20) -#define EPITCR_STOPEN (1 << 21) -#define EPITCR_OM_DISCON (0 << 22) -#define EPITCR_OM_TOGGLE (1 << 22) -#define EPITCR_OM_CLEAR (2 << 22) -#define EPITCR_OM_SET (3 << 22) -#define EPITCR_CLKSRC_OFF (0 << 24) -#define EPITCR_CLKSRC_PERIPHERAL (1 << 24) -#define EPITCR_CLKSRC_REF_HIGH (1 << 24) -#define EPITCR_CLKSRC_REF_LOW (3 << 24) - -#define EPITSR_OCIF (1 << 0) - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "hardware.h" - -static struct clock_event_device clockevent_epit; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -static void __iomem *timer_base; - -static inline void epit_irq_disable(void) -{ - u32 val; - - val = __raw_readl(timer_base + EPITCR); - val &= ~EPITCR_OCIEN; - __raw_writel(val, timer_base + EPITCR); -} - -static inline void epit_irq_enable(void) -{ - u32 val; - - val = __raw_readl(timer_base + EPITCR); - val |= EPITCR_OCIEN; - __raw_writel(val, timer_base + EPITCR); -} - -static void epit_irq_acknowledge(void) -{ - __raw_writel(EPITSR_OCIF, timer_base + EPITSR); -} - -static int __init epit_clocksource_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - - return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32, - clocksource_mmio_readl_down); -} - -/* clock event */ - -static int epit_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + EPITCNR); - - __raw_writel(tcmp - evt, timer_base + EPITCMPR); - - return 0; -} - -static void epit_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call epit_set_next_event() - */ - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - epit_irq_disable(); - - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - - /* Clear pending interrupt */ - epit_irq_acknowledge(); - } - - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR "epit_set_mode: Periodic mode is not " - "supported for i.MX EPIT\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * epit_set_next_event(), the core has about 4 minutes - * to call epit_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - epit_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t epit_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_epit; - - epit_irq_acknowledge(); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction epit_timer_irq = { - .name = "i.MX EPIT Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = epit_timer_interrupt, -}; - -static struct clock_event_device clockevent_epit = { - .name = "epit", - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = epit_set_mode, - .set_next_event = epit_set_next_event, - .rating = 200, -}; - -static int __init epit_clockevent_init(struct clk *timer_clk) -{ - clockevent_epit.cpumask = cpumask_of(0); - clockevents_config_and_register(&clockevent_epit, - clk_get_rate(timer_clk), - 0x800, 0xfffffffe); - - return 0; -} - -void __init epit_timer_init(void __iomem *base, int irq) -{ - struct clk *timer_clk; - - timer_clk = clk_get_sys("imx-epit.0", NULL); - if (IS_ERR(timer_clk)) { - pr_err("i.MX epit: unable to get clk\n"); - return; - } - - clk_prepare_enable(timer_clk); - - timer_base = base; - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - __raw_writel(0x0, timer_base + EPITCR); - - __raw_writel(0xffffffff, timer_base + EPITLR); - __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, - timer_base + EPITCR); - - /* init and register the timer to the framework */ - epit_clocksource_init(timer_clk); - epit_clockevent_init(timer_clk); - - /* Make irqs happen */ - setup_irq(irq, &epit_timer_irq); -} diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h deleted file mode 100644 index a21d3313f994..000000000000 --- a/arch/arm/mach-imx/eukrea-baseboards.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on board-pcm038.h which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_EUKREA_BASEBOARDS_H__ -#define __MACH_EUKREA_BASEBOARDS_H__ - -#ifndef __ASSEMBLY__ -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. - * TODO: Add your own baseboard init function and call it from - * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() - * eukrea_cpuimx35_init() eukrea_cpuimx51_init() - * or eukrea_cpuimx51sd_init(). - * - * This example here is for the development board. Refer - * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 - * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 - * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 - * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 - * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd - */ - -extern void eukrea_mbimxsd25_baseboard_init(void); -extern void eukrea_mbimx27_baseboard_init(void); -extern void eukrea_mbimxsd35_baseboard_init(void); -extern void eukrea_mbimx51_baseboard_init(void); -extern void eukrea_mbimxsd51_baseboard_init(void); - -#endif - -#endif /* __MACH_EUKREA_BASEBOARDS_H__ */ diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c deleted file mode 100644 index b2f08bfbbdd3..000000000000 --- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/spi/ads7846.h> -#include <linux/backlight.h> -#include <video/platform_lcd.h> - -#include <asm/mach/arch.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -static const int eukrea_mbimx27_pins[] __initconst = { - /* UART2 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART3 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* UART4 */ -#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, -#endif - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* SPI1 */ - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* SSI4 */ -#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \ - || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE) - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD | GPIO_PUEN, - PC18_PF_SSI4_TXD | GPIO_PUEN, - PC19_PF_SSI4_CLK, -#endif -}; - -static const uint32_t eukrea_mbimx27_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), -}; - -static const struct matrix_keymap_data -eukrea_mbimx27_keymap_data __initconst = { - .keymap = eukrea_mbimx27_keymap, - .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), -}; - -static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_PORTF | 16, - }, - { - .name = "led2", - .default_trigger = "none", - .active_low = 1, - .gpio = GPIO_PORTF | 19, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimx27_gpio_led_info __initconst = { - .leds = eukrea_mbimx27_gpio_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds), -}; - -static struct imx_fb_videomode eukrea_mbimx27_modes[] = { - { - .mode = { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = 156000, - .hsync_len = 30, - .left_margin = 38, - .right_margin = 20, - .vsync_len = 3, - .upper_margin = 15, - .lower_margin = 4, - }, - .pcr = 0xFAD08B80, - .bpp = 16, - }, { - .mode = { - .name = "DVI-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 32000, - .hsync_len = 1, - .left_margin = 35, - .right_margin = 0, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 0, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, { - .mode = { - .name = "DVI-SVGA", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .hsync_len = 1, - .left_margin = 35, - .right_margin = 0, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 0, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = { - .mode = eukrea_mbimx27_modes, - .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00040060, -}; - -static void eukrea_mbimx27_bl_set_intensity(int intensity) -{ - if (intensity) - gpio_direction_output(GPIO_PORTE | 5, 1); - else - gpio_direction_output(GPIO_PORTE | 5, 0); -} - -static struct generic_bl_info eukrea_mbimx27_bl_info = { - .name = "eukrea_mbimx27-bl", - .max_intensity = 0xff, - .default_intensity = 0xff, - .set_bl_intensity = eukrea_mbimx27_bl_set_intensity, -}; - -static struct platform_device eukrea_mbimx27_bl_dev = { - .name = "generic-bl", - .id = 1, - .dev = { - .platform_data = &eukrea_mbimx27_bl_info, - }, -}; - -static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_PORTA | 25, 1); - else - gpio_direction_output(GPIO_PORTA | 25, 0); -} - -static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = { - .set_power = eukrea_mbimx27_lcd_power_set, -}; - -static struct platform_device eukrea_mbimx27_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimx27_lcd_power_data, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define ADS7846_PENDOWN (GPIO_PORTD | 25) - -static void __maybe_unused ads7846_dev_init(void) -{ - if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { - printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); - return; - } - gpio_direction_input(ADS7846_PENDOWN); -} - -static int ads7846_get_pendown_state(void) -{ - return !gpio_get_value(ADS7846_PENDOWN); -} - -static struct ads7846_platform_data ads7846_config __initdata = { - .get_pendown_state = ads7846_get_pendown_state, - .keep_vref_on = 1, -}; - -static struct spi_board_info __maybe_unused - eukrea_mbimx27_spi_board_info[] __initdata = { - [0] = { - .modalias = "ads7846", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 1500000, - /* irq number is run-time assigned */ - .platform_data = &ads7846_config, - .mode = SPI_MODE_2, - }, -}; - -static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28}; - -static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = { - .chipselect = eukrea_mbimx27_spi_cs, - .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs), -}; - -static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .dat3_card_detect = 1, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = { - .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, -}; - -/* - * system init for baseboard usage. Will be called by cpuimx27 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimx27_baseboard_init(void) -{ - mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins, - ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27"); - - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); -#if !defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) - imx27_add_imx_uart3(&uart_pdata); -#endif - - imx27_add_imx_fb(&eukrea_mbimx27_fb_data); - imx27_add_mxc_mmc(0, &sdhc_pdata); - - i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, - ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); - - imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata); - -#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ - || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) - /* ADS7846 Touchscreen controller init */ - mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN); - ads7846_dev_init(); -#endif - - /* SPI_CS0 init */ - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); - imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); - eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25)); - spi_register_board_info(eukrea_mbimx27_spi_board_info, - ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); - - /* Leds configuration */ - mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT); - mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT); - /* Backlight */ - mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT); - gpio_request(GPIO_PORTE | 5, "backlight"); - platform_device_register(&eukrea_mbimx27_bl_dev); - /* LCD Reset */ - mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT); - gpio_request(GPIO_PORTA | 25, "lcd_enable"); - platform_device_register(&eukrea_mbimx27_lcd_powerdev); - - imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data); - - gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info); - imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); -} diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c deleted file mode 100644 index e77cc3af6db2..000000000000 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/spi/spi.h> -#include <video/platform_lcd.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include "common.h" -#include "devices-imx25.h" -#include "hardware.h" -#include "iomux-mx25.h" -#include "mx25.h" - -static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { - /* LCD */ - MX25_PAD_LD0__LD0, - MX25_PAD_LD1__LD1, - MX25_PAD_LD2__LD2, - MX25_PAD_LD3__LD3, - MX25_PAD_LD4__LD4, - MX25_PAD_LD5__LD5, - MX25_PAD_LD6__LD6, - MX25_PAD_LD7__LD7, - MX25_PAD_LD8__LD8, - MX25_PAD_LD9__LD9, - MX25_PAD_LD10__LD10, - MX25_PAD_LD11__LD11, - MX25_PAD_LD12__LD12, - MX25_PAD_LD13__LD13, - MX25_PAD_LD14__LD14, - MX25_PAD_LD15__LD15, - MX25_PAD_GPIO_E__LD16, - MX25_PAD_GPIO_F__LD17, - MX25_PAD_HSYNC__HSYNC, - MX25_PAD_VSYNC__VSYNC, - MX25_PAD_LSCLK__LSCLK, - MX25_PAD_OE_ACD__OE_ACD, - MX25_PAD_CONTRAST__CONTRAST, - /* LCD_PWR */ - MX25_PAD_PWM__GPIO_1_26, - /* LED */ - MX25_PAD_POWER_FAIL__GPIO_3_19, - /* SWITCH */ - MX25_PAD_VSTBY_ACK__GPIO_3_18, - /* UART2 */ - MX25_PAD_UART2_RTS__UART2_RTS, - MX25_PAD_UART2_CTS__UART2_CTS, - MX25_PAD_UART2_TXD__UART2_TXD, - MX25_PAD_UART2_RXD__UART2_RXD, - /* SD1 */ - MX25_PAD_SD1_CMD__SD1_CMD, - MX25_PAD_SD1_CLK__SD1_CLK, - MX25_PAD_SD1_DATA0__SD1_DATA0, - MX25_PAD_SD1_DATA1__SD1_DATA1, - MX25_PAD_SD1_DATA2__SD1_DATA2, - MX25_PAD_SD1_DATA3__SD1_DATA3, - /* SD1 CD */ - MX25_PAD_DE_B__GPIO_2_20, - /* I2S */ - MX25_PAD_KPP_COL3__AUD5_TXFS, - MX25_PAD_KPP_COL2__AUD5_TXC, - MX25_PAD_KPP_COL1__AUD5_RXD, - MX25_PAD_KPP_COL0__AUD5_TXD, - /* CAN */ - MX25_PAD_GPIO_D__CAN2_RX, - MX25_PAD_GPIO_C__CAN2_TX, - /* SPI1 */ - MX25_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX25_PAD_CSPI1_MISO__CSPI1_MISO, - MX25_PAD_CSPI1_SS0__GPIO_1_16, - MX25_PAD_CSPI1_SS1__GPIO_1_17, - MX25_PAD_CSPI1_SCLK__CSPI1_SCLK, - MX25_PAD_CSPI1_RDY__GPIO_2_22, -}; - -#define GPIO_LED1 IMX_GPIO_NR(3, 19) -#define GPIO_SWITCH1 IMX_GPIO_NR(3, 18) -#define GPIO_SD1CD IMX_GPIO_NR(2, 20) -#define GPIO_LCDPWR IMX_GPIO_NR(1, 26) -#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 16) -#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 17) -#define GPIO_SPI1_IRQ IMX_GPIO_NR(2, 22) - -static struct imx_fb_videomode eukrea_mximxsd_modes[] = { - { - .mode = { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = KHZ2PICOS(6500), - .left_margin = 30, - .right_margin = 38, - .upper_margin = 20, - .lower_margin = 3, - .hsync_len = 15, - .vsync_len = 4, - }, - .bpp = 16, - .pcr = 0xCAD08B80, - }, { - .mode = { - .name = "DVI-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 32000, - .hsync_len = 7, - .left_margin = 100, - .right_margin = 100, - .vsync_len = 7, - .upper_margin = 7, - .lower_margin = 100, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, { - .mode = { - .name = "DVI-SVGA", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .hsync_len = 7, - .left_margin = 75, - .right_margin = 75, - .vsync_len = 7, - .upper_margin = 7, - .lower_margin = 75, - }, - .pcr = 0xFA208B80, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = { - .mode = eukrea_mximxsd_modes, - .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00040060, -}; - -static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_LCDPWR, 1); - else - gpio_direction_output(GPIO_LCDPWR, 0); -} - -static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { - .set_power = eukrea_mbimxsd_lcd_power_set, -}; - -static struct platform_device eukrea_mbimxsd_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, -}; - -static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_LED1, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimxsd_led_info __initconst = { - .leds = eukrea_mbimxsd_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), -}; - -static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { - { - .gpio = GPIO_SWITCH1, - .code = BTN_0, - .desc = "BP1", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data - eukrea_mbimxsd_button_data __initconst = { - .buttons = eukrea_mbimxsd_gpio_buttons, - .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), -}; - -static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_lcd_powerdev, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { - .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_gpio = GPIO_SD1CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = { - { - .modalias = "spidev", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, - { - .modalias = "spidev", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - }, -}; - -static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1}; - -static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = { - .chipselect = eukrea_mbimxsd25_spi_cs, - .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs), -}; - -/* - * system init for baseboard usage. Will be called by cpuimx25 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimxsd25_baseboard_init(void) -{ - if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, - ARRAY_SIZE(eukrea_mbimxsd_pads))) - printk(KERN_ERR "error setting mbimxsd pads !\n"); - - imx25_add_imx_uart1(&uart_pdata); - imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata); - imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); - - imx25_add_flexcan1(); - imx25_add_sdhci_esdhc_imx(0, &sd1_pdata); - - gpio_request(GPIO_LED1, "LED1"); - gpio_direction_output(GPIO_LED1, 1); - gpio_free(GPIO_LED1); - - gpio_request(GPIO_SWITCH1, "SWITCH1"); - gpio_direction_input(GPIO_SWITCH1); - gpio_free(GPIO_SWITCH1); - - gpio_request(GPIO_LCDPWR, "LCDPWR"); - gpio_direction_output(GPIO_LCDPWR, 1); - - i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, - ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); - - gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ"); - gpio_direction_input(GPIO_SPI1_IRQ); - gpio_free(GPIO_SPI1_IRQ); - imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data); - spi_register_board_info(eukrea_mbimxsd25_spi_board_info, - ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info)); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); - imx_add_gpio_keys(&eukrea_mbimxsd_button_data); - imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); -} diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c deleted file mode 100644 index 14d6c8249b76..000000000000 --- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/spi/spi.h> -#include <video/platform_lcd.h> -#include <linux/i2c.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx35.h" -#include "hardware.h" -#include "iomux-mx35.h" - -static const struct fb_videomode fb_modedb[] = { - { - .name = "CMO-QVGA", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = KHZ2PICOS(6500), - .left_margin = 68, - .right_margin = 20, - .upper_margin = 15, - .lower_margin = 4, - .hsync_len = 30, - .vsync_len = 3, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - { - .name = "DVI-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 32000, - .left_margin = 100, - .right_margin = 100, - .upper_margin = 7, - .lower_margin = 100, - .hsync_len = 7, - .vsync_len = 7, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - { - .name = "DVI-SVGA", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 25000, - .left_margin = 75, - .right_margin = 75, - .upper_margin = 7, - .lower_margin = 75, - .hsync_len = 7, - .vsync_len = 7, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "CMO-QVGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { - /* LCD */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - /* Backlight */ - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - /* LCD_PWR */ - MX35_PAD_D3_CLS__GPIO1_4, - /* LED */ - MX35_PAD_LD23__GPIO3_29, - /* SWITCH */ - MX35_PAD_LD19__GPIO3_25, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* I2S */ - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, - MX35_PAD_STXD4__AUDMUX_AUD4_TXD, - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, - MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* CAN2 */ - MX35_PAD_TX5_RX0__CAN2_TXCAN, - MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1 CD */ - MX35_PAD_LD18__GPIO3_24, - /* SPI */ - MX35_PAD_CSPI1_MOSI__CSPI1_MOSI, - MX35_PAD_CSPI1_MISO__CSPI1_MISO, - MX35_PAD_CSPI1_SS0__GPIO1_18, - MX35_PAD_CSPI1_SS1__GPIO1_19, - MX35_PAD_CSPI1_SCLK__CSPI1_SCLK, - MX35_PAD_CSPI1_SPI_RDY__GPIO3_5, -}; - -#define GPIO_LED1 IMX_GPIO_NR(3, 29) -#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) -#define GPIO_LCDPWR IMX_GPIO_NR(1, 4) -#define GPIO_SD1CD IMX_GPIO_NR(3, 24) -#define GPIO_SPI1_SS0 IMX_GPIO_NR(1, 18) -#define GPIO_SPI1_SS1 IMX_GPIO_NR(1, 19) -#define GPIO_SPI1_IRQ IMX_GPIO_NR(3, 5) - -static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_LCDPWR, 1); - else - gpio_direction_output(GPIO_LCDPWR, 0); -} - -static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = { - .set_power = eukrea_mbimxsd_lcd_power_set, -}; - -static struct platform_device eukrea_mbimxsd_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimxsd_lcd_power_data, -}; - -static struct gpio_led eukrea_mbimxsd_leds[] = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_LED1, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimxsd_led_info __initconst = { - .leds = eukrea_mbimxsd_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds), -}; - -static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = { - { - .gpio = GPIO_SWITCH1, - .code = BTN_0, - .desc = "BP1", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data - eukrea_mbimxsd_button_data __initconst = { - .buttons = eukrea_mbimxsd_gpio_buttons, - .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons), -}; - -static struct platform_device *platform_devices[] __initdata = { - &eukrea_mbimxsd_lcd_powerdev, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { - .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, -}; - -static struct esdhc_platform_data sd1_pdata = { - .cd_gpio = GPIO_SD1CD, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_NONE, -}; - -static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = { - { - .modalias = "spidev", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, - { - .modalias = "spidev", - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - }, -}; - -static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1}; - -static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = { - .chipselect = eukrea_mbimxsd35_spi_cs, - .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs), -}; - -/* - * system init for baseboard usage. Will be called by cpuimx35 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimxsd35_baseboard_init(void) -{ - if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads, - ARRAY_SIZE(eukrea_mbimxsd_pads))) - printk(KERN_ERR "error setting mbimxsd pads !\n"); - - imx35_add_imx_uart1(&uart_pdata); - imx35_add_ipu_core(); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); - - imx35_add_flexcan1(); - imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); - - gpio_request(GPIO_LED1, "LED1"); - gpio_direction_output(GPIO_LED1, 1); - gpio_free(GPIO_LED1); - - gpio_request(GPIO_SWITCH1, "SWITCH1"); - gpio_direction_input(GPIO_SWITCH1); - gpio_free(GPIO_SWITCH1); - - gpio_request(GPIO_LCDPWR, "LCDPWR"); - gpio_direction_output(GPIO_LCDPWR, 1); - - i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, - ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); - - gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ"); - gpio_direction_input(GPIO_SPI1_IRQ); - gpio_free(GPIO_SPI1_IRQ); - imx35_add_spi_imx0(&eukrea_mbimxsd35_spi0_data); - spi_register_board_info(eukrea_mbimxsd35_spi_board_info, - ARRAY_SIZE(eukrea_mbimxsd35_spi_board_info)); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - gpio_led_register_device(-1, &eukrea_mbimxsd_led_info); - imx_add_gpio_keys(&eukrea_mbimxsd_button_data); - imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); -} diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c deleted file mode 100644 index 9be6c1e69d68..000000000000 --- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on pcm970-baseboard.c which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/leds.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <video/platform_lcd.h> -#include <linux/backlight.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx51.h" -#include "hardware.h" -#include "iomux-mx51.h" - -static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = { - /* LED */ - MX51_PAD_NANDF_D10__GPIO3_30, - /* SWITCH */ - NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - /* UART 3 */ - MX51_PAD_UART3_RXD__UART3_RXD, - MX51_PAD_UART3_TXD__UART3_TXD, - MX51_PAD_KEY_COL4__UART3_RTS, - MX51_PAD_KEY_COL5__UART3_CTS, - /* SD */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - /* SD1 CD */ - NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), - /* SSI */ - MX51_PAD_AUD3_BB_TXD__AUD3_TXD, - MX51_PAD_AUD3_BB_RXD__AUD3_RXD, - MX51_PAD_AUD3_BB_CK__AUD3_TXC, - MX51_PAD_AUD3_BB_FS__AUD3_TXFS, - /* LCD Backlight */ - MX51_PAD_DI1_D1_CS__GPIO3_4, - /* LCD RST */ - MX51_PAD_CSI1_D9__GPIO3_13, -}; - -#define GPIO_LED1 IMX_GPIO_NR(3, 30) -#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31) -#define GPIO_LCDRST IMX_GPIO_NR(3, 13) -#define GPIO_LCDBL IMX_GPIO_NR(3, 4) - -static void eukrea_mbimxsd51_lcd_power_set(struct plat_lcd_data *pd, - unsigned int power) -{ - if (power) - gpio_direction_output(GPIO_LCDRST, 1); - else - gpio_direction_output(GPIO_LCDRST, 0); -} - -static struct plat_lcd_data eukrea_mbimxsd51_lcd_power_data = { - .set_power = eukrea_mbimxsd51_lcd_power_set, -}; - -static struct platform_device eukrea_mbimxsd51_lcd_powerdev = { - .name = "platform-lcd", - .dev.platform_data = &eukrea_mbimxsd51_lcd_power_data, -}; - -static void eukrea_mbimxsd51_bl_set_intensity(int intensity) -{ - if (intensity) - gpio_direction_output(GPIO_LCDBL, 1); - else - gpio_direction_output(GPIO_LCDBL, 0); -} - -static struct generic_bl_info eukrea_mbimxsd51_bl_info = { - .name = "eukrea_mbimxsd51-bl", - .max_intensity = 0xff, - .default_intensity = 0xff, - .set_bl_intensity = eukrea_mbimxsd51_bl_set_intensity, -}; - -static struct platform_device eukrea_mbimxsd51_bl_dev = { - .name = "generic-bl", - .id = 1, - .dev = { - .platform_data = &eukrea_mbimxsd51_bl_info, - }, -}; - -static const struct gpio_led eukrea_mbimxsd51_leds[] __initconst = { - { - .name = "led1", - .default_trigger = "heartbeat", - .active_low = 1, - .gpio = GPIO_LED1, - }, -}; - -static const struct gpio_led_platform_data - eukrea_mbimxsd51_led_info __initconst = { - .leds = eukrea_mbimxsd51_leds, - .num_leds = ARRAY_SIZE(eukrea_mbimxsd51_leds), -}; - -static struct gpio_keys_button eukrea_mbimxsd51_gpio_buttons[] = { - { - .gpio = GPIO_SWITCH1, - .code = BTN_0, - .desc = "BP1", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data - eukrea_mbimxsd51_button_data __initconst = { - .buttons = eukrea_mbimxsd51_gpio_buttons, - .nbuttons = ARRAY_SIZE(eukrea_mbimxsd51_gpio_buttons), -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct i2c_board_info eukrea_mbimxsd51_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static const -struct imx_ssi_platform_data eukrea_mbimxsd51_ssi_pdata __initconst = { - .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, -}; - -static int screen_type; - -static int __init eukrea_mbimxsd51_screen_type(char *options) -{ - if (!strcmp(options, "dvi")) - screen_type = 1; - else if (!strcmp(options, "tft")) - screen_type = 0; - - return 0; -} -__setup("screen_type=", eukrea_mbimxsd51_screen_type); - -/* - * system init for baseboard usage. Will be called by cpuimx51sd init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init eukrea_mbimxsd51_baseboard_init(void) -{ - if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd51_pads, - ARRAY_SIZE(eukrea_mbimxsd51_pads))) - printk(KERN_ERR "error setting mbimxsd pads !\n"); - - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); - - imx51_add_sdhci_esdhc_imx(0, NULL); - - imx51_add_imx_ssi(0, &eukrea_mbimxsd51_ssi_pdata); - - gpio_request(GPIO_LED1, "LED1"); - gpio_direction_output(GPIO_LED1, 1); - gpio_free(GPIO_LED1); - - gpio_request(GPIO_SWITCH1, "SWITCH1"); - gpio_direction_input(GPIO_SWITCH1); - gpio_free(GPIO_SWITCH1); - - gpio_request(GPIO_LCDRST, "LCDRST"); - gpio_direction_output(GPIO_LCDRST, 0); - gpio_request(GPIO_LCDBL, "LCDBL"); - gpio_direction_output(GPIO_LCDBL, 0); - if (!screen_type) { - platform_device_register(&eukrea_mbimxsd51_bl_dev); - platform_device_register(&eukrea_mbimxsd51_lcd_powerdev); - } else { - gpio_free(GPIO_LCDRST); - gpio_free(GPIO_LCDBL); - } - - i2c_register_board_info(0, eukrea_mbimxsd51_i2c_devices, - ARRAY_SIZE(eukrea_mbimxsd51_i2c_devices)); - - gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info); - imx_add_gpio_keys(&eukrea_mbimxsd51_button_data); - imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0); -} diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index 44a65e9ff1fc..2e633569d2f8 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -1,39 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011-2013 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/io.h> #include <linux/irq.h> +#include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> -#include <linux/irqchip/arm-gic.h> + #include "common.h" +#include "hardware.h" +#define GPC_CNTR 0x0 #define GPC_IMR1 0x008 #define GPC_PGC_CPU_PDN 0x2a0 +#define GPC_PGC_CPU_PUPSCR 0x2a4 +#define GPC_PGC_CPU_PDNSCR 0x2a8 +#define GPC_PGC_SW2ISO_SHIFT 0x8 +#define GPC_PGC_SW_SHIFT 0x0 + +#define GPC_CNTR_L2_PGE_SHIFT 22 #define IMR_NUM 4 +#define GPC_MAX_IRQS (IMR_NUM * 32) static void __iomem *gpc_base; static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM]; -void imx_gpc_pre_suspend(void) +void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) +{ + writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | + (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR); +} + +void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw) +{ + writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | + (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR); +} + +void imx_gpc_set_arm_power_in_lpm(bool power_off) +{ + writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); +} + +void imx_gpc_set_l2_mem_power_in_lpm(bool power_off) +{ + u32 val; + + val = readl_relaxed(gpc_base + GPC_CNTR); + val &= ~(1 << GPC_CNTR_L2_PGE_SHIFT); + if (power_off) + val |= 1 << GPC_CNTR_L2_PGE_SHIFT; + writel_relaxed(val, gpc_base + GPC_CNTR); +} + +void imx_gpc_pre_suspend(bool arm_power_off) { void __iomem *reg_imr1 = gpc_base + GPC_IMR1; int i; /* Tell GPC to power off ARM core when suspend */ - writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN); + if (arm_power_off) + imx_gpc_set_arm_power_in_lpm(arm_power_off); for (i = 0; i < IMR_NUM; i++) { gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); @@ -47,7 +80,7 @@ void imx_gpc_post_resume(void) int i; /* Keep ARM core powered on for other low-power modes */ - writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN); + imx_gpc_set_arm_power_in_lpm(false); for (i = 0; i < IMR_NUM; i++) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); @@ -55,17 +88,17 @@ void imx_gpc_post_resume(void) static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) { - unsigned int idx = d->irq / 32 - 1; + unsigned int idx = d->hwirq / 32; u32 mask; - /* Sanity check for SPI irq */ - if (d->irq < 32) - return -EINVAL; - - mask = 1 << d->irq % 32; + mask = 1 << d->hwirq % 32; gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask : gpc_wake_irqs[idx] & ~mask; + /* + * Do *not* call into the parent, as the GIC doesn't have any + * wake-up facility... + */ return 0; } @@ -78,7 +111,6 @@ void imx_gpc_mask_all(void) gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); writel_relaxed(~0, reg_imr1 + i * 4); } - } void imx_gpc_restore_all(void) @@ -90,51 +122,163 @@ void imx_gpc_restore_all(void) writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); } -static void imx_gpc_irq_unmask(struct irq_data *d) +void imx_gpc_hwirq_unmask(unsigned int hwirq) { void __iomem *reg; u32 val; - /* Sanity check for SPI irq */ - if (d->irq < 32) - return; - - reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4; + reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; val = readl_relaxed(reg); - val &= ~(1 << d->irq % 32); + val &= ~(1 << hwirq % 32); writel_relaxed(val, reg); } -static void imx_gpc_irq_mask(struct irq_data *d) +void imx_gpc_hwirq_mask(unsigned int hwirq) { void __iomem *reg; u32 val; - /* Sanity check for SPI irq */ - if (d->irq < 32) - return; - - reg = gpc_base + GPC_IMR1 + (d->irq / 32 - 1) * 4; + reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4; val = readl_relaxed(reg); - val |= 1 << (d->irq % 32); + val |= 1 << (hwirq % 32); writel_relaxed(val, reg); } -void __init imx_gpc_init(void) +static void imx_gpc_irq_unmask(struct irq_data *d) { - struct device_node *np; + imx_gpc_hwirq_unmask(d->hwirq); + irq_chip_unmask_parent(d); +} + +static void imx_gpc_irq_mask(struct irq_data *d) +{ + imx_gpc_hwirq_mask(d->hwirq); + irq_chip_mask_parent(d); +} + +static struct irq_chip imx_gpc_chip = { + .name = "GPC", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = imx_gpc_irq_mask, + .irq_unmask = imx_gpc_irq_unmask, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_wake = imx_gpc_irq_set_wake, + .irq_set_type = irq_chip_set_type_parent, +#ifdef CONFIG_SMP + .irq_set_affinity = irq_chip_set_affinity_parent, +#endif +}; + +static int imx_gpc_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count != 3) + return -EINVAL; + + /* No PPI should point to this domain */ + if (fwspec->param[0] != 0) + return -EINVAL; + + *hwirq = fwspec->param[1]; + *type = fwspec->param[2]; + return 0; + } + + return -EINVAL; +} + +static int imx_gpc_domain_alloc(struct irq_domain *domain, + unsigned int irq, + unsigned int nr_irqs, void *data) +{ + struct irq_fwspec *fwspec = data; + struct irq_fwspec parent_fwspec; + irq_hw_number_t hwirq; int i; - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); - gpc_base = of_iomap(np, 0); - WARN_ON(!gpc_base); + if (fwspec->param_count != 3) + return -EINVAL; /* Not GIC compliant */ + if (fwspec->param[0] != 0) + return -EINVAL; /* No PPI should point to this domain */ + + hwirq = fwspec->param[1]; + if (hwirq >= GPC_MAX_IRQS) + return -EINVAL; /* Can't deal with this */ + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, + &imx_gpc_chip, NULL); + + parent_fwspec = *fwspec; + parent_fwspec.fwnode = domain->parent->fwnode; + return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, + &parent_fwspec); +} + +static const struct irq_domain_ops imx_gpc_domain_ops = { + .translate = imx_gpc_domain_translate, + .alloc = imx_gpc_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + +static int __init imx_gpc_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + int i; + + if (!parent) { + pr_err("%pOF: no parent, giving up\n", node); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%pOF: unable to obtain parent domain\n", node); + return -ENXIO; + } + + gpc_base = of_iomap(node, 0); + if (WARN_ON(!gpc_base)) + return -ENOMEM; + + domain = irq_domain_create_hierarchy(parent_domain, 0, GPC_MAX_IRQS, of_fwnode_handle(node), + &imx_gpc_domain_ops, NULL); + if (!domain) { + iounmap(gpc_base); + return -ENOMEM; + } /* Initially mask all interrupts */ for (i = 0; i < IMR_NUM; i++) writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); - /* Register GPC as the secondary interrupt controller behind GIC */ - gic_arch_extn.irq_mask = imx_gpc_irq_mask; - gic_arch_extn.irq_unmask = imx_gpc_irq_unmask; - gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake; + /* + * Clear the OF_POPULATED flag set in of_irq_init so that + * later the GPC power domain driver will not be skipped. + */ + of_node_clear_flag(node, OF_POPULATED); + + return 0; +} +IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init); + +void __init imx_gpc_check_dt(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); + if (WARN_ON(!np)) + return; + + if (WARN_ON(!of_property_read_bool(np, "interrupt-controller"))) { + pr_warn("Outdated DT detected, suspend/resume will NOT work\n"); + + /* map GPC, so that at least CPUidle and WARs keep working */ + gpc_base = of_iomap(np, 0); + } + of_node_put(np); } diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index a3b0b04b45c9..0760fff39a0b 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -1,27 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #define __ASM_ARCH_MXC_HARDWARE_H__ +#ifndef __ASSEMBLY__ #include <asm/io.h> -#include <asm/sizes.h> +#include <soc/imx/revision.h> +#endif +#include <linux/sizes.h> #define addr_in_module(addr, mod) \ ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) @@ -103,16 +93,11 @@ #include "mxc.h" -#include "mx51.h" -#include "mx53.h" #include "mx3x.h" #include "mx31.h" #include "mx35.h" #include "mx2x.h" -#include "mx21.h" #include "mx27.h" -#include "mx1.h" -#include "mx25.h" #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ @@ -121,8 +106,4 @@ .type = _type, \ } -/* There's a off-by-one betweem the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 627f16f0e9d1..5f9c7b48ae80 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -1,23 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/linkage.h> #include <linux/init.h> -#include <asm/asm-offsets.h> -#include <asm/hardware/cache-l2x0.h> +#include <asm/assembler.h> - .section ".text.head", "ax" +.arch armv7-a -#ifdef CONFIG_SMP diag_reg_offset: .word g_diag_reg - . @@ -30,42 +22,16 @@ diag_reg_offset: .endm ENTRY(v7_secondary_startup) - bl v7_invalidate_l1 +ARM_BE8(setend be) @ go BE8 if entered LE + mrc p15, 0, r0, c0, c0, 0 + lsl r0, r0, #16 + lsr r0, r0, #20 + /* 0xc07 is cortex A7's ID */ + mov r1, #0xc00 + orr r1, #0x7 + cmp r0, r1 + beq secondary_startup + set_diag_reg b secondary_startup ENDPROC(v7_secondary_startup) -#endif - -#ifdef CONFIG_ARM_CPU_SUSPEND -/* - * The following code must assume it is running from physical address - * where absolute virtual addresses to the data section have to be - * turned into relative ones. - */ - -#ifdef CONFIG_CACHE_L2X0 - .macro pl310_resume - adr r0, l2x0_saved_regs_offset - ldr r2, [r0] - add r2, r2, r0 - ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 - ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value - str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl - mov r1, #0x1 - str r1, [r0, #L2X0_CTRL] @ re-enable L2 - .endm - -l2x0_saved_regs_offset: - .word l2x0_saved_regs - . - -#else - .macro pl310_resume - .endm -#endif - -ENTRY(v7_cpu_resume) - bl v7_invalidate_l1 - pl310_resume - b cpu_resume -ENDPROC(v7_cpu_resume) -#endif diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c index 3daf1ed90579..e24a46dc5703 100644 --- a/arch/arm/mach-imx/hotplug.c +++ b/arch/arm/mach-imx/hotplug.c @@ -1,42 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/errno.h> #include <linux/jiffies.h> +#include <asm/cacheflush.h> #include <asm/cp15.h> #include <asm/proc-fns.h> #include "common.h" - -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - asm volatile( - "mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, %3\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C), "Ir" (0x40) - : "cc"); -} +#include "hardware.h" /* * platform-specific code to shutdown a CPU @@ -45,14 +20,16 @@ static inline void cpu_enter_lowpower(void) */ void imx_cpu_die(unsigned int cpu) { - cpu_enter_lowpower(); + v7_exit_coherency_flush(louis); /* * We use the cpu jumping argument register to sync with * imx_cpu_kill() which is running on cpu0 and waiting for * the register being cleared to kill the cpu. */ imx_set_cpu_arg(cpu, ~0); - cpu_do_idle(); + + while (1) + cpu_do_idle(); } int imx_cpu_kill(unsigned int cpu) @@ -64,5 +41,7 @@ int imx_cpu_kill(unsigned int cpu) return 0; imx_enable_cpu(cpu, false); imx_set_cpu_arg(cpu, 0); + if (cpu_is_imx7d()) + imx_gpcv2_set_core1_pdn_pup_by_software(true); return 1; } diff --git a/arch/arm/mach-imx/iim.h b/arch/arm/mach-imx/iim.h index 315bffadafda..72c3bca898f5 100644 --- a/arch/arm/mach-imx/iim.h +++ b/arch/arm/mach-imx/iim.h @@ -1,20 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __ASM_ARCH_MXC_IIM_H__ diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c deleted file mode 100644 index 3e1ec5ffe630..000000000000 --- a/arch/arm/mach-imx/imx25-dt.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include "common.h" -#include "mx25.h" - -static void __init imx25_dt_init(void) -{ - mxc_arch_reset_init_dt(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char * const imx25_dt_board_compat[] __initconst = { - "fsl,imx25", - NULL -}; - -static void __init imx25_timer_init(void) -{ - mx25_clocks_init_dt(); -} - -DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") - .map_io = mx25_map_io, - .init_early = imx25_init_early, - .init_irq = mx25_init_irq, - .handle_irq = imx25_handle_irq, - .init_time = imx25_timer_init, - .init_machine = imx25_dt_init, - .dt_compat = imx25_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c deleted file mode 100644 index 4e235ecb4021..000000000000 --- a/arch/arm/mach-imx/imx27-dt.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "mx27.h" - -static void __init imx27_dt_init(void) -{ - struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; - - mxc_arch_reset_init_dt(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - platform_device_register_full(&devinfo); -} - -static const char * const imx27_dt_board_compat[] __initconst = { - "fsl,imx27", - NULL -}; - -static void __init imx27_timer_init(void) -{ - mx27_clocks_init_dt(); -} - -DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = imx27_timer_init, - .init_machine = imx27_dt_init, - .dt_compat = imx27_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c deleted file mode 100644 index 818a1cc2fe45..000000000000 --- a/arch/arm/mach-imx/imx31-dt.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "mx31.h" - -static void __init imx31_dt_init(void) -{ - mxc_arch_reset_init_dt(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} - -static const char *imx31_dt_board_compat[] __initdata = { - "fsl,imx31", - NULL -}; - -static void __init imx31_dt_timer_init(void) -{ - mx31_clocks_init_dt(); -} - -DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = imx31_dt_timer_init, - .init_machine = imx31_dt_init, - .dt_compat = imx31_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c deleted file mode 100644 index 53e43e579dd7..000000000000 --- a/arch/arm/mach-imx/imx51-dt.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "mx51.h" - -static void __init imx51_dt_init(void) -{ - struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; - - mxc_arch_reset_init_dt(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - platform_device_register_full(&devinfo); -} - -static const char *imx51_dt_board_compat[] __initdata = { - "fsl,imx51", - NULL -}; - -static void __init imx51_timer_init(void) -{ - mx51_clocks_init_dt(); -} - -DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_time = imx51_timer_init, - .init_machine = imx51_dt_init, - .init_late = imx51_init_late, - .dt_compat = imx51_dt_board_compat, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c deleted file mode 100644 index 7c66805d2cc0..000000000000 --- a/arch/arm/mach-imx/iomux-imx31.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/io.h> -#include <linux/kernel.h> - -#include "hardware.h" -#include "iomux-mx3.h" - -/* - * IOMUX register (base) addresses - */ -#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) -#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) -#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) -#define IOMUXGPR (IOMUX_BASE + 0x008) -#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C) -#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154) - -static DEFINE_SPINLOCK(gpio_mux_lock); - -#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) - -static unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; -/* - * set the mode for a IOMUX pin. - */ -int mxc_iomux_mode(unsigned int pin_mode) -{ - u32 field, l, mode, ret = 0; - void __iomem *reg; - - reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); - field = pin_mode & 0x3; - mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; - - spin_lock(&gpio_mux_lock); - - l = __raw_readl(reg); - l &= ~(0xff << (field * 8)); - l |= mode << (field * 8); - __raw_writel(l, reg); - - spin_unlock(&gpio_mux_lock); - - return ret; -} -EXPORT_SYMBOL(mxc_iomux_mode); - -/* - * This function configures the pad value for a IOMUX pin. - */ -void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) -{ - u32 field, l; - void __iomem *reg; - - pin &= IOMUX_PADNUM_MASK; - reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; - field = (pin + 2) % 3; - - pr_debug("%s: reg offset = 0x%x, field = %d\n", - __func__, (pin + 2) / 3, field); - - spin_lock(&gpio_mux_lock); - - l = __raw_readl(reg); - l &= ~(0x1ff << (field * 10)); - l |= config << (field * 10); - __raw_writel(l, reg); - - spin_unlock(&gpio_mux_lock); -} -EXPORT_SYMBOL(mxc_iomux_set_pad); - -/* - * allocs a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - */ -int mxc_iomux_alloc_pin(unsigned int pin, const char *label) -{ - unsigned pad = pin & IOMUX_PADNUM_MASK; - - if (pad >= (PIN_MAX + 1)) { - printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", - pad, label ? label : "?"); - return -EINVAL; - } - - if (test_and_set_bit(pad, mxc_pin_alloc_map)) { - printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", - pad, label ? label : "?"); - return -EBUSY; - } - mxc_iomux_mode(pin); - - return 0; -} -EXPORT_SYMBOL(mxc_iomux_alloc_pin); - -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label) -{ - const unsigned int *p = pin_list; - int i; - int ret = -EINVAL; - - for (i = 0; i < count; i++) { - ret = mxc_iomux_alloc_pin(*p, label); - if (ret) - goto setup_error; - p++; - } - return 0; - -setup_error: - mxc_iomux_release_multiple_pins(pin_list, i); - return ret; -} -EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); - -void mxc_iomux_release_pin(unsigned int pin) -{ - unsigned pad = pin & IOMUX_PADNUM_MASK; - - if (pad < (PIN_MAX + 1)) - clear_bit(pad, mxc_pin_alloc_map); -} -EXPORT_SYMBOL(mxc_iomux_release_pin); - -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) -{ - const unsigned int *p = pin_list; - int i; - - for (i = 0; i < count; i++) { - mxc_iomux_release_pin(*p); - p++; - } -} -EXPORT_SYMBOL(mxc_iomux_release_multiple_pins); - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en) -{ - u32 l; - - spin_lock(&gpio_mux_lock); - l = __raw_readl(IOMUXGPR); - if (en) - l |= gp; - else - l &= ~gp; - - __raw_writel(l, IOMUXGPR); - spin_unlock(&gpio_mux_lock); -} -EXPORT_SYMBOL(mxc_iomux_set_gpr); diff --git a/arch/arm/mach-imx/iomux-mx1.h b/arch/arm/mach-imx/iomux-mx1.h deleted file mode 100644 index 95f4681d85d7..000000000000 --- a/arch/arm/mach-imx/iomux-mx1.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#ifndef __MACH_IOMUX_MX1_H__ -#define __MACH_IOMUX_MX1_H__ - -#include "iomux-v1.h" - -#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) -#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) -#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) -#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) -#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) -#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) -#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) -#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) -#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) -#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) -#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) -#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) -#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) -#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) -#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) -#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) -#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) -#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) -#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) -#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) -#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) -#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) -#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) -#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) -#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) -#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) -#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) -#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) -#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) -#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) -#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) -#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) -#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) -#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) -#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) -#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) -#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) -#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) -#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) -#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) -#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) -#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) -#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) -#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) -#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) -#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) -#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) -#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) -#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) -#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) -#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) -#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) -#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) -#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) -#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) -#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) -#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) -#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) -#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) -#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) -#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) -#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) -#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) -#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) -#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) -#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) -#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) -#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) -#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) -#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) -#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) -#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) -#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) -#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) -#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) -#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) -#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) -#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) -#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) -#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) -#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) -#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) -#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) -#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) -#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) -#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) -#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) -#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) -#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) -#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) -#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) -#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) -#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) -#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) -#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) -#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) -#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) -#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) -#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) -#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) -#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) -#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) -#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) -#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) -#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) - -#endif /* ifndef __MACH_IOMUX_MX1_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx21.h b/arch/arm/mach-imx/iomux-mx21.h deleted file mode 100644 index a70cffceb085..000000000000 --- a/arch/arm/mach-imx/iomux-mx21.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#ifndef __MACH_IOMUX_MX21_H__ -#define __MACH_IOMUX_MX21_H__ - -#include "iomux-mx2x.h" -#include "iomux-v1.h" - -/* Primary GPIO pin functions */ - -#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) -#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) -#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) -#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) -#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) -#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) -#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) -#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) -#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) -#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) -#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) -#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) -#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) -#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) - -/* Alternate GPIO pin functions */ - -#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) -#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) -#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) -#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) -#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) -#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) -#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) -#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) -#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) -#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) -#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) -#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) -#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) -#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) -#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) -#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) -#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) -#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) - -/* AIN GPIO pin functions */ - -#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) -#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) -#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) -#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) -#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) -#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) -#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) -#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) -#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) -#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) -#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) - -/* BIN GPIO pin functions */ - -#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) -#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) - -/* CIN GPIO pin functions */ - -#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) - -/* AOUT GPIO pin functions */ - -#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) -#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) -#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) -#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) -#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) -#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) -#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) -#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) -#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) -#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) -#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) -#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) -#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) -#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) -#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) - -#endif /* ifndef __MACH_IOMUX_MX21_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx25.h b/arch/arm/mach-imx/iomux-mx25.h deleted file mode 100644 index be51e838375c..000000000000 --- a/arch/arm/mach-imx/iomux-mx25.h +++ /dev/null @@ -1,524 +0,0 @@ -/* - * arch/arm/plat-mxc/include/mach/iomux-mx25.h - * - * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de> - * - * based on arch/arm/mach-mx25/mx25_pins.h - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * and - * arch/arm/plat-mxc/include/mach/iomux-mx35.h - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __MACH_IOMUX_MX25_H__ -#define __MACH_IOMUX_MX25_H__ - -#include "iomux-v3.h" - -/* - * IOMUX/PAD Bit field definitions - */ - -#define MX25_PAD_A10__A10 IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A10__GPIO_4_0 IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A13__A13 IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A13__GPIO_4_1 IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A14__A14 IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A14__GPIO_2_0 IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A15__A15 IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A15__GPIO_2_1 IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A16__A16 IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A16__GPIO_2_2 IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A17__A17 IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A17__GPIO_2_3 IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A18__A18 IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__GPIO_2_4 IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A18__FEC_COL IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL) - -#define MX25_PAD_A19__A19 IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__FEC_RX_ER IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL) -#define MX25_PAD_A19__GPIO_2_5 IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A20__A20 IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__GPIO_2_6 IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A20__FEC_RDATA2 IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL) - -#define MX25_PAD_A21__A21 IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__GPIO_2_7 IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A21__FEC_RDATA3 IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL) - -#define MX25_PAD_A22__A22 IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A22__GPIO_2_8 IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A23__A23 IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A23__GPIO_2_9 IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_A24__A24 IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__GPIO_2_10 IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A24__FEC_RX_CLK IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL) - -#define MX25_PAD_A25__A25 IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__GPIO_2_11 IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_A25__FEC_CRS IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL) - -#define MX25_PAD_EB0__EB0 IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL) -#define MX25_PAD_EB0__GPIO_2_12 IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_EB1__EB1 IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL) -#define MX25_PAD_EB1__GPIO_2_13 IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_OE__OE IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE__GPIO_2_14 IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS0__CS0 IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL) -#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NF_CE0__NF_CE0 IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NF_CE0__GPIO_3_22 IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_ECB__ECB IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__UART5_TXD_MUX IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_ECB__GPIO_3_23 IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LBA__LBA IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__UART5_RXD_MUX IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL) -#define MX25_PAD_LBA__GPIO_3_24 IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_BCLK__BCLK IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BCLK__GPIO_4_4 IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_RW__RW IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL) -#define MX25_PAD_RW__GPIO_3_25 IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFWE_B__NFWE_B IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWE_B__GPIO_3_26 IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFRE_B__NFRE_B IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFRE_B__GPIO_3_27 IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFALE__NFALE IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFALE__GPIO_3_28 IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFCLE__NFCLE IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFCLE__GPIO_3_29 IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFWP_B__NFWP_B IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_NFWP_B__GPIO_3_30 IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_NFRB__NFRB IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE) -#define MX25_PAD_NFRB__GPIO_3_31 IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D15__D15 IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D15__LD16 IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_D15__GPIO_4_5 IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D14__D14 IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D14__LD17 IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_D14__GPIO_4_6 IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D13__D13 IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D13__LD18 IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_D13__GPIO_4_7 IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D12__D12 IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D12__GPIO_4_8 IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D11__D11 IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D11__GPIO_4_9 IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D10__D10 IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__GPIO_4_10 IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_D9__D9 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__GPIO_4_11 IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE) - -#define MX25_PAD_D8__D8 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__GPIO_4_12 IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_D7__D7 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D7__GPIO_4_13 IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D6__D6 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D6__GPIO_4_14 IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D5__D5 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D5__GPIO_4_15 IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D4__D4 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D4__GPIO_4_16 IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D3__D3 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D3__GPIO_4_17 IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D2__D2 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D2__GPIO_4_18 IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D1__D1 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D1__GPIO_4_19 IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_D0__D0 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_D0__GPIO_4_20 IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD0__LD0 IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL) -#define MX25_PAD_LD0__GPIO_2_15 IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD1__LD1 IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL) -#define MX25_PAD_LD1__GPIO_2_16 IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD2__LD2 IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD2__GPIO_2_17 IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD3__LD3 IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD3__GPIO_2_18 IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD4__LD4 IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD4__GPIO_2_19 IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD5__LD5 IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD5__GPIO_1_19 IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD6__LD6 IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD6__GPIO_1_20 IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD7__LD7 IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD7__GPIO_1_21 IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD8__LD8 IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD8__FEC_TX_ERR IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD9__LD9 IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD9__FEC_COL IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD10__LD10 IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD10__FEC_RX_ER IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD11__LD11 IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD11__FEC_RDATA2 IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD12__LD12 IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD12__FEC_RDATA3 IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL) - -#define MX25_PAD_LD13__LD13 IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD13__FEC_TDATA2 IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD14__LD14 IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD14__FEC_TDATA3 IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LD15__LD15 IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_LD15__FEC_RX_CLK IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL) - -#define MX25_PAD_HSYNC__HSYNC IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_HSYNC__GPIO_1_22 IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_VSYNC__VSYNC IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSYNC__GPIO_1_23 IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_LSCLK__LSCLK IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_LSCLK__GPIO_1_24 IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_OE_ACD__OE_ACD IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_OE_ACD__GPIO_1_25 IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CONTRAST__CONTRAST IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__PWM4_PWMO IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CONTRAST__FEC_CRS IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL) - -#define MX25_PAD_PWM__PWM IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__GPIO_1_26 IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__UART5_RXD_MUX IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__GPIO_1_27 IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D2__CSPI3_MOSI IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__GPIO_1_28 IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D3__CSPI3_MISO IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__UART5_RTS IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__GPIO_1_29 IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D4__CSPI3_SCLK IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__GPIO_1_30 IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D5__CSPI3_RDY IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D6__GPIO_1_31 IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D7__GPIO_1_6 IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D8__GPIO_1_7 IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_D9__GPIO_4_21 IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_MCLK__GPIO_1_8 IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_VSYNC__GPIO_1_9 IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_HSYNC__GPIO_1_10 IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_CLK__GPIO_1_12 IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_I2C1_DAT__GPIO_1_13 IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MOSI__GPIO_1_14 IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_MISO__GPIO_1_15 IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS0__GPIO_1_16 IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SS1__GPIO_1_17 IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CSPI1_SCLK__GPIO_1_18 IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE) -#define MX25_PAD_CSPI1_RDY__GPIO_2_22 IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN) -#define MX25_PAD_UART1_RXD__GPIO_4_22 IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART1_TXD__GPIO_4_23 IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP) -#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL) -#define MX25_PAD_UART1_RTS__GPIO_4_24 IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP) -#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL) -#define MX25_PAD_UART1_CTS__GPIO_4_25 IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RXD__GPIO_4_26 IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_TXD__GPIO_4_27 IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__FEC_COL IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL) -#define MX25_PAD_UART2_RTS__GPIO_4_28 IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UART2_CTS__FEC_RX_ER IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UART2_CTS__GPIO_4_29 IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_CMD__FEC_RDATA2 IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_CMD__GPIO_2_23 IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_CLK__FEC_RDATA3 IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_CLK__GPIO_2_24 IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA0__GPIO_2_25 IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA1__GPIO_2_26 IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA2__FEC_RX_CLK IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA2__GPIO_2_27 IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP) -#define MX25_PAD_SD1_DATA3__FEC_CRS IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL) -#define MX25_PAD_SD1_DATA3__GPIO_2_28 IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL) - -#define KPP_CTL_ROW (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) -#define KPP_CTL_COL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) - -#define MX25_PAD_KPP_ROW0__KPP_ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW0__GPIO_2_29 IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_ROW1__KPP_ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW1__GPIO_2_30 IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_ROW2__KPP_ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW2__GPIO_2_31 IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_ROW3__KPP_ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW) -#define MX25_PAD_KPP_ROW3__CSI_LD1 IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL) -#define MX25_PAD_KPP_ROW3__GPIO_3_0 IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL0__KPP_COL0 IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL0__GPIO_3_1 IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL1__KPP_COL1 IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL1__GPIO_3_2 IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL2__KPP_COL2 IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL2__UART4_RTS IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL2__GPIO_3_3 IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_KPP_COL3__KPP_COL3 IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL) -#define MX25_PAD_KPP_COL3__UART4_CTS IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX25_PAD_KPP_COL3__GPIO_3_4 IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDC__GPIO_3_5 IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) -#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_MDIO__GPIO_3_6 IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA0__GPIO_3_7 IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL) -#define MX25_PAD_FEC_TDATA1__GPIO_3_8 IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_FEC_TX_EN__GPIO_3_9 IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA0__GPIO_3_10 IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) -#define MX25_PAD_FEC_RDATA1__GPIO_3_11 IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTRL) -#define MX25_PAD_FEC_RX_DV__CAN2_RX IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP) -#define MX25_PAD_FEC_RX_DV__GPIO_3_12 IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN) -#define MX25_PAD_FEC_TX_CLK__GPIO_3_13 IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__OWIRE IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_RTCK__GPIO_3_14 IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_DE_B__GPIO_2_20 IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_TDO__TDO IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_GPIO_A__GPIO_A IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_A__CAN1_TX IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) -#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE) - -#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP) -#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP) - -#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) - -#define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) - -#define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST) -#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_REQ__GPIO_3_17 IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_VSTBY_ACK__GPIO_3_18 IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL) -#define MX25_PAD_POWER_FAIL__GPIO_3_19 IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CLKO__GPIO_2_21 IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE0__GPIO_4_30 IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_BOOT_MODE1__GPIO_4_31 IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL) - -#define MX25_PAD_CTL_GRP_DVS_MISC IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_FEC IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_JTAG IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_NFC IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_CSI IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_WEIM IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_DDR IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_CRM IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_KPP IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_SDHC1 IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_LCD IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_UART IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_NFC IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_CSI IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DSE_CSPI1 IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DDRTYPE IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) -#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX25_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx27.h b/arch/arm/mach-imx/iomux-mx27.h deleted file mode 100644 index 218e99e89e86..000000000000 --- a/arch/arm/mach-imx/iomux-mx27.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#ifndef __MACH_IOMUX_MX27_H__ -#define __MACH_IOMUX_MX27_H__ - -#include "iomux-mx2x.h" -#include "iomux-v1.h" - -/* Primary GPIO pin functions */ - -#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) -#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) -#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) -#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) -#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) -#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) -#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) -#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) -#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) -#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) -#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) -#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) -#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) -#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) -#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) -#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) -#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) -#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) -#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) -#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) -#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) -#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) -#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) -#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) -#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) -#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) -#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) -#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) -#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) -#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) - -/* Alternate GPIO pin functions */ - -#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) -#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) -#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) -#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) -#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) -#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) -#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) -#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) -#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) -#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) -#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) -#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) -#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) -#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) -#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) -#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) -#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) -#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) -#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) -#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) -#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) -#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) -#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) -#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) -#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) -#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) -#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) -#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) -#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) -#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) -#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) -#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) -#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) -#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) -#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) -#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) -#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) -#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) -#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) -#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) -#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) -#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) -#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) -#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) -#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) -#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) -#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) -#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) -#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) -#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) -#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) -#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) -#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) - -/* AIN GPIO pin functions */ - -#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) -#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) - -/* BIN GPIO pin functions */ - -#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) - -/* CIN GPIO pin functions */ - -#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) -#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) -#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) -#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) -#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) -#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) -#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) -#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) -#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) -#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) -#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) -#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) -#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) -#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) -#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) -#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) -#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) -/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ - -/* AOUT GPIO pin functions */ - -#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) -#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) - -/* BOUT GPIO pin functions */ - -#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) -#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) -#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) -#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) -#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) -#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) -#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) - -#endif /* __MACH_IOMUX_MX27_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx2x.h b/arch/arm/mach-imx/iomux-mx2x.h deleted file mode 100644 index 7a9b20abda09..000000000000 --- a/arch/arm/mach-imx/iomux-mx2x.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#ifndef __MACH_IOMUX_MX2x_H__ -#define __MACH_IOMUX_MX2x_H__ - -/* Primary GPIO pin functions */ - -#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) -#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) -#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) -#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) -#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) -#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) -#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) -#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) -#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) -#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) -#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) -#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) -#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) -#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) -#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) -#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) -#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) -#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) -#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) -#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) -#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) -#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) -#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) -#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) -#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) -#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) -#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) -#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) -#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) -#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) -#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) -#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) -#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) -#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) -#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) -#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) -#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) -#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) -#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) -#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) -#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) -#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) -#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) -#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) -#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) -#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) -#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) -#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) -#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) -#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) -#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) -#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) -#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) -#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) -#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) -#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) -#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) -#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) -#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) -#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) -#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) -#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) -#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) -#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) -#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) -#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) - -/* Alternate GPIO pin functions */ - -#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) -#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) -#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) -#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) -#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) -#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) -#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) -#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) -#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) -#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) -#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) -#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) -#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) -#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) -#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) -#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) -#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) -#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) -#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) -#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) -#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) -#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) -#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) -#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) -#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) -#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) -#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) - -/* AIN GPIO pin functions */ - -#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) -#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) -#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) -#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) -#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) -#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) -#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) -#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) -#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) -#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) -#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) -#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) -#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) -#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) -#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) -#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) -#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) -#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) -#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) -#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) -#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) -#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) -#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) -#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) -#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) -#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) -#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) -#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) -#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) -#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) -#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) -#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) -#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) -#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) - -/* BIN GPIO pin functions */ - -#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) - -/* CIN GPIO pin functions */ - -#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) -#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) -#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) -#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) -#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) -#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) -#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) -#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) -#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) -#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) - -/* AOUT GPIO pin functions */ - -#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) -#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) -#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) -#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) -#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) - -#endif /* ifndef __MACH_IOMUX_MX2x_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h deleted file mode 100644 index f79f78a1c0ed..000000000000 --- a/arch/arm/mach-imx/iomux-mx3.h +++ /dev/null @@ -1,753 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#ifndef __MACH_IOMUX_MX3_H__ -#define __MACH_IOMUX_MX3_H__ - -#include <linux/types.h> -/* - * various IOMUX output functions - */ - -#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ -#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ -#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ -#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ -#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ -#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ -#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ -#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ -#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ -#define IOMUX_ICONFIG_FUNC 2 /* used as function */ -#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ -#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ - -#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) -#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) -#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) -#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* - * setups a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - * - if the pin is configured as a GPIO, we claim it through kernel gpiolib - */ -int mxc_iomux_alloc_pin(unsigned int pin, const char *label); -/* - * setups mutliple pins - * convenient way to call the above function with tables - */ -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label); - -/* - * releases a single pin: - * - make it available for a future use by another driver - * - frees the GPIO if the pin was configured as GPIO - * - DOES NOT reconfigure the IOMUX in its reset state - */ -void mxc_iomux_release_pin(unsigned int pin); -/* - * releases multiple pins - * convenvient way to call the above function with tables - */ -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void mxc_iomux_set_gpr(enum iomux_gp_func, bool en); - -/* - * This function only configures the iomux hardware. - * It is called by the setup functions and should not be called directly anymore. - * It is here visible for backward compatibility - */ -int mxc_iomux_mode(unsigned int pin_mode); - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_GPIONUM_SHIFT 9 -#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) -#define IOMUX_MODE_SHIFT 17 -#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) - -#define IOMUX_PIN(gpionum, padnum) \ - (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ - (padnum & IOMUX_PADNUM_MASK)) - -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) - -#define IOMUX_TO_GPIO(iomux_pin) \ - ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), - MX31_PIN_PWMO = IOMUX_PIN( 9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), -}; - -#define PIN_MAX 327 -#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ - -/* - * Convenience values for use with mxc_iomux_mode() - * - * Format here is MX31_PIN_(pin name)__(function) - */ -#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) -#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) -#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) -#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) -#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) -#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) -#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO) -#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC) - - -/* - * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, - * cspi2_ss1, cspi1_ss0 cspi1_ss1 - */ - -/* - * This function configures the pad value for a IOMUX pin. - */ -void mxc_iomux_set_pad(enum iomux_pins, u32); - -#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx35.h b/arch/arm/mach-imx/iomux-mx35.h deleted file mode 100644 index 90bfa6b5be6a..000000000000 --- a/arch/arm/mach-imx/iomux-mx35.h +++ /dev/null @@ -1,1267 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option, NO_PAD_CTRL) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_IOMUX_MX35_H__ -#define __MACH_IOMUX_MX35_H__ - -#include "iomux-v3.h" - -/* - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> see also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) - -#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) - -#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) -#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) - -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) - -#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) - -#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) -#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) - -#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) -#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) -#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) -#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) -#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) -#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) -#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) - -#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) - -#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - - -#endif /* __MACH_IOMUX_MX35_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx51.h b/arch/arm/mach-imx/iomux-mx51.h deleted file mode 100644 index 75bbcc4aa2d2..000000000000 --- a/arch/arm/mach-imx/iomux-mx51.h +++ /dev/null @@ -1,827 +0,0 @@ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __MACH_IOMUX_MX51_H__ -#define __MACH_IOMUX_MX51_H__ - -#include "iomux-v3.h" -#define __NA_ 0x000 - - -/* Pad control groupings */ -#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS) -#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_HYS | PAD_CTL_PUE) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ - PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ - PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \ - PAD_CTL_SRE_FAST | PAD_CTL_DVS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) - -#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) -#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) - -/* - * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num> - * See also iomux-v3.h - */ - -/* Raw pin modes without pad control */ -/* PAD MUX ALT INPSE PATH PADCTRL */ - -/* The same pins as above but with the default pad control values applied */ -#define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL) -#define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \ - MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS)) -#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2) -#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4) -#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL) -#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL) -#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL) -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL) -#define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL) -#define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4) -#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4) -#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5) -#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL) -#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) -#define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) -#define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) -#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) - -#endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c deleted file mode 100644 index 2b156d1d9e21..000000000000 --- a/arch/arm/mach-imx/iomux-v1.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * arch/arm/plat-mxc/iomux-v1.c - * - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix - * - * Common code for i.MX1, i.MX21 and i.MX27 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <asm/mach/map.h> - -#include "hardware.h" -#include "iomux-v1.h" - -static void __iomem *imx_iomuxv1_baseaddr; -static unsigned imx_iomuxv1_numports; - -static inline unsigned long imx_iomuxv1_readl(unsigned offset) -{ - return __raw_readl(imx_iomuxv1_baseaddr + offset); -} - -static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) -{ - __raw_writel(val, imx_iomuxv1_baseaddr + offset); -} - -static inline void imx_iomuxv1_rmwl(unsigned offset, - unsigned long mask, unsigned long value) -{ - unsigned long reg = imx_iomuxv1_readl(offset); - - reg &= ~mask; - reg |= value; - - imx_iomuxv1_writel(reg, offset); -} - -static inline void imx_iomuxv1_set_puen( - unsigned int port, unsigned int pin, int on) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); -} - -static inline void imx_iomuxv1_set_ddir( - unsigned int port, unsigned int pin, int out) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); -} - -static inline void imx_iomuxv1_set_gpr( - unsigned int port, unsigned int pin, int af) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); -} - -static inline void imx_iomuxv1_set_gius( - unsigned int port, unsigned int pin, int inuse) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); -} - -static inline void imx_iomuxv1_set_ocr( - unsigned int port, unsigned int pin, unsigned int ocr) -{ - unsigned long shift = (pin & 0xf) << 1; - unsigned long mask = 3 << shift; - unsigned long value = ocr << shift; - unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port); - - imx_iomuxv1_rmwl(offset, mask, value); -} - -static inline void imx_iomuxv1_set_iconfa( - unsigned int port, unsigned int pin, unsigned int aout) -{ - unsigned long shift = (pin & 0xf) << 1; - unsigned long mask = 3 << shift; - unsigned long value = aout << shift; - unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port); - - imx_iomuxv1_rmwl(offset, mask, value); -} - -static inline void imx_iomuxv1_set_iconfb( - unsigned int port, unsigned int pin, unsigned int bout) -{ - unsigned long shift = (pin & 0xf) << 1; - unsigned long mask = 3 << shift; - unsigned long value = bout << shift; - unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port); - - imx_iomuxv1_rmwl(offset, mask, value); -} - -int mxc_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3; - unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3; - - if (port >= imx_iomuxv1_numports) - return -EINVAL; - - /* Pullup enable */ - imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN); - - /* Data direction */ - imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT); - - /* Primary / alternate function */ - imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF); - - /* use as gpio? */ - imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF))); - - imx_iomuxv1_set_ocr(port, pin, ocr); - - imx_iomuxv1_set_iconfa(port, pin, aout); - - imx_iomuxv1_set_iconfb(port, pin, bout); - - return 0; -} -EXPORT_SYMBOL(mxc_gpio_mode); - -static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) -{ - size_t i; - int ret = 0; - - for (i = 0; i < count; ++i) { - ret = mxc_gpio_mode(list[i]); - - if (ret) - return ret; - } - - return ret; -} - -int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label) -{ - int ret; - - ret = imx_iomuxv1_setup_multiple(pin_list, count); - return ret; -} -EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); - -int __init imx_iomuxv1_init(void __iomem *base, int numports) -{ - imx_iomuxv1_baseaddr = base; - imx_iomuxv1_numports = numports; - - return 0; -} diff --git a/arch/arm/mach-imx/iomux-v1.h b/arch/arm/mach-imx/iomux-v1.h deleted file mode 100644 index 02651a40fe23..000000000000 --- a/arch/arm/mach-imx/iomux-v1.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#ifndef __MACH_IOMUX_V1_H__ -#define __MACH_IOMUX_V1_H__ - -/* -* GPIO Module and I/O Multiplexer -* x = 0..3 for reg_A, reg_B, reg_C, reg_D -*/ -#define MXC_DDIR(x) (0x00 + ((x) << 8)) -#define MXC_OCR1(x) (0x04 + ((x) << 8)) -#define MXC_OCR2(x) (0x08 + ((x) << 8)) -#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) -#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) -#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) -#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) -#define MXC_DR(x) (0x1c + ((x) << 8)) -#define MXC_GIUS(x) (0x20 + ((x) << 8)) -#define MXC_SSR(x) (0x24 + ((x) << 8)) -#define MXC_ICR1(x) (0x28 + ((x) << 8)) -#define MXC_ICR2(x) (0x2c + ((x) << 8)) -#define MXC_IMR(x) (0x30 + ((x) << 8)) -#define MXC_ISR(x) (0x34 + ((x) << 8)) -#define MXC_GPR(x) (0x38 + ((x) << 8)) -#define MXC_SWR(x) (0x3c + ((x) << 8)) -#define MXC_PUEN(x) (0x40 + ((x) << 8)) - -#define MX1_NUM_GPIO_PORT 4 -#define MX21_NUM_GPIO_PORT 6 -#define MX27_NUM_GPIO_PORT 6 - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -extern int mxc_gpio_mode(int gpio_mode); -extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label); - -extern int imx_iomuxv1_init(void __iomem *base, int numports); - -#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c deleted file mode 100644 index 9dae74bf47fc..000000000000 --- a/arch/arm/mach-imx/iomux-v3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <asm/mach/map.h> - -#include "hardware.h" -#include "iomux-v3.h" - -static void __iomem *base; - -/* - * configures a single pad in the iomuxer - */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) -{ - u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; - u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; - u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; - u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; - u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; - u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - - if (mux_ctrl_ofs) - __raw_writel(mux_mode, base + mux_ctrl_ofs); - - if (sel_input_ofs) - __raw_writel(sel_input, base + sel_input_ofs); - - if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) - __raw_writel(pad_ctrl, base + pad_ctrl_ofs); - - return 0; -} -EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); - -int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count) -{ - iomux_v3_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = mxc_iomux_v3_setup_pad(*p); - if (ret) - return ret; - p++; - } - return 0; -} -EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); - -void mxc_iomux_v3_init(void __iomem *iomux_v3_base) -{ - base = iomux_v3_base; -} diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h deleted file mode 100644 index 2fa3b5430102..000000000000 --- a/arch/arm/mach-imx/iomux-v3.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> - * - * IOMUX/PAD Bit field definitions - * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..57 (17) - * SEL_INP: 58..61 (4) - * reserved: 63 (1) -*/ - -typedef u64 iomux_v3_cfg_t; - -#define MUX_CTRL_OFS_SHIFT 0 -#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) -#define MUX_PAD_CTRL_OFS_SHIFT 12 -#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) -#define MUX_SEL_INPUT_OFS_SHIFT 24 -#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) - -#define MUX_MODE_SHIFT 36 -#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) -#define MUX_PAD_CTRL_SHIFT 41 -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) -#define MUX_SEL_INPUT_SHIFT 58 -#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) - -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ - _sel_input, _pad_ctrl) \ - (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ - ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ - ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) - -#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) -/* - * Use to set PAD control - */ - -#define NO_PAD_CTRL (1 << 16) -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_HYS (1 << 8) - -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) -#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) - -#define PAD_CTL_ODE (1 << 3) - -#define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) -#define PAD_CTL_DSE_HIGH (2 << 1) -#define PAD_CTL_DSE_MAX (3 << 1) - -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define IOMUX_CONFIG_SION (0x1 << 4) - -#define MX51_NUM_GPIO_PORT 4 - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -/* - * setups a single pad in the iomuxer - */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); - -/* - * setups mutliple pads - * convenient way to call the above function with tables - */ -int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); - -/* - * Initialise the iomux controller - */ -void mxc_iomux_v3_init(void __iomem *iomux_v3_base); - -#endif /* __MACH_IOMUX_V3_H__*/ - diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c index 0a920d184867..2ce3e0130ada 100644 --- a/arch/arm/mach-imx/irq-common.c +++ b/arch/arm/mach-imx/irq-common.c @@ -1,19 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) BitBox Ltd 2010 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #include <linux/module.h> @@ -33,8 +20,10 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) gc = irq_get_chip_data(irq); if (gc && gc->private) { exirq = gc->private; - if (exirq->set_irq_fiq) - ret = exirq->set_irq_fiq(irq, type); + if (exirq->set_irq_fiq) { + struct irq_data *d = irq_get_irq_data(irq); + ret = exirq->set_irq_fiq(irqd_to_hwirq(d), type); + } } return ret; diff --git a/arch/arm/mach-imx/irq-common.h b/arch/arm/mach-imx/irq-common.h index 5b2dabba330f..1c2ac0fa4ab1 100644 --- a/arch/arm/mach-imx/irq-common.h +++ b/arch/arm/mach-imx/irq-common.h @@ -1,19 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) BitBox Ltd 2010 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __PLAT_MXC_IRQ_COMMON_H__ @@ -24,7 +11,6 @@ struct mxc_extra_irq { - int (*set_priority)(unsigned char irq, unsigned char prio); int (*set_irq_fiq)(unsigned int irq, unsigned int type); }; diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c deleted file mode 100644 index 067580b2969b..000000000000 --- a/arch/arm/mach-imx/mach-apf9328.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * linux/arch/arm/mach-imx/mach-apf9328.c - * - * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com> - * - * This work is based on mach-scb9328.c which is: - * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> - * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/dm9000.h> -#include <linux/gpio.h> -#include <linux/i2c.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx1.h" -#include "hardware.h" -#include "iomux-mx1.h" - -static const int apf9328_pins[] __initconst = { - /* UART1 */ - PC9_PF_UART1_CTS, - PC10_PF_UART1_RTS, - PC11_PF_UART1_TXD, - PC12_PF_UART1_RXD, - /* UART2 */ - PB28_PF_UART2_CTS, - PB29_PF_UART2_RTS, - PB30_PF_UART2_TXD, - PB31_PF_UART2_RXD, - /* I2C */ - PA15_PF_I2C_SDA, - PA16_PF_I2C_SCL, -}; - -/* - * The APF9328 can have up to 32MB NOR Flash - */ -static struct resource flash_resource = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct physmap_flash_data apf9328_flash_data = { - .width = 2, -}; - -static struct platform_device apf9328_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &apf9328_flash_data, - }, - .resource = &flash_resource, - .num_resources = 1, -}; - -/* - * APF9328 has a DM9000 Ethernet controller - */ -static struct dm9000_plat_data dm9000_setup = { - .flags = DM9000_PLATF_16BITONLY -}; - -static struct resource dm9000_resources[] = { - { - .start = MX1_CS4_PHYS + 0x00C00000, - .end = MX1_CS4_PHYS + 0x00C00001, - .flags = IORESOURCE_MEM, - }, { - .start = MX1_CS4_PHYS + 0x00C00002, - .end = MX1_CS4_PHYS + 0x00C00003, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct platform_device dm9000x_device = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9000_resources), - .resource = dm9000_resources, - .dev = { - .platform_data = &dm9000_setup, - } -}; - -static const struct imxuart_platform_data uart1_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data apf9328_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct platform_device *devices[] __initdata = { - &apf9328_flash_device, - &dm9000x_device, -}; - -static void __init apf9328_init(void) -{ - imx1_soc_init(); - - mxc_gpio_setup_multiple_pins(apf9328_pins, - ARRAY_SIZE(apf9328_pins), - "APF9328"); - - imx1_add_imx_uart0(NULL); - imx1_add_imx_uart1(&uart1_pdata); - - imx1_add_imx_i2c(&apf9328_i2c_data); - - dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14)); - dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14)); - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init apf9328_timer_init(void) -{ - mx1_clocks_init(32768); -} - -MACHINE_START(APF9328, "Armadeus APF9328") - /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */ - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .init_time = apf9328_timer_init, - .init_machine = apf9328_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c deleted file mode 100644 index 368a6e3f5926..000000000000 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * armadillo5x0.c - * - * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * updates in http://alberdroid.blogspot.com/ - * - * Based on Atmark Techno, Inc. armadillo 500 BSP 2008 - * Based on mx31ads.c and pcm037.c Great Work! - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/delay.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx31.h" -#include "crmregs-imx3.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static int armadillo5x0_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* UART2 */ - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - /* LAN9118_IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ - /* I2C2 */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - /* OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /* USB host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), -}; - -/* USB */ - -#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4) -#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6) -#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3) - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbotg_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - /* Chip already enabled by hardware */ - /* OTG phy reset*/ - err = gpio_request(OTG_RESET, "USB-OTG-RESET"); - if (err) { - pr_err("Failed to request the usb otg reset gpio\n"); - return err; - } - - err = gpio_direction_output(OTG_RESET, 1/*HIGH*/); - if (err) { - pr_err("Failed to reset the usb otg phy\n"); - goto otg_free_reset; - } - - gpio_set_value(OTG_RESET, 0/*LOW*/); - mdelay(5); - gpio_set_value(OTG_RESET, 1/*HIGH*/); - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); - -otg_free_reset: - gpio_free(OTG_RESET); - return err; -} - -static int usbh2_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - - /* Enable the chip */ - err = gpio_request(USBH2_CS, "USB-H2-CS"); - if (err) { - pr_err("Failed to request the usb host 2 CS gpio\n"); - return err; - } - - err = gpio_direction_output(USBH2_CS, 0/*Enabled*/); - if (err) { - pr_err("Failed to drive the usb host 2 CS gpio\n"); - goto h2_free_cs; - } - - /* H2 phy reset*/ - err = gpio_request(USBH2_RESET, "USB-H2-RESET"); - if (err) { - pr_err("Failed to request the usb host 2 reset gpio\n"); - goto h2_free_cs; - } - - err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/); - if (err) { - pr_err("Failed to reset the usb host 2 phy\n"); - goto h2_free_reset; - } - - gpio_set_value(USBH2_RESET, 0/*LOW*/); - mdelay(5); - gpio_set_value(USBH2_RESET, 1/*HIGH*/); - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); - -h2_free_reset: - gpio_free(USBH2_RESET); -h2_free_cs: - gpio_free(USBH2_CS); - return err; -} - -static struct mxc_usbh_platform_data usbotg_pdata __initdata = { - .init = usbotg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* RTC over I2C*/ -#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) - -static struct i2c_board_info armadillo5x0_i2c_rtc = { - I2C_BOARD_INFO("s35390a", 0x30), -}; - -/* GPIO BUTTONS */ -static struct gpio_keys_button armadillo5x0_buttons[] = { - { - .code = KEY_ENTER, /*28*/ - .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0), - .active_low = 1, - .desc = "menu", - .wakeup = 1, - }, { - .code = KEY_BACK, /*158*/ - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0), - .active_low = 1, - .desc = "back", - .wakeup = 1, - } -}; - -static const struct gpio_keys_platform_data - armadillo5x0_button_data __initconst = { - .buttons = armadillo5x0_buttons, - .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), -}; - -/* - * NAND Flash - */ -static const struct mxc_nand_platform_data -armadillo5x0_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -/* - * MTD NOR Flash - */ -static struct mtd_partition armadillo5x0_nor_flash_partitions[] = { - { - .name = "nor.bootloader", - .offset = 0x00000000, - .size = 4*32*1024, - }, { - .name = "nor.kernel", - .offset = MTDPART_OFS_APPEND, - .size = 16*128*1024, - }, { - .name = "nor.userland", - .offset = MTDPART_OFS_APPEND, - .size = 110*128*1024, - }, { - .name = "nor.config", - .offset = MTDPART_OFS_APPEND, - .size = 1*128*1024, - }, -}; - -static const struct physmap_flash_data - armadillo5x0_nor_flash_pdata __initconst = { - .width = 2, - .parts = armadillo5x0_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), -}; - -static const struct resource armadillo5x0_nor_flash_resource __initconst = { - .flags = IORESOURCE_MEM, - .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 640x480 @ 60 Hz */ - .name = "CRT-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 35, - .right_margin = 115, - .upper_margin = 43, - .lower_margin = 1, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, {/* 800x600 @ 56 Hz */ - .name = "CRT-SVGA", - .refresh = 56, - .xres = 800, - .yres = 600, - .pixclock = 30000, - .left_margin = 30, - .right_margin = 108, - .upper_margin = 13, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "CRT-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* - * SDHC 1 - * MMC support - */ -static int armadillo5x0_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static int armadillo5x0_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - int gpio_det, gpio_wp; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B); - - ret = gpio_request(gpio_det, "sdhc-card-detect"); - if (ret) - return ret; - - gpio_direction_input(gpio_det); - - ret = gpio_request(gpio_wp, "sdhc-write-protect"); - if (ret) - goto err_gpio_free; - - gpio_direction_input(gpio_wp); - - /* When supported the trigger type have to be BOTH */ - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), - detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(gpio_wp); - -err_gpio_free: - gpio_free(gpio_det); - - return ret; - -} - -static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .get_ro = armadillo5x0_sdhc1_get_ro, - .init = armadillo5x0_sdhc1_init, - .exit = armadillo5x0_sdhc1_exit, -}; - -/* - * SMSC 9118 - * Network support - */ -static struct resource armadillo5x0_smc911x_resources[] = { - { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device armadillo5x0_smc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources), - .resource = armadillo5x0_smc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -/* UART device data */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &armadillo5x0_smc911x_device, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -/* - * Perform board specific initializations - */ -static void __init armadillo5x0_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(armadillo5x0_pins, - ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - armadillo5x0_smc911x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - armadillo5x0_smc911x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx_add_gpio_keys(&armadillo5x0_button_data); - imx31_add_imx_i2c1(NULL); - - /* Register UART */ - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); - - /* SMSC9118 IRQ pin */ - gpio_direction_input(MX31_PIN_GPIO1_0); - - /* Register SDHC */ - imx31_add_mxc_mmc(0, &sdhc_pdata); - - /* Register FB */ - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* Register NOR Flash */ - platform_device_register_resndata(NULL, "physmap-flash", -1, - &armadillo5x0_nor_flash_resource, 1, - &armadillo5x0_nor_flash_pdata, - sizeof(armadillo5x0_nor_flash_pdata)); - - /* Register NAND Flash */ - imx31_add_mxc_nand(&armadillo5x0_nand_board_info); - - /* set NAND page size to 2k if not configured via boot mode pins */ - __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) | - (1 << 30), mx3_ccm_base + MXC_CCM_RCSR); - - /* RTC */ - /* Get RTC IRQ and register the chip */ - if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) { - if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0) - armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO); - else - gpio_free(ARMADILLO5X0_RTC_GPIO); - } - if (armadillo5x0_i2c_rtc.irq == 0) - pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); - i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); - - /* USB */ - - usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbotg_pdata.otg) - imx31_add_mxc_ehci_otg(&usbotg_pdata); - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -static void __init armadillo5x0_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(ARMADILLO5X0, "Armadillo-500") - /* Maintainer: Alberto Panizzo */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = armadillo5x0_timer_init, - .init_machine = armadillo5x0_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c deleted file mode 100644 index 2d00476f7d2c..000000000000 --- a/arch/arm/mach-imx/mach-bug.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const unsigned int bug_pins[] __initconst = { - MX31_PIN_PC_RST__CTS5, - MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, - MX31_PIN_PC_BVD1__RXD5, -}; - -static void __init bug_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(bug_pins, - ARRAY_SIZE(bug_pins), "uart-4"); - imx31_add_imx_uart4(&uart_pdata); -} - -static void __init bug_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(BUG, "BugLabs BUGBase") - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = bug_timer_init, - .init_machine = bug_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c deleted file mode 100644 index ea50870bda80..000000000000 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (C) 2009 Eric Benard - eric@eukrea.com - * - * Based on pcm038.c which is : - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/io.h> -#include <linux/mtd/plat-ram.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx27.h" -#include "eukrea-baseboards.h" -#include "hardware.h" -#include "iomux-mx27.h" -#include "ulpi.h" - -static const int eukrea_cpuimx27_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART4 */ -#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, -#endif - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* SDHC2 */ -#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -#endif -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) - /* Quad UART's IRQ */ - GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN, - GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN, - GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN, - GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN, -#endif - /* OTG */ - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* USBH2 */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, -}; - -static struct physmap_flash_data eukrea_cpuimx27_flash_data = { - .width = 2, -}; - -static struct resource eukrea_cpuimx27_flash_resource = { - .start = 0xc0000000, - .end = 0xc3ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device eukrea_cpuimx27_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &eukrea_cpuimx27_flash_data, - }, - .num_resources = 1, - .resource = &eukrea_cpuimx27_flash_resource, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -cpuimx27_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct platform_device *platform_devices[] __initdata = { - &eukrea_cpuimx27_nor_mtd_device, -}; - -static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) -static struct plat_serial8250_port serial_platform_data[] = { - { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000), - /* irq number is run-time assigned */ - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000), - /* irq number is run-time assigned */ - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000), - /* irq number is run-time assigned */ - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000), - /* irq number is run-time assigned */ - .uartclk = 14745600, - .regshift = 1, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, - }, { - } -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_platform_data, - }, -}; -#endif - -static int eukrea_cpuimx27_otg_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = eukrea_cpuimx27_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = eukrea_cpuimx27_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init eukrea_cpuimx27_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", eukrea_cpuimx27_otg_mode); - -static void __init eukrea_cpuimx27_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins, - ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27"); - - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_mxc_nand(&cpuimx27_nand_board_info); - - i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); - - imx27_add_imx_i2c(0, &cpuimx27_i2c1_data); - - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx27_add_imx2_wdt(); - imx27_add_mxc_w1(); - -#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) - /* SDHC2 can be used for Wifi */ - imx27_add_mxc_mmc(1, NULL); -#endif -#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USEUART4) - /* in which case UART4 is also used for Bluetooth */ - imx27_add_imx_uart3(&uart_pdata); -#endif - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) - serial_platform_data[0].irq = IMX_GPIO_NR(2, 23); - serial_platform_data[1].irq = IMX_GPIO_NR(2, 22); - serial_platform_data[2].irq = IMX_GPIO_NR(2, 27); - serial_platform_data[3].irq = IMX_GPIO_NR(2, 30); - platform_device_register(&serial_device); -#endif - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } else { - imx27_add_fsl_usb2_udc(&otg_device_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); - -#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD - eukrea_mbimx27_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx27_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = eukrea_cpuimx27_timer_init, - .init_machine = eukrea_cpuimx27_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c deleted file mode 100644 index 771362d1fbee..000000000000 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * Copyright (C) 2009 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/i2c/tsc2007.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/i2c-gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx35.h" -#include "eukrea-baseboards.h" -#include "hardware.h" -#include "iomux-mx35.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data - eukrea_cpuimx35_i2c0_data __initconst = { - .bitrate = 100000, -}; - -#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2) -static int tsc2007_get_pendown_state(void) -{ - return !gpio_get_value(TSC2007_IRQGPIO); -} - -static struct tsc2007_platform_data tsc2007_info = { - .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = tsc2007_get_pendown_state, -}; - -static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("tsc2007", 0x48), - .platform_data = &tsc2007_info, - /* irq number is run-time assigned */ - }, -}; - -static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* TSC2007 IRQ */ - MX35_PAD_ATA_DA2__GPIO3_2, -}; - -static const struct mxc_nand_platform_data - eukrea_cpuimx35_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static int eukrea_cpuimx35_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static const struct mxc_usbh_platform_data otg_pdata __initconst = { - .init = eukrea_cpuimx35_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = eukrea_cpuimx35_usbh1_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -}; - -static bool otg_mode_host __initdata; - -static int __init eukrea_cpuimx35_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", eukrea_cpuimx35_otg_mode); - -/* - * Board specific initialization. - */ -static void __init eukrea_cpuimx35_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, - ARRAY_SIZE(eukrea_cpuimx35_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(); - - imx35_add_imx_uart0(&uart_pdata); - imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); - - eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO); - i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx35_i2c_devices)); - imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); - - if (otg_mode_host) - imx35_add_mxc_ehci_otg(&otg_pdata); - else - imx35_add_fsl_usb2_udc(&otg_device_pdata); - - imx35_add_mxc_ehci_hs(&usbh1_pdata); - -#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD - eukrea_mbimxsd35_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx35_timer_init(void) -{ - mx35_clocks_init(); -} - -MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") - /* Maintainer: Eukrea Electromatique */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .init_time = eukrea_cpuimx35_timer_init, - .init_machine = eukrea_cpuimx35_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c deleted file mode 100644 index 9b5ddf5bbd33..000000000000 --- a/arch/arm/mach-imx/mach-cpuimx51sd.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - * - * Copyright (C) 2010 Eric Bénard <eric@eukrea.com> - * - * based on board-mx51_babbage.c which is - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/i2c/tsc2007.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/i2c-gpio.h> -#include <linux/spi/spi.h> -#include <linux/can/platform/mcp251x.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx51.h" -#include "eukrea-baseboards.h" -#include "hardware.h" -#include "iomux-mx51.h" - -#define USBH1_RST IMX_GPIO_NR(2, 28) -#define ETH_RST IMX_GPIO_NR(2, 31) -#define TSC2007_IRQGPIO_REV2 IMX_GPIO_NR(3, 12) -#define TSC2007_IRQGPIO_REV3 IMX_GPIO_NR(4, 0) -#define CAN_IRQGPIO IMX_GPIO_NR(1, 1) -#define CAN_RST IMX_GPIO_NR(4, 15) -#define CAN_NCS IMX_GPIO_NR(4, 24) -#define CAN_RXOBF_REV2 IMX_GPIO_NR(1, 4) -#define CAN_RXOBF_REV3 IMX_GPIO_NR(3, 12) -#define CAN_RX1BF IMX_GPIO_NR(1, 6) -#define CAN_TXORTS IMX_GPIO_NR(1, 7) -#define CAN_TX1RTS IMX_GPIO_NR(1, 8) -#define CAN_TX2RTS IMX_GPIO_NR(1, 9) -#define I2C_SCL IMX_GPIO_NR(4, 16) -#define I2C_SDA IMX_GPIO_NR(4, 17) - -/* USB_CTRL_1 */ -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) - -#define MX51_USB_PLLDIV_12_MHZ 0x00 -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 -#define MX51_USB_PLL_DIV_24_MHZ 0x02 - -static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */ - - /* FEC */ - MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */ - - /* HSI2C */ - MX51_PAD_I2C1_CLK__GPIO4_16, - MX51_PAD_I2C1_DAT__GPIO4_17, - - /* I2C1 */ - MX51_PAD_SD2_CMD__I2C1_SCL, - MX51_PAD_SD2_CLK__I2C1_SDA, - - /* CAN */ - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */ - MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */ - MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */ - MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */ - MX51_PAD_GPIO1_6__GPIO1_6, - MX51_PAD_GPIO1_7__GPIO1_7, - MX51_PAD_GPIO1_8__GPIO1_8, - MX51_PAD_GPIO1_9__GPIO1_9, - - /* Touchscreen */ - /* IRQ */ - NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), - NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP | - PAD_CTL_PKE | PAD_CTL_SRE_FAST | - PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int tsc2007_get_pendown_state(void) -{ - if (mx51_revision() < IMX_CHIP_REVISION_3_0) - return !gpio_get_value(TSC2007_IRQGPIO_REV2); - else - return !gpio_get_value(TSC2007_IRQGPIO_REV3); -} - -static struct tsc2007_platform_data tsc2007_info = { - .model = 2007, - .x_plate_ohms = 180, - .get_pendown_state = tsc2007_get_pendown_state, -}; - -static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("tsc2007", 0x49), - .platform_data = &tsc2007_info, - }, -}; - -static const struct mxc_nand_platform_data - eukrea_cpuimx51sd_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -/* This function is board specific as the bit mask for the plldiv will also -be different for other Freescale SoCs, thus a common bitmask is not -possible and cannot get place in /plat-mxc/ehci.c.*/ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* The clock for the USBH1 ULPI port will come from the PHY. */ - v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, - usbother_base + MX51_USB_CTRL_1_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_ITC_NO_THRESHOLD); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -static const struct mxc_usbh_platform_data usbh1_config __initconst = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init eukrea_cpuimx51sd_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode); - -static struct i2c_gpio_platform_data pdata = { - .sda_pin = I2C_SDA, - .sda_is_open_drain = 0, - .scl_pin = I2C_SCL, - .scl_is_open_drain = 0, - .udelay = 2, -}; - -static struct platform_device hsi2c_gpio_device = { - .name = "i2c-gpio", - .id = 0, - .dev.platform_data = &pdata, -}; - -static struct mcp251x_platform_data mcp251x_info = { - .oscillator_frequency = 24E6, -}; - -static struct spi_board_info cpuimx51sd_spi_device[] = { - { - .modalias = "mcp2515", - .max_speed_hz = 10000000, - .bus_num = 0, - .mode = SPI_MODE_0, - .chip_select = 0, - .platform_data = &mcp251x_info, - /* irq number is run-time assigned */ - }, -}; - -static int cpuimx51sd_spi1_cs[] = { - CAN_NCS, -}; - -static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = { - .chipselect = cpuimx51sd_spi1_cs, - .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs), -}; - -static struct platform_device *rev2_platform_devices[] __initdata = { - &hsi2c_gpio_device, -}; - -static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = { - .bitrate = 100000, -}; - -static void __init eukrea_cpuimx51sd_init(void) -{ - imx51_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, - ARRAY_SIZE(eukrea_cpuimx51sd_pads)); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); - imx51_add_imx2_wdt(0); - - gpio_request(ETH_RST, "eth_rst"); - gpio_set_value(ETH_RST, 1); - imx51_add_fec(NULL); - - gpio_request(CAN_IRQGPIO, "can_irq"); - gpio_direction_input(CAN_IRQGPIO); - gpio_free(CAN_IRQGPIO); - gpio_request(CAN_NCS, "can_ncs"); - gpio_direction_output(CAN_NCS, 1); - gpio_free(CAN_NCS); - gpio_request(CAN_RST, "can_rst"); - gpio_direction_output(CAN_RST, 0); - msleep(20); - gpio_set_value(CAN_RST, 1); - imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata); - cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO); - spi_register_board_info(cpuimx51sd_spi_device, - ARRAY_SIZE(cpuimx51sd_spi_device)); - - if (mx51_revision() < IMX_CHIP_REVISION_3_0) { - eukrea_cpuimx51sd_i2c_devices[1].irq = - gpio_to_irq(TSC2007_IRQGPIO_REV2), - platform_add_devices(rev2_platform_devices, - ARRAY_SIZE(rev2_platform_devices)); - gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq"); - gpio_direction_input(TSC2007_IRQGPIO_REV2); - gpio_free(TSC2007_IRQGPIO_REV2); - } else { - eukrea_cpuimx51sd_i2c_devices[1].irq = - gpio_to_irq(TSC2007_IRQGPIO_REV3), - imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data); - gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq"); - gpio_direction_input(TSC2007_IRQGPIO_REV3); - gpio_free(TSC2007_IRQGPIO_REV3); - } - - i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices)); - - if (otg_mode_host) - imx51_add_mxc_ehci_otg(&dr_utmi_config); - else { - initialize_otg_port(NULL); - imx51_add_fsl_usb2_udc(&usb_pdata); - } - - gpio_request(USBH1_RST, "usb_rst"); - gpio_direction_output(USBH1_RST, 0); - msleep(20); - gpio_set_value(USBH1_RST, 1); - imx51_add_mxc_ehci_hs(1, &usbh1_config); - -#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD - eukrea_mbimxsd51_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx51sd_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") - /* Maintainer: Eric Bénard <eric@eukrea.com> */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_time = eukrea_cpuimx51sd_timer_init, - .init_machine = eukrea_cpuimx51sd_init, - .init_late = imx51_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c deleted file mode 100644 index 4bf454424249..000000000000 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> - * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx25.h" -#include "eukrea-baseboards.h" -#include "hardware.h" -#include "iomux-mx25.h" -#include "mx25.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = { - /* FEC - RMII */ - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - /* I2C1 */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, -}; - -static const struct fec_platform_data mx25_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -static const struct mxc_nand_platform_data -eukrea_cpuimx25_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static const struct imxi2c_platform_data -eukrea_cpuimx25_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -static int eukrea_cpuimx25_otg_init(struct platform_device *pdev) -{ - return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static const struct mxc_usbh_platform_data otg_pdata __initconst = { - .init = eukrea_cpuimx25_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev) -{ - return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { - .init = eukrea_cpuimx25_usbh2_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -}; - -static bool otg_mode_host __initdata; - -static int __init eukrea_cpuimx25_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", eukrea_cpuimx25_otg_mode); - -static void __init eukrea_cpuimx25_init(void) -{ - imx25_soc_init(); - - if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, - ARRAY_SIZE(eukrea_cpuimx25_pads))) - printk(KERN_ERR "error setting cpuimx25 pads !\n"); - - imx25_add_imx_uart0(&uart_pdata); - imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); - imx25_add_imxdi_rtc(); - imx25_add_fec(&mx25_fec_pdata); - imx25_add_imx2_wdt(); - - i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, - ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); - imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); - - if (otg_mode_host) - imx25_add_mxc_ehci_otg(&otg_pdata); - else - imx25_add_fsl_usb2_udc(&otg_device_pdata); - - imx25_add_mxc_ehci_hs(&usbh2_pdata); - -#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD - eukrea_mbimxsd25_baseboard_init(); -#endif -} - -static void __init eukrea_cpuimx25_timer_init(void) -{ - mx25_clocks_init(); -} - -MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") - /* Maintainer: Eukrea Electromatique */ - .atag_offset = 0x100, - .map_io = mx25_map_io, - .init_early = imx25_init_early, - .init_irq = mx25_init_irq, - .handle_irq = imx25_handle_irq, - .init_time = eukrea_cpuimx25_timer_init, - .init_machine = eukrea_cpuimx25_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx1.c b/arch/arm/mach-imx/mach-imx1.c new file mode 100644 index 000000000000..a4688f575ffe --- /dev/null +++ b/arch/arm/mach-imx/mach-imx1.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + */ + +#include <asm/mach/arch.h> + +#include "common.h" +#include "hardware.h" + +static void __init imx1_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX1); +} + +static const char * const imx1_dt_board_compat[] __initconst = { + "fsl,imx1", + NULL +}; + +DT_MACHINE_START(IMX1_DT, "Freescale i.MX1 (Device Tree Support)") + .init_early = imx1_init_early, + .dt_compat = imx1_dt_board_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx25.c b/arch/arm/mach-imx/mach-imx25.c new file mode 100644 index 000000000000..114df312a99a --- /dev/null +++ b/arch/arm/mach-imx/mach-imx25.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Pengutronix + */ + +#include <asm/mach/arch.h> +#include "common.h" +#include "hardware.h" + +static void __init imx25_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX25); +} + +static void __init imx25_dt_init(void) +{ + imx_aips_allow_unprivileged_access("fsl,imx25-aips"); +} + +static const char * const imx25_dt_board_compat[] __initconst = { + "fsl,imx25", + NULL +}; + +DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)") + .init_early = imx25_init_early, + .init_machine = imx25_dt_init, + .init_late = imx25_pm_init, + .dt_compat = imx25_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27.c b/arch/arm/mach-imx/mach-imx27.c new file mode 100644 index 000000000000..ada84fe8a1fd --- /dev/null +++ b/arch/arm/mach-imx/mach-imx27.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Pengutronix + */ + +#include <linux/init.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" +#include "hardware.h" +#include "mx27.h" + +/* MX27 memory map definition */ +static struct map_desc imx27_io_desc[] __initdata = { + /* + * this fixed mapping covers: + * - AIPI1 + * - AIPI2 + * - AITC + * - ROM Patch + * - and some reserved space + */ + imx_map_entry(MX27, AIPI, MT_DEVICE), + /* + * this fixed mapping covers: + * - CSI + * - ATA + */ + imx_map_entry(MX27, SAHB1, MT_DEVICE), + /* + * this fixed mapping covers: + * - EMI + */ + imx_map_entry(MX27, X_MEMC, MT_DEVICE), +}; + +/* + * Initialize the memory map. It is called during the + * system startup to create static physical to virtual + * memory map for the IO modules. + */ +static void __init mx27_map_io(void) +{ + iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); +} + +static void __init imx27_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX27); +} + +static const char * const imx27_dt_board_compat[] __initconst = { + "fsl,imx27", + NULL +}; + +DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_late = imx27_pm_init, + .dt_compat = imx27_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c deleted file mode 100644 index 29ac8ee651d2..000000000000 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ /dev/null @@ -1,611 +0,0 @@ -/* - * mach-imx27_visstrim_m10.c - * - * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com> - * - * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/i2c/pca953x.h> -#include <linux/input.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/leds.h> -#include <linux/platform_data/asoc-mx27vis.h> -#include <media/soc_camera.h> -#include <sound/tlv320aic32x4.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/system_info.h> -#include <asm/memblock.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -#define TVP5150_RSTN (GPIO_PORTC + 18) -#define TVP5150_PWDN (GPIO_PORTC + 19) -#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) -#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25) - -#define VERSION_MASK 0x7 -#define MOTHERBOARD_SHIFT 4 -#define EXPBOARD_SHIFT 0 - -#define MOTHERBOARD_BIT2 (GPIO_PORTD + 31) -#define MOTHERBOARD_BIT1 (GPIO_PORTD + 30) -#define MOTHERBOARD_BIT0 (GPIO_PORTD + 29) - -#define EXPBOARD_BIT2 (GPIO_PORTD + 25) -#define EXPBOARD_BIT1 (GPIO_PORTD + 27) -#define EXPBOARD_BIT0 (GPIO_PORTD + 28) - -#define AMP_GAIN_0 (GPIO_PORTF + 9) -#define AMP_GAIN_1 (GPIO_PORTF + 8) -#define AMP_MUTE_SDL (GPIO_PORTE + 5) -#define AMP_MUTE_SDR (GPIO_PORTF + 7) - -static const int visstrim_m10_pins[] __initconst = { - /* UART1 (console) */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* Both I2Cs */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* USB OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC9_PF_USBOTG_DATA0, - PC11_PF_USBOTG_DATA1, - PC10_PF_USBOTG_DATA2, - PC13_PF_USBOTG_DATA3, - PC12_PF_USBOTG_DATA4, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PE25_PF_USBOTG_DATA7, - PE24_PF_USBOTG_CLK, - PE2_PF_USBOTG_DIR, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PB23_PF_USB_PWR, - PB24_PF_USB_OC, - /* CSI */ - TVP5150_RSTN | GPIO_GPIO | GPIO_OUT, - TVP5150_PWDN | GPIO_GPIO | GPIO_OUT, - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, - /* mother board version */ - MOTHERBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - MOTHERBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - MOTHERBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - /* expansion board version */ - EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - /* Audio AMP control */ - AMP_GAIN_0 | GPIO_GPIO | GPIO_OUT, - AMP_GAIN_1 | GPIO_GPIO | GPIO_OUT, - AMP_MUTE_SDL | GPIO_GPIO | GPIO_OUT, - AMP_MUTE_SDR | GPIO_GPIO | GPIO_OUT, -}; - -static struct gpio visstrim_m10_version_gpios[] = { - { EXPBOARD_BIT0, GPIOF_IN, "exp-version-0" }, - { EXPBOARD_BIT1, GPIOF_IN, "exp-version-1" }, - { EXPBOARD_BIT2, GPIOF_IN, "exp-version-2" }, - { MOTHERBOARD_BIT0, GPIOF_IN, "mother-version-0" }, - { MOTHERBOARD_BIT1, GPIOF_IN, "mother-version-1" }, - { MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" }, -}; - -static const struct gpio visstrim_m10_gpios[] __initconst = { - { - .gpio = TVP5150_RSTN, - .flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH, - .label = "tvp5150_rstn", - }, - { - .gpio = TVP5150_PWDN, - .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW, - .label = "tvp5150_pwdn", - }, - { - .gpio = OTG_PHY_CS_GPIO, - .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW, - .label = "usbotg_cs", - }, - { - .gpio = AMP_GAIN_0, - .flags = GPIOF_DIR_OUT, - .label = "amp-gain-0", - }, - { - .gpio = AMP_GAIN_1, - .flags = GPIOF_DIR_OUT, - .label = "amp-gain-1", - }, - { - .gpio = AMP_MUTE_SDL, - .flags = GPIOF_DIR_OUT, - .label = "amp-mute-sdl", - }, - { - .gpio = AMP_MUTE_SDR, - .flags = GPIOF_DIR_OUT, - .label = "amp-mute-sdr", - }, -}; - -/* Camera */ -static int visstrim_camera_power(struct device *dev, int on) -{ - gpio_set_value(TVP5150_PWDN, on); - - return 0; -}; - -static int visstrim_camera_reset(struct device *dev) -{ - gpio_set_value(TVP5150_RSTN, 0); - ndelay(500); - gpio_set_value(TVP5150_RSTN, 1); - - return 0; -}; - -static struct i2c_board_info visstrim_i2c_camera = { - I2C_BOARD_INFO("tvp5150", 0x5d), -}; - -static struct soc_camera_link iclink_tvp5150 = { - .bus_id = 0, - .board_info = &visstrim_i2c_camera, - .i2c_adapter_id = 0, - .power = visstrim_camera_power, - .reset = visstrim_camera_reset, -}; - -static struct mx2_camera_platform_data visstrim_camera = { - .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | - MX2_CAMERA_PCLK_SAMPLE_RISING, - .clk = 100000, -}; - -static phys_addr_t mx2_camera_base __initdata; -#define MX2_CAMERA_BUF_SIZE SZ_8M - -static void __init visstrim_analog_camera_init(void) -{ - struct platform_device *pdev; - int dma; - - gpio_set_value(TVP5150_PWDN, 1); - ndelay(1); - gpio_set_value(TVP5150_RSTN, 0); - ndelay(500); - gpio_set_value(TVP5150_RSTN, 1); - ndelay(200000); - - pdev = imx27_add_mx2_camera(&visstrim_camera); - if (IS_ERR(pdev)) - return; - - dma = dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base, mx2_camera_base, - MX2_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - return; -} - -static void __init visstrim_reserve(void) -{ - /* reserve 4 MiB for mx2-camera */ - mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE); -} - -/* GPIOs used as events for applications */ -static struct gpio_keys_button visstrim_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_RESTART, - .gpio = (GPIO_PORTC + 15), - .desc = "Default config", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_RECORD, - .gpio = (GPIO_PORTF + 14), - .desc = "Record", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_STOP, - .gpio = (GPIO_PORTF + 13), - .desc = "Stop", - .active_low = 0, - .wakeup = 1, - } -}; - -static const struct gpio_keys_platform_data - visstrim_gpio_keys_platform_data __initconst = { - .buttons = visstrim_gpio_keys, - .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), -}; - -/* led */ -static const struct gpio_led visstrim_m10_leds[] __initconst = { - { - .name = "visstrim:ld0", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 29), - }, - { - .name = "visstrim:ld1", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 24), - }, - { - .name = "visstrim:ld2", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 28), - }, - { - .name = "visstrim:ld3", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 25), - }, -}; - -static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = { - .leds = visstrim_m10_leds, - .num_leds = ARRAY_SIZE(visstrim_m10_leds), -}; - -/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ -static int visstrim_m10_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); - return ret; -} - -static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data); -} - -static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { - .init = visstrim_m10_sdhc1_init, - .exit = visstrim_m10_sdhc1_exit, -}; - -/* Visstrim_SM10 NOR flash */ -static struct physmap_flash_data visstrim_m10_flash_data = { - .width = 2, -}; - -static struct resource visstrim_m10_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device visstrim_m10_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &visstrim_m10_flash_data, - }, - .num_resources = 1, - .resource = &visstrim_m10_flash_resource, -}; - -static struct platform_device *platform_devices[] __initdata = { - &visstrim_m10_nor_mtd_device, -}; - -/* Visstrim_M10 uses UART0 as console */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* I2C */ -static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { - .gpio_base = 240, /* After MX27 internal GPIOs */ - .invert = 0, -}; - -static struct aic32x4_pdata visstrim_m10_aic32x4_pdata = { - .power_cfg = AIC32X4_PWR_MICBIAS_2075_LDOIN | - AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE | - AIC32X4_PWR_AIC32X4_LDO_ENABLE | - AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 | - AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED, - .micpga_routing = AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K | - AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K, - .swapdacs = false, -}; - -static struct i2c_board_info visstrim_m10_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9555", 0x20), - .platform_data = &visstrim_m10_pca9555_pdata, - }, - { - I2C_BOARD_INFO("tlv320aic32x4", 0x18), - .platform_data = &visstrim_m10_aic32x4_pdata, - }, - { - I2C_BOARD_INFO("m41t00", 0x68), - } -}; - -/* USB OTG */ -static int otg_phy_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static const struct mxc_usbh_platform_data -visstrim_m10_usbotg_pdata __initconst = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* SSI */ -static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = { - .flags = IMX_SSI_DMA | IMX_SSI_SYN, -}; - -/* coda */ - -static void __init visstrim_coda_init(void) -{ - struct platform_device *pdev; - int dma; - - pdev = imx27_add_coda(); - dma = dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base + MX2_CAMERA_BUF_SIZE, - mx2_camera_base + MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - return; -} - -/* DMA deinterlace */ -static struct platform_device visstrim_deinterlace = { - .name = "m2m-deinterlace", - .id = 0, -}; - -static void __init visstrim_deinterlace_init(void) -{ - int ret = -ENOMEM; - struct platform_device *pdev = &visstrim_deinterlace; - int dma; - - ret = platform_device_register(pdev); - - dma = dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE, - mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - return; -} - -/* Emma-PrP for format conversion */ -static void __init visstrim_emmaprp_init(void) -{ - struct platform_device *pdev; - int dma; - - pdev = imx27_add_mx2_emmaprp(); - if (IS_ERR(pdev)) - return; - - /* - * Use the same memory area as the analog camera since both - * devices are, by nature, exclusive. - */ - dma = dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base, mx2_camera_base, - MX2_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - pr_err("Failed to declare memory for emmaprp\n"); -} - -/* Audio */ -static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = { - .amp_gain0_gpio = AMP_GAIN_0, - .amp_gain1_gpio = AMP_GAIN_1, - .amp_mutel_gpio = AMP_MUTE_SDL, - .amp_muter_gpio = AMP_MUTE_SDR, -}; - -static void __init visstrim_m10_revision(void) -{ - int exp_version = 0; - int mo_version = 0; - int ret; - - ret = gpio_request_array(visstrim_m10_version_gpios, - ARRAY_SIZE(visstrim_m10_version_gpios)); - if (ret) { - pr_err("Failed to request version gpios"); - return; - } - - /* Get expansion board version (negative logic) */ - exp_version |= !gpio_get_value(EXPBOARD_BIT2) << 2; - exp_version |= !gpio_get_value(EXPBOARD_BIT1) << 1; - exp_version |= !gpio_get_value(EXPBOARD_BIT0); - - /* Get mother board version (negative logic) */ - mo_version |= !gpio_get_value(MOTHERBOARD_BIT2) << 2; - mo_version |= !gpio_get_value(MOTHERBOARD_BIT1) << 1; - mo_version |= !gpio_get_value(MOTHERBOARD_BIT0); - - system_rev = 0x27000; - system_rev |= (mo_version << MOTHERBOARD_SHIFT); - system_rev |= (exp_version << EXPBOARD_SHIFT); -} - -static void __init visstrim_m10_board_init(void) -{ - int ret; - int mo_version; - - imx27_soc_init(); - visstrim_m10_revision(); - - ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, - ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); - if (ret) - pr_err("Failed to setup pins (%d)\n", ret); - - ret = gpio_request_array(visstrim_m10_gpios, - ARRAY_SIZE(visstrim_m10_gpios)); - if (ret) - pr_err("Failed to request gpios (%d)\n", ret); - - imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata); - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); - imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); - i2c_register_board_info(0, visstrim_m10_i2c_devices, - ARRAY_SIZE(visstrim_m10_i2c_devices)); - - imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); - imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); - imx27_add_fec(NULL); - imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata, - sizeof(snd_mx27vis_pdata)); - platform_device_register_resndata(NULL, "soc-camera-pdrv", 0, NULL, 0, - &iclink_tvp5150, sizeof(iclink_tvp5150)); - gpio_led_register_device(0, &visstrim_m10_led_data); - - /* Use mother board version to decide what video devices we shall use */ - mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK; - if (mo_version & 0x1) { - visstrim_emmaprp_init(); - - /* - * Despite not being used, tvp5150 must be - * powered on to avoid I2C problems. To minimize - * power consupmtion keep reset enabled. - */ - gpio_set_value(TVP5150_PWDN, 1); - ndelay(1); - gpio_set_value(TVP5150_RSTN, 0); - } else { - visstrim_deinterlace_init(); - visstrim_analog_camera_init(); - } - visstrim_coda_init(); -} - -static void __init visstrim_m10_timer_init(void) -{ - mx27_clocks_init((unsigned long)25000000); -} - -MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") - .atag_offset = 0x100, - .reserve = visstrim_reserve, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = visstrim_m10_timer_init, - .init_machine = visstrim_m10_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c deleted file mode 100644 index 1a851aea6832..000000000000 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "hardware.h" -#include "common.h" -#include "devices-imx27.h" -#include "iomux-mx27.h" - -static const int mx27ipcam_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, -}; - -static void __init mx27ipcam_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins), - "mx27ipcam"); - - imx27_add_imx_uart0(NULL); - imx27_add_fec(NULL); - imx27_add_imx2_wdt(); -} - -static void __init mx27ipcam_timer_init(void) -{ - mx27_clocks_init(25000000); -} - -MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = mx27ipcam_timer_init, - .init_machine = mx27ipcam_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c deleted file mode 100644 index 3da2e3e44ce9..000000000000 --- a/arch/arm/mach-imx/mach-imx27lite.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -static const int mx27lite_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mx27lite_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), - "imx27lite"); - imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); -} - -static void __init mx27lite_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = mx27lite_timer_init, - .init_machine = mx27lite_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx31.c b/arch/arm/mach-imx/mach-imx31.c new file mode 100644 index 000000000000..e9a1092b6093 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx31.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Pengutronix + */ + +#include <asm/mach/arch.h> +#include "common.h" + +static const char * const imx31_dt_board_compat[] __initconst = { + "fsl,imx31", + NULL +}; + +DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .dt_compat = imx31_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx35.c b/arch/arm/mach-imx/mach-imx35.c new file mode 100644 index 000000000000..35dbc719fb6d --- /dev/null +++ b/arch/arm/mach-imx/mach-imx35.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2012 Steffen Trumtrar, Pengutronix + * + * based on imx27-dt.c + */ + +#include <asm/mach/arch.h> +#include "common.h" +#include "mx35.h" + +static const char * const imx35_dt_board_compat[] __initconst = { + "fsl,imx35", + NULL +}; + +DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, + .map_io = mx35_map_io, + .init_early = imx35_init_early, + .dt_compat = imx35_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c new file mode 100644 index 000000000000..9dc9d0ae9342 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx50.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Greg Ungerer <gerg@uclinux.org> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Linaro Ltd. + */ + +#include <asm/mach/arch.h> + +#include "common.h" +#include "hardware.h" + +static void __init imx50_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX50); +} + +static const char * const imx50_dt_board_compat[] __initconst = { + "fsl,imx50", + NULL +}; + +DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") + .init_early = imx50_init_early, + .dt_compat = imx50_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c new file mode 100644 index 000000000000..510801f6f71c --- /dev/null +++ b/arch/arm/mach-imx/mach-imx51.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011 Linaro Ltd. + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "hardware.h" + +static void __init imx51_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX51); +} + +/* + * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by + * the Freescale marketing division. However this did not remove the + * hardware from the chip which still needs to be configured for proper + * IPU support. + */ +#define MX51_MIPI_HSC_BASE 0x83fdc000 +static void __init imx51_ipu_mipi_setup(void) +{ + void __iomem *hsc_addr; + + hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K); + WARN_ON(!hsc_addr); + + /* setup MIPI module to legacy mode */ + imx_writel(0xf00, hsc_addr); + + /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ + imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); + + iounmap(hsc_addr); +} + +static void __init imx51_m4if_setup(void) +{ + void __iomem *m4if_base; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if"); + if (!np) + return; + + m4if_base = of_iomap(np, 0); + of_node_put(np); + if (!m4if_base) { + pr_err("Unable to map M4IF registers\n"); + return; + } + + /* + * Configure VPU and IPU with higher priorities + * in order to avoid artifacts during video playback + */ + writel_relaxed(0x00000203, m4if_base + 0x40); + writel_relaxed(0x00000000, m4if_base + 0x44); + writel_relaxed(0x00120125, m4if_base + 0x9c); + writel_relaxed(0x001901A3, m4if_base + 0x48); + iounmap(m4if_base); +} + +static void __init imx51_dt_init(void) +{ + imx51_ipu_mipi_setup(); + imx_src_init(); + imx51_m4if_setup(); + imx5_pmu_init(); + imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); +} + +static void __init imx51_init_late(void) +{ + mx51_neon_fixup(); + imx51_pm_init(); +} + +static const char * const imx51_dt_board_compat[] __initconst = { + "fsl,imx51", + NULL +}; + +DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") + .init_early = imx51_init_early, + .init_machine = imx51_dt_init, + .init_late = imx51_init_late, + .dt_compat = imx51_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c index 98c58944015a..6622406e0081 100644 --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -1,54 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/mach/time.h> #include "common.h" #include "hardware.h" -#include "mx53.h" + +static void __init imx53_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX53); +} static void __init imx53_dt_init(void) { - mxc_arch_reset_init_dt(); + imx_src_init(); + imx5_pmu_init(); + imx_aips_allow_unprivileged_access("fsl,imx53-aipstz"); +} - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +static void __init imx53_init_late(void) +{ + imx53_pm_init(); } -static const char *imx53_dt_board_compat[] __initdata = { +static const char * const imx53_dt_board_compat[] __initconst = { "fsl,imx53", NULL }; -static void __init imx53_timer_init(void) -{ - mx53_clocks_init_dt(); -} - DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)") - .map_io = mx53_map_io, .init_early = imx53_init_early, - .init_irq = mx53_init_irq, - .handle_irq = imx53_handle_irq, - .init_time = imx53_timer_init, .init_machine = imx53_dt_init, .init_late = imx53_init_late, .dt_compat = imx53_dt_board_compat, - .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 7be13f8e69a0..7f6200925752 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -1,294 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011-2013 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/clkdev.h> -#include <linux/clocksource.h> -#include <linux/cpu.h> -#include <linux/delay.h> -#include <linux/export.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irq.h> #include <linux/irqchip.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/opp.h> +#include <linux/pci.h> #include <linux/phy.h> -#include <linux/reboot.h> #include <linux/regmap.h> #include <linux/micrel_phy.h> #include <linux/mfd/syscon.h> -#include <asm/hardware/cache-l2x0.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/system_misc.h> #include "common.h" #include "cpuidle.h" #include "hardware.h" -static u32 chip_revision; - -int imx6q_revision(void) -{ - return chip_revision; -} - -static void __init imx6q_init_revision(void) -{ - u32 rev = imx_anatop_get_digprog(); - - switch (rev & 0xff) { - case 0: - chip_revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - chip_revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - chip_revision = IMX_CHIP_REVISION_1_2; - break; - default: - chip_revision = IMX_CHIP_REVISION_UNKNOWN; - } - - mxc_set_cpu_type(rev >> 16 & 0xff); -} - -static void imx6q_restart(enum reboot_mode mode, const char *cmd) -{ - struct device_node *np; - void __iomem *wdog_base; - - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); - wdog_base = of_iomap(np, 0); - if (!wdog_base) - goto soft; - - imx_src_prepare_restart(); - - /* enable wdog */ - writew_relaxed(1 << 2, wdog_base); - /* write twice to ensure the request will not get ignored */ - writew_relaxed(1 << 2, wdog_base); - - /* wait for reset to assert ... */ - mdelay(500); - - pr_err("Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); - -soft: - /* we'll take a jump through zero as a poor second */ - soft_restart(0); -} - /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { if (IS_BUILTIN(CONFIG_PHYLIB)) { /* min rx data delay */ - phy_write(phydev, 0x0b, 0x8105); - phy_write(phydev, 0x0c, 0x0000); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); /* max rx/tx clock delay, min rx/tx control delay */ - phy_write(phydev, 0x0b, 0x8104); - phy_write(phydev, 0x0c, 0xf0f0); - phy_write(phydev, 0x0b, 0x104); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); + phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); + phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, + MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW); } return 0; } -static void __init imx6q_sabrelite_cko1_setup(void) +/* + * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High + * as they are used for slots1-7 PERST# + */ +static void ventana_pciesw_early_fixup(struct pci_dev *dev) { - struct clk *cko1_sel, *ahb, *cko1; - unsigned long rate; - - cko1_sel = clk_get_sys(NULL, "cko1_sel"); - ahb = clk_get_sys(NULL, "ahb"); - cko1 = clk_get_sys(NULL, "cko1"); - if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) { - pr_err("cko1 setup failed!\n"); - goto put_clk; - } - clk_set_parent(cko1_sel, ahb); - rate = clk_round_rate(cko1, 16000000); - clk_set_rate(cko1, rate); -put_clk: - if (!IS_ERR(cko1_sel)) - clk_put(cko1_sel); - if (!IS_ERR(ahb)) - clk_put(ahb); - if (!IS_ERR(cko1)) - clk_put(cko1); -} + u32 dw; -static void __init imx6q_sabrelite_init(void) -{ - if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, - ksz9021rn_phy_fixup); - imx6q_sabrelite_cko1_setup(); -} + if (!of_machine_is_compatible("gw,ventana")) + return; -static void __init imx6q_sabresd_cko1_setup(void) -{ - struct clk *cko1_sel, *pll4, *pll4_post, *cko1; - unsigned long rate; - - cko1_sel = clk_get_sys(NULL, "cko1_sel"); - pll4 = clk_get_sys(NULL, "pll4_audio"); - pll4_post = clk_get_sys(NULL, "pll4_post_div"); - cko1 = clk_get_sys(NULL, "cko1"); - if (IS_ERR(cko1_sel) || IS_ERR(pll4) - || IS_ERR(pll4_post) || IS_ERR(cko1)) { - pr_err("cko1 setup failed!\n"); - goto put_clk; - } - /* - * Setting pll4 at 768MHz (24MHz * 32) - * So its child clock can get 24MHz easily - */ - clk_set_rate(pll4, 768000000); - - clk_set_parent(cko1_sel, pll4_post); - rate = clk_round_rate(cko1, 24000000); - clk_set_rate(cko1, rate); -put_clk: - if (!IS_ERR(cko1_sel)) - clk_put(cko1_sel); - if (!IS_ERR(pll4_post)) - clk_put(pll4_post); - if (!IS_ERR(pll4)) - clk_put(pll4); - if (!IS_ERR(cko1)) - clk_put(cko1); -} + if (dev->devfn != 0) + return; -static void __init imx6q_sabresd_init(void) -{ - imx6q_sabresd_cko1_setup(); -} + pci_read_config_dword(dev, 0x62c, &dw); + dw |= 0xaaa8; // GPIO1-7 outputs + pci_write_config_dword(dev, 0x62c, dw); -static void __init imx6q_1588_init(void) -{ - struct regmap *gpr; - - gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); - if (!IS_ERR(gpr)) - regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); - else - pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); + pci_read_config_dword(dev, 0x644, &dw); + dw |= 0xfe; // GPIO1-7 output high + pci_write_config_dword(dev, 0x644, dw); + msleep(100); } -static void __init imx6q_usb_init(void) -{ - imx_anatop_usb_chrg_detect_disable(); -} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); -static void __init imx6q_init_machine(void) +static void __init imx6q_enet_phy_init(void) { - if (of_machine_is_compatible("fsl,imx6q-sabrelite")) - imx6q_sabrelite_init(); - else if (of_machine_is_compatible("fsl,imx6q-sabresd") || - of_machine_is_compatible("fsl,imx6dl-sabresd")) - imx6q_sabresd_init(); - - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - - imx_anatop_init(); - imx6q_pm_init(); - imx6q_usb_init(); - imx6q_1588_init(); + if (IS_BUILTIN(CONFIG_PHYLIB)) { + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + } } -#define OCOTP_CFG3 0x440 -#define OCOTP_CFG3_SPEED_SHIFT 16 -#define OCOTP_CFG3_SPEED_1P2GHZ 0x3 - -static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev) +static void __init imx6q_1588_init(void) { struct device_node *np; - void __iomem *base; - u32 val; + struct clk *ptp_clk, *fec_enet_ref; + struct clk *enet_ref; + struct regmap *gpr; + u32 clksel; - np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); if (!np) { - pr_warn("failed to find ocotp node\n"); + pr_warn("%s: failed to find fec node\n", __func__); return; } - base = of_iomap(np, 0); - if (!base) { - pr_warn("failed to map ocotp\n"); + /* + * If enet_clk_ref configured, we assume DT did it properly and . + * clk-imx6q.c will do needed configuration. + */ + fec_enet_ref = of_clk_get_by_name(np, "enet_clk_ref"); + if (!IS_ERR(fec_enet_ref)) + goto put_node; + + ptp_clk = of_clk_get(np, 2); + if (IS_ERR(ptp_clk)) { + pr_warn("%s: failed to get ptp clock\n", __func__); goto put_node; } - val = readl_relaxed(base + OCOTP_CFG3); - val >>= OCOTP_CFG3_SPEED_SHIFT; - if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ) - if (opp_disable(cpu_dev, 1200000000)) - pr_warn("failed to disable 1.2 GHz OPP\n"); + enet_ref = clk_get_sys(NULL, "enet_ref"); + if (IS_ERR(enet_ref)) { + pr_warn("%s: failed to get enet clock\n", __func__); + goto put_ptp_clk; + } + + /* + * If enet_ref from ANATOP/CCM is the PTP clock source, we need to + * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad + * (external OSC), and we need to clear the bit. + */ + clksel = clk_is_match(ptp_clk, enet_ref) ? + IMX6Q_GPR1_ENET_CLK_SEL_ANATOP : + IMX6Q_GPR1_ENET_CLK_SEL_PAD; + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6Q_GPR1_ENET_CLK_SEL_MASK, + clksel); + else + pr_err("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); + clk_put(enet_ref); +put_ptp_clk: + clk_put(ptp_clk); put_node: of_node_put(np); } -static void __init imx6q_opp_init(struct device *cpu_dev) +static void __init imx6q_axi_init(void) { - struct device_node *np; + struct regmap *gpr; + unsigned int mask; - np = of_find_node_by_path("/cpus/cpu@0"); - if (!np) { - pr_warn("failed to find cpu0 node\n"); - return; + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + /* + * Enable the cacheable attribute of VPU and IPU + * AXI transactions. + */ + mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL | + IMX6Q_GPR4_VPU_RD_CACHE_SEL | + IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | + IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK | + IMX6Q_GPR4_IPU_WR_CACHE_CTL | + IMX6Q_GPR4_IPU_RD_CACHE_CTL; + regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask); + + /* Increase IPU read QoS priority */ + regmap_update_bits(gpr, IOMUXC_GPR6, + IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | + IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + regmap_update_bits(gpr, IOMUXC_GPR7, + IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | + IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK, + (0xf << 16) | (0x7 << 20)); + } else { + pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n"); } +} - cpu_dev->of_node = np; - if (of_init_opp_table(cpu_dev)) { - pr_warn("failed to init OPP table\n"); - goto put_node; - } +static void __init imx6q_init_machine(void) +{ + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + /* + * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. + * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), + * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. + */ + imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10); + else + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", + imx_get_soc_revision()); - imx6q_opp_check_1p2ghz(cpu_dev); + imx6q_enet_phy_init(); -put_node: - of_node_put(np); -} + of_platform_default_populate(NULL, NULL, NULL); -static struct platform_device imx6q_cpufreq_pdev = { - .name = "imx6q-cpufreq", -}; + imx_anatop_init(); + cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); + imx6q_1588_init(); + imx6q_axi_init(); +} static void __init imx6q_init_late(void) { /* - * WAIT mode is broken on TO 1.0 and 1.1, so there is no point - * to run cpuidle on them. + * WAIT mode is broken on imx6 Dual/Quad revision 1.0 and 1.1 so + * there is no point to run cpuidle on them. + * + * It does work on imx6 Solo/DualLite starting from 1.1 */ - if (imx6q_revision() > IMX_CHIP_REVISION_1_1) + if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) || + (cpu_is_imx6dl() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0)) imx6q_cpuidle_init(); - if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { - imx6q_opp_init(&imx6q_cpufreq_pdev.dev); - platform_device_register(&imx6q_cpufreq_pdev); - } + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) + platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); } static void __init imx6q_map_io(void) @@ -297,70 +211,30 @@ static void __init imx6q_map_io(void) imx_scu_map_io(); } -#ifdef CONFIG_CACHE_L2X0 -static void __init imx6q_init_l2cache(void) -{ - void __iomem *l2x0_base; - struct device_node *np; - unsigned int val; - - np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); - if (!np) - goto out; - - l2x0_base = of_iomap(np, 0); - if (!l2x0_base) { - of_node_put(np); - goto out; - } - - /* Configure the L2 PREFETCH and POWER registers */ - val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); - val |= 0x70800000; - writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); - val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; - writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); - - iounmap(l2x0_base); - of_node_put(np); - -out: - l2x0_of_init(0, ~0UL); -} -#else -static inline void imx6q_init_l2cache(void) {} -#endif - static void __init imx6q_init_irq(void) { - imx6q_init_revision(); - imx6q_init_l2cache(); + imx_gpc_check_dt(); + imx_init_revision_from_anatop(); + imx_init_l2cache(); imx_src_init(); - imx_gpc_init(); irqchip_init(); + imx6_pm_ccm_init("fsl,imx6q-ccm"); } -static void __init imx6q_timer_init(void) -{ - of_clk_init(NULL); - clocksource_of_init(); - imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx6q_revision()); -} - -static const char *imx6q_dt_compat[] __initdata = { +static const char * const imx6q_dt_compat[] __initconst = { "fsl,imx6dl", "fsl,imx6q", + "fsl,imx6qp", NULL, }; DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, - .init_time = imx6q_timer_init, .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, - .restart = imx6q_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 132db2609507..f6e87363d605 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -1,52 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ -#include <linux/clk-provider.h> #include <linux/irqchip.h> -#include <linux/of.h> #include <linux/of_platform.h> -#include <asm/hardware/cache-l2x0.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/regmap.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +static void __init imx6sl_fec_init(void) +{ + struct regmap *gpr; + + /* set FEC clock from internal PLL clock source */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, + IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0); + } else { + pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n"); + } +} + +static void __init imx6sl_init_late(void) +{ + /* imx6sl reuses imx6q cpufreq driver */ + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) + platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); + + if (IS_ENABLED(CONFIG_SOC_IMX6SL) && cpu_is_imx6sl()) + imx6sl_cpuidle_init(); + else if (IS_ENABLED(CONFIG_SOC_IMX6SLL)) + imx6sx_cpuidle_init(); +} static void __init imx6sl_init_machine(void) { - mxc_arch_reset_init_dt(); + of_platform_default_populate(NULL, NULL, NULL); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + if (cpu_is_imx6sl()) + imx6sl_fec_init(); + imx_anatop_init(); + imx6sl_pm_init(); } static void __init imx6sl_init_irq(void) { - l2x0_of_init(0, ~0UL); + imx_gpc_check_dt(); + imx_init_revision_from_anatop(); + imx_init_l2cache(); imx_src_init(); - imx_gpc_init(); irqchip_init(); + if (cpu_is_imx6sl()) + imx6_pm_ccm_init("fsl,imx6sl-ccm"); + else + imx6_pm_ccm_init("fsl,imx6sll-ccm"); } -static void __init imx6sl_timer_init(void) -{ - of_clk_init(NULL); -} - -static const char *imx6sl_dt_compat[] __initdata = { +static const char * const imx6sl_dt_compat[] __initconst = { "fsl,imx6sl", + "fsl,imx6sll", NULL, }; DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") - .map_io = debug_ll_io_init, + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_irq = imx6sl_init_irq, - .init_time = imx6sl_timer_init, .init_machine = imx6sl_init_machine, + .init_late = imx6sl_init_late, .dt_compat = imx6sl_dt_compat, - .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c new file mode 100644 index 000000000000..3feb31ab556e --- /dev/null +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <linux/irqchip.h> +#include <linux/of_platform.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "cpuidle.h" + +static void __init imx6sx_init_machine(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + imx_anatop_init(); + imx6sx_pm_init(); +} + +static void __init imx6sx_init_irq(void) +{ + imx_gpc_check_dt(); + imx_init_revision_from_anatop(); + imx_init_l2cache(); + imx_src_init(); + irqchip_init(); + imx6_pm_ccm_init("fsl,imx6sx-ccm"); +} + +static void __init imx6sx_init_late(void) +{ + imx6sx_cpuidle_init(); + + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) + platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); +} + +static const char * const imx6sx_dt_compat[] __initconst = { + "fsl,imx6sx", + NULL, +}; + +DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, + .init_irq = imx6sx_init_irq, + .init_machine = imx6sx_init_machine, + .dt_compat = imx6sx_dt_compat, + .init_late = imx6sx_init_late, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c new file mode 100644 index 000000000000..cb6d29c2bb5f --- /dev/null +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ +#include <linux/irqchip.h> +#include <linux/of_platform.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +static void __init imx6ul_init_machine(void) +{ + imx_print_silicon_rev(cpu_is_imx6ull() ? "i.MX6ULL" : "i.MX6UL", + imx_get_soc_revision()); + + of_platform_default_populate(NULL, NULL, NULL); + imx_anatop_init(); + imx6ul_pm_init(); +} + +static void __init imx6ul_init_irq(void) +{ + imx_init_revision_from_anatop(); + imx_src_init(); + irqchip_init(); + imx6_pm_ccm_init("fsl,imx6ul-ccm"); +} + +static void __init imx6ul_init_late(void) +{ + imx6sx_cpuidle_init(); + + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) + platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); +} + +static const char * const imx6ul_dt_compat[] __initconst = { + "fsl,imx6ul", + "fsl,imx6ull", + "fsl,imx6ulz", + NULL, +}; + +DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)") + .init_irq = imx6ul_init_irq, + .init_machine = imx6ul_init_machine, + .init_late = imx6ul_init_late, + .dt_compat = imx6ul_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx7d-cm4.c b/arch/arm/mach-imx/mach-imx7d-cm4.c new file mode 100644 index 000000000000..0800b5891d2a --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7d-cm4.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> + */ + +#include <linux/kernel.h> +#include <asm/v7m.h> +#include <asm/mach/arch.h> + +static const char * const imx7d_cm4_dt_compat[] __initconst = { + "fsl,imx7d-cm4", + NULL, +}; + +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)") + .dt_compat = imx7d_cm4_dt_compat, + .restart = armv7m_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c new file mode 100644 index 000000000000..87632ae0201c --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + */ +#include <linux/irqchip.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx7-iomuxc-gpr.h> +#include <linux/platform_device.h> +#include <linux/phy.h> +#include <linux/regmap.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" + +static int bcm54220_phy_fixup(struct phy_device *dev) +{ + /* enable RXC skew select RGMII copper mode */ + phy_write(dev, 0x1e, 0x21); + phy_write(dev, 0x1f, 0x7ea8); + phy_write(dev, 0x1e, 0x2f); + phy_write(dev, 0x1f, 0x71b7); + + return 0; +} + +#define PHY_ID_BCM54220 0x600d8589 + +static void __init imx7d_enet_phy_init(void) +{ + if (IS_BUILTIN(CONFIG_PHYLIB)) { + phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff, + bcm54220_phy_fixup); + } +} + +static void __init imx7d_enet_clk_sel(void) +{ + struct regmap *gpr; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); + } else { + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); + } +} + +static void __init imx7d_enet_init(void) +{ + imx7d_enet_phy_init(); + imx7d_enet_clk_sel(); +} + +static void __init imx7d_init_machine(void) +{ + imx_anatop_init(); + imx7d_enet_init(); +} + +static void __init imx7d_init_late(void) +{ + if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) + platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); +} + +static void __init imx7d_init_irq(void) +{ + imx_init_revision_from_anatop(); + imx7_src_init(); + irqchip_init(); +} + +static const char *const imx7d_dt_compat[] __initconst = { + "fsl,imx7d", + "fsl,imx7s", + NULL, +}; + +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") + .smp = smp_ops(imx7_smp_ops), + .init_irq = imx7d_init_irq, + .init_machine = imx7d_init_machine, + .init_late = imx7d_init_late, + .dt_compat = imx7d_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c new file mode 100644 index 000000000000..a3c8dadec1c5 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Author: Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <linux/irqchip.h> +#include <linux/mfd/syscon.h> +#include <linux/of_platform.h> +#include <linux/regmap.h> +#include <asm/mach/arch.h> + +#include "common.h" +#include "cpuidle.h" +#include "hardware.h" + +#define SIM_JTAG_ID_REG 0x8c + +static void __init imx7ulp_set_revision(void) +{ + struct regmap *sim; + u32 revision; + + sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim"); + if (IS_ERR(sim)) { + pr_warn("failed to find fsl,imx7ulp-sim regmap!\n"); + return; + } + + if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) { + pr_warn("failed to read sim regmap!\n"); + return; + } + + /* + * bit[31:28] of JTAG_ID register defines revision as below from B0: + * 0001 B0 + * 0010 B1 + * 0011 B2 + */ + switch (revision >> 28) { + case 1: + imx_set_soc_revision(IMX_CHIP_REVISION_2_0); + break; + case 2: + imx_set_soc_revision(IMX_CHIP_REVISION_2_1); + break; + case 3: + imx_set_soc_revision(IMX_CHIP_REVISION_2_2); + break; + default: + imx_set_soc_revision(IMX_CHIP_REVISION_1_0); + break; + } +} + +static void __init imx7ulp_init_machine(void) +{ + imx7ulp_pm_init(); + + mxc_set_cpu_type(MXC_CPU_IMX7ULP); + imx7ulp_set_revision(); + of_platform_default_populate(NULL, NULL, NULL); +} + +static const char *const imx7ulp_dt_compat[] __initconst = { + "fsl,imx7ulp", + NULL, +}; + +static void __init imx7ulp_init_late(void) +{ + if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) + platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); + + imx7ulp_cpuidle_init(); +} + +DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") + .init_machine = imx7ulp_init_machine, + .dt_compat = imx7ulp_dt_compat, + .init_late = imx7ulp_init_late, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c new file mode 100644 index 000000000000..2063a3059c84 --- /dev/null +++ b/arch/arm/mach-imx/mach-imxrt.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#include <linux/kernel.h> +#include <asm/mach/arch.h> +#include <asm/v7m.h> + +static const char *const imxrt_compat[] __initconst = { + "fsl,imxrt1050", + NULL +}; + +DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)") + .dt_compat = imxrt_compat, + .restart = armv7m_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c deleted file mode 100644 index c7bc41d6b468..000000000000 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * KZM-ARM11-01 support - * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> - * - * based on code for MX31ADS, - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/smsc911x.h> -#include <linux/types.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/irq.h> -#include <asm/mach-types.h> -#include <asm/memory.h> -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ - IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ - IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \ - MX31_IO_ADDRESS(x)) - -/* - * KZM-ARM11-01 Board Control Registers on FPGA - */ -#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) - -/* - * External UART for touch panel on FPGA - */ -#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) - -#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) -/* - * KZM-ARM11-01 has an external UART on FPGA - */ -static struct plat_serial8250_port serial_platform_data[] = { - { - .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550), - .mapbase = KZM_ARM11_16550, - /* irq number is run-time assigned */ - .irqflags = IRQ_TYPE_EDGE_RISING, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_BUGGY_UART, - }, - {}, -}; - -static struct resource serial8250_resources[] = { - { - .start = KZM_ARM11_16550, - .end = KZM_ARM11_16550 + 0x10, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, - .num_resources = ARRAY_SIZE(serial8250_resources), - .resource = serial8250_resources, -}; - -static int __init kzm_init_ext_uart(void) -{ - u8 tmp; - - /* - * GPIO 1-1: external UART interrupt line - */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* - * Unmask UART interrupt - */ - tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); - tmp |= 0x2; - __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); - - serial_platform_data[0].irq = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - serial8250_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - serial8250_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - return platform_device_register(&serial_device); -} -#else -static inline int kzm_init_ext_uart(void) -{ - return 0; -} -#endif - -/* - * SMSC LAN9118 - */ -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -static struct smsc911x_platform_config kzm_smsc9118_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, -}; - -static struct resource kzm_smsc9118_resources[] = { - { - .start = MX31_CS5_BASE_ADDR, - .end = MX31_CS5_BASE_ADDR + SZ_128K - 1, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device kzm_smsc9118_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(kzm_smsc9118_resources), - .resource = kzm_smsc9118_resources, - .dev = { - .platform_data = &kzm_smsc9118_config, - }, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static int __init kzm_init_smsc9118(void) -{ - /* - * GPIO 1-2: SMSC9118 interrupt line - */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - kzm_smsc9118_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - kzm_smsc9118_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - - return platform_device_register(&kzm_smsc9118_device); -} -#else -static inline int kzm_init_smsc9118(void) -{ - return 0; -} -#endif - -#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init kzm_init_imx_uart(void) -{ - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); -} -#else -static inline void kzm_init_imx_uart(void) -{ -} -#endif - -static int kzm_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_DCD_DCE1__DCD_DCE1, - MX31_PIN_RI_DCE1__RI_DCE1, - MX31_PIN_DSR_DCE1__DSR_DCE1, - MX31_PIN_DTR_DCE1__DTR_DCE1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_DCD_DTE1__DCD_DTE2, - MX31_PIN_RI_DTE1__RI_DTE2, - MX31_PIN_DSR_DTE1__DSR_DTE2, - MX31_PIN_DTR_DTE1__DTR_DTE2, -}; - -/* - * Board specific initialization. - */ -static void __init kzm_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(kzm_pins, - ARRAY_SIZE(kzm_pins), "kzm"); - kzm_init_ext_uart(); - kzm_init_smsc9118(); - kzm_init_imx_uart(); - - pr_info("Clock input source is 26MHz\n"); -} - -/* - * This structure defines static mappings for the kzm-arm11-01 board. - */ -static struct map_desc kzm_io_desc[] __initdata = { - { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = MX31_CS4_SIZE, - .type = MT_DEVICE - }, - { - .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), - .length = MX31_CS5_SIZE, - .type = MT_DEVICE - }, -}; - -/* - * Set up static virtual mappings. - */ -static void __init kzm_map_io(void) -{ - mx31_map_io(); - iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc)); -} - -static void __init kzm_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") - .atag_offset = 0x100, - .map_io = kzm_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = kzm_timer_init, - .init_machine = kzm_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c new file mode 100644 index 000000000000..0034359a9b4f --- /dev/null +++ b/arch/arm/mach-imx/mach-ls1021a.c @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + */ + +#include <asm/mach/arch.h> + +#include "common.h" + +static const char * const ls1021a_dt_compat[] __initconst = { + "fsl,ls1021a", + NULL, +}; + +DT_MACHINE_START(LS1021A, "Freescale LS1021A") + .smp = smp_ops(ls1021a_smp_ops), + .dt_compat = ls1021a_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c deleted file mode 100644 index 9f883e4d6fc9..000000000000 --- a/arch/arm/mach-imx/mach-mx1ads.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * arch/arm/mach-imx/mach-mx1ads.c - * - * Initially based on: - * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c - * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de> - * - * 2004 (c) MontaVista Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/i2c.h> -#include <linux/i2c/pcf857x.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx1.h" -#include "hardware.h" -#include "iomux-mx1.h" - -static const int mx1ads_pins[] __initconst = { - /* UART1 */ - PC9_PF_UART1_CTS, - PC10_PF_UART1_RTS, - PC11_PF_UART1_TXD, - PC12_PF_UART1_RXD, - /* UART2 */ - PB28_PF_UART2_CTS, - PB29_PF_UART2_RTS, - PB30_PF_UART2_TXD, - PB31_PF_UART2_RXD, - /* I2C */ - PA15_PF_I2C_SDA, - PA16_PF_I2C_SCL, - /* SPI */ - PC13_PF_SPI1_SPI_RDY, - PC14_PF_SPI1_SCLK, - PC15_PF_SPI1_SS, - PC16_PF_SPI1_MISO, - PC17_PF_SPI1_MOSI, -}; - -/* - * UARTs platform data - */ - -static const struct imxuart_platform_data uart0_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxuart_platform_data uart1_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* - * Physmap flash - */ - -static const struct physmap_flash_data mx1ads_flash_data __initconst = { - .width = 4, /* bankwidth in bytes */ -}; - -static const struct resource flash_resource __initconst = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -/* - * I2C - */ -static struct pcf857x_platform_data pcf857x_data[] = { - { - .gpio_base = 4 * 32, - }, { - .gpio_base = 4 * 32 + 16, - } -}; - -static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mx1ads_i2c_devices[] = { - { - I2C_BOARD_INFO("pcf8575", 0x22), - .platform_data = &pcf857x_data[0], - }, { - I2C_BOARD_INFO("pcf8575", 0x24), - .platform_data = &pcf857x_data[1], - }, -}; - -/* - * Board init - */ -static void __init mx1ads_init(void) -{ - imx1_soc_init(); - - mxc_gpio_setup_multiple_pins(mx1ads_pins, - ARRAY_SIZE(mx1ads_pins), "mx1ads"); - - /* UART */ - imx1_add_imx_uart0(&uart0_pdata); - imx1_add_imx_uart1(&uart1_pdata); - - /* Physmap flash */ - platform_device_register_resndata(NULL, "physmap-flash", 0, - &flash_resource, 1, - &mx1ads_flash_data, sizeof(mx1ads_flash_data)); - - /* I2C */ - i2c_register_board_info(0, mx1ads_i2c_devices, - ARRAY_SIZE(mx1ads_i2c_devices)); - - imx1_add_imx_i2c(&mx1ads_i2c_data); -} - -static void __init mx1ads_timer_init(void) -{ - mx1_clocks_init(32000); -} - -MACHINE_START(MX1ADS, "Freescale MX1ADS") - /* Maintainer: Sascha Hauer, Pengutronix */ - .atag_offset = 0x100, - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .init_time = mx1ads_timer_init, - .init_machine = mx1ads_init, - .restart = mxc_restart, -MACHINE_END - -MACHINE_START(MXLADS, "Freescale MXLADS") - .atag_offset = 0x100, - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .init_time = mx1ads_timer_init, - .init_machine = mx1ads_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c deleted file mode 100644 index a06aa4dc37fc..000000000000 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/physmap.h> -#include <linux/gpio.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx21.h" -#include "hardware.h" -#include "iomux-mx21.h" - -/* - * Memory-mapped I/O on MX21ADS base board - */ -#define MX21ADS_MMIO_BASE_ADDR 0xf5000000 -#define MX21ADS_MMIO_SIZE 0xc00000 - -#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \ - (MX21ADS_MMIO_BASE_ADDR + (offset)) - -#define MX21ADS_CS8900A_MMIO_SIZE 0x200000 -#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11) -#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) -#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000) -#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000) - -/* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP 0x0001 /* read */ -#define MX21ADS_IO_TP6 0x0001 /* write */ -#define MX21ADS_IO_SW_SEL 0x0002 /* read */ -#define MX21ADS_IO_TP7 0x0002 /* write */ -#define MX21ADS_IO_RESET_E_UART 0x0004 -#define MX21ADS_IO_RESET_BASE 0x0008 -#define MX21ADS_IO_CSI_CTL2 0x0010 -#define MX21ADS_IO_CSI_CTL1 0x0020 -#define MX21ADS_IO_CSI_CTL0 0x0040 -#define MX21ADS_IO_UART1_EN 0x0080 -#define MX21ADS_IO_UART4_EN 0x0100 -#define MX21ADS_IO_LCDON 0x0200 -#define MX21ADS_IO_IRDA_EN 0x0400 -#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 -#define MX21ADS_IO_IRDA_MD0_B 0x1000 -#define MX21ADS_IO_IRDA_MD1 0x2000 -#define MX21ADS_IO_LED4_ON 0x4000 -#define MX21ADS_IO_LED3_ON 0x8000 - -static const int mx21ads_pins[] __initconst = { - - /* CS8900A */ - (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), - - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - - /* UART3 (IrDA) - only TXD and RXD */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - - /* UART4 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - - /* LCDC */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA24_PF_REV, /* Sharp panel dedicated signal */ - PA25_PF_CLS, /* Sharp panel dedicated signal */ - PA26_PF_PS, /* Sharp panel dedicated signal */ - PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */ - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - - /* MMC/SDHC */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - - /* NFC */ - PF0_PF_NRFB, - PF1_PF_NFCE, - PF2_PF_NFWP, - PF3_PF_NFCLE, - PF4_PF_NFALE, - PF5_PF_NFRE, - PF6_PF_NFWE, - PF7_PF_NFIO0, - PF8_PF_NFIO1, - PF9_PF_NFIO2, - PF10_PF_NFIO3, - PF11_PF_NFIO4, - PF12_PF_NFIO5, - PF13_PF_NFIO6, - PF14_PF_NFIO7, -}; - -/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */ -static struct physmap_flash_data mx21ads_flash_data = { - .width = 4, -}; - -static struct resource mx21ads_flash_resource = { - .start = MX21_CS0_BASE_ADDR, - .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx21ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx21ads_flash_data, - }, - .num_resources = 1, - .resource = &mx21ads_flash_resource, -}; - -static struct resource mx21ads_cs8900_resources[] __initdata = { - DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), - /* irq number is run-time assigned */ - DEFINE_RES_IRQ(-1), -}; - -static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = { - .name = "cs89x0", - .id = 0, - .res = mx21ads_cs8900_resources, - .num_res = ARRAY_SIZE(mx21ads_cs8900_resources), -}; - -static const struct imxuart_platform_data uart_pdata_rts __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxuart_platform_data uart_pdata_norts __initconst = { -}; - -static int mx21ads_fb_init(struct platform_device *pdev) -{ - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp |= MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); - return 0; -} - -static void mx21ads_fb_exit(struct platform_device *pdev) -{ - u16 tmp; - - tmp = __raw_readw(MX21ADS_IO_REG); - tmp &= ~MX21ADS_IO_LCDON; - __raw_writew(tmp, MX21ADS_IO_REG); -} - -/* - * Connected is a portrait Sharp-QVGA display - * of type: LQ035Q7DB02 - */ -static struct imx_fb_videomode mx21ads_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 2, - .left_margin = 6, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 8, - .lower_margin = 10, - }, - .pcr = 0xfb108bc7, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { - .mode = mx21ads_modes, - .num_modes = ARRAY_SIZE(mx21ads_modes), - - .pwmr = 0x00a903ff, - .lscr1 = 0x00120300, - .dmacr = 0x00020008, - - .init = mx21ads_fb_init, - .exit = mx21ads_fb_exit, -}; - -static int mx21ads_sdhc_get_ro(struct device *dev) -{ - return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; -} - -static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); -} - -static void mx21ads_sdhc_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data); -} - -static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { - .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ - .get_ro = mx21ads_sdhc_get_ro, - .init = mx21ads_sdhc_init, - .exit = mx21ads_sdhc_exit, -}; - -static const struct mxc_nand_platform_data -mx21ads_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct map_desc mx21ads_io_desc[] __initdata = { - /* - * Memory-mapped I/O on MX21ADS Base board: - * - CS8900A Ethernet controller - * - ST16C2552CJ UART - * - CPU and Base board version - * - Base board I/O register - */ - { - .virtual = MX21ADS_MMIO_BASE_ADDR, - .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR), - .length = MX21ADS_MMIO_SIZE, - .type = MT_DEVICE, - }, -}; - -static void __init mx21ads_map_io(void) -{ - mx21_map_io(); - iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc)); -} - -static struct platform_device *platform_devices[] __initdata = { - &mx21ads_nor_mtd_device, -}; - -static void __init mx21ads_board_init(void) -{ - imx21_soc_init(); - - mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), - "mx21ads"); - - imx21_add_imx_uart0(&uart_pdata_rts); - imx21_add_imx_uart2(&uart_pdata_norts); - imx21_add_imx_uart3(&uart_pdata_rts); - imx21_add_imx_fb(&mx21ads_fb_data); - imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); - imx21_add_mxc_nand(&mx21ads_nand_board_info); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - - mx21ads_cs8900_resources[1].start = - gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO); - mx21ads_cs8900_resources[1].end = - gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO); - platform_device_register_full(&mx21ads_cs8900_devinfo); -} - -static void __init mx21ads_timer_init(void) -{ - mx21_clocks_init(32768, 26000000); -} - -MACHINE_START(MX21ADS, "Freescale i.MX21ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx21ads_map_io, - .init_early = imx21_init_early, - .init_irq = mx21_init_irq, - .handle_irq = imx21_handle_irq, - .init_time = mx21ads_timer_init, - .init_machine = mx21ads_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c deleted file mode 100644 index 13490c203050..000000000000 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, - * Boston, MA 02110-1301, USA. - */ - -/* - * This machine is known as: - * - i.MX25 3-Stack Development System - * - i.MX25 Platform Development Kit (i.MX25 PDK) - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/usb/otg.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx25.h" -#include "hardware.h" -#include "iomux-mx25.h" -#include "mx25.h" - -#define MX25PDK_CAN_PWDN IMX_GPIO_NR(4, 6) - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static iomux_v3_cfg_t mx25pdk_pads[] = { - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */ - MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */ - - /* LCD */ - MX25_PAD_LD0__LD0, - MX25_PAD_LD1__LD1, - MX25_PAD_LD2__LD2, - MX25_PAD_LD3__LD3, - MX25_PAD_LD4__LD4, - MX25_PAD_LD5__LD5, - MX25_PAD_LD6__LD6, - MX25_PAD_LD7__LD7, - MX25_PAD_LD8__LD8, - MX25_PAD_LD9__LD9, - MX25_PAD_LD10__LD10, - MX25_PAD_LD11__LD11, - MX25_PAD_LD12__LD12, - MX25_PAD_LD13__LD13, - MX25_PAD_LD14__LD14, - MX25_PAD_LD15__LD15, - MX25_PAD_GPIO_E__LD16, - MX25_PAD_GPIO_F__LD17, - MX25_PAD_HSYNC__HSYNC, - MX25_PAD_VSYNC__VSYNC, - MX25_PAD_LSCLK__LSCLK, - MX25_PAD_OE_ACD__OE_ACD, - MX25_PAD_CONTRAST__CONTRAST, - - /* Keypad */ - MX25_PAD_KPP_ROW0__KPP_ROW0, - MX25_PAD_KPP_ROW1__KPP_ROW1, - MX25_PAD_KPP_ROW2__KPP_ROW2, - MX25_PAD_KPP_ROW3__KPP_ROW3, - MX25_PAD_KPP_COL0__KPP_COL0, - MX25_PAD_KPP_COL1__KPP_COL1, - MX25_PAD_KPP_COL2__KPP_COL2, - MX25_PAD_KPP_COL3__KPP_COL3, - - /* SD1 */ - MX25_PAD_SD1_CMD__SD1_CMD, - MX25_PAD_SD1_CLK__SD1_CLK, - MX25_PAD_SD1_DATA0__SD1_DATA0, - MX25_PAD_SD1_DATA1__SD1_DATA1, - MX25_PAD_SD1_DATA2__SD1_DATA2, - MX25_PAD_SD1_DATA3__SD1_DATA3, - MX25_PAD_A14__GPIO_2_0, /* WriteProtect */ - MX25_PAD_A15__GPIO_2_1, /* CardDetect */ - - /* I2C1 */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, - - /* CAN1 */ - MX25_PAD_GPIO_A__CAN1_TX, - MX25_PAD_GPIO_B__CAN1_RX, - MX25_PAD_D14__GPIO_4_6, /* CAN_PWDN */ -}; - -static const struct fec_platform_data mx25_fec_pdata __initconst = { - .phy = PHY_INTERFACE_MODE_RMII, -}; - -#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3) -#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8) - -static void __init mx25pdk_fec_reset(void) -{ - gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable"); - gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset"); - - gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ - gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ - udelay(2); - - /* turn on PHY power and lift reset */ - gpio_set_value(FEC_ENABLE_GPIO, 1); - gpio_set_value(FEC_RESET_B_GPIO, 1); -} - -static const struct mxc_nand_platform_data -mx25pdk_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct imx_fb_videomode mx25pdk_modes[] = { - { - .mode = { - .name = "CRT-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39683, - .left_margin = 45, - .right_margin = 114, - .upper_margin = 33, - .lower_margin = 11, - .hsync_len = 1, - .vsync_len = 1, - }, - .bpp = 16, - .pcr = 0xFA208B80, - }, -}; - -static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = { - .mode = mx25pdk_modes, - .num_modes = ARRAY_SIZE(mx25pdk_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static const uint32_t mx25pdk_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(0, 2, KEY_VOLUMEDOWN), - KEY(0, 3, KEY_HOME), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(1, 3, KEY_VOLUMEUP), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), - KEY(3, 0, KEY_F1), - KEY(3, 1, KEY_F2), - KEY(3, 2, KEY_F3), - KEY(3, 3, KEY_POWER), -}; - -static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = { - .keymap = mx25pdk_keymap, - .keymap_size = ARRAY_SIZE(mx25pdk_keymap), -}; - -static int mx25pdk_usbh2_init(struct platform_device *pdev) -{ - return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { - .init = mx25pdk_usbh2_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -#define SD1_GPIO_WP IMX_GPIO_NR(2, 0) -#define SD1_GPIO_CD IMX_GPIO_NR(2, 1) - -static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = { - .wp_gpio = SD1_GPIO_WP, - .cd_gpio = SD1_GPIO_CD, - .wp_type = ESDHC_WP_GPIO, - .cd_type = ESDHC_CD_GPIO, -}; - -static void __init mx25pdk_init(void) -{ - imx25_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, - ARRAY_SIZE(mx25pdk_pads)); - - imx25_add_imx_uart0(&uart_pdata); - imx25_add_fsl_usb2_udc(&otg_device_pdata); - imx25_add_mxc_ehci_hs(&usbh2_pdata); - imx25_add_mxc_nand(&mx25pdk_nand_board_info); - imx25_add_imxdi_rtc(); - imx25_add_imx_fb(&mx25pdk_fb_pdata); - imx25_add_imx2_wdt(); - - mx25pdk_fec_reset(); - imx25_add_fec(&mx25_fec_pdata); - imx25_add_imx_keypad(&mx25pdk_keymap_data); - - imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata); - imx25_add_imx_i2c0(&mx25_3ds_i2c0_data); - - gpio_request_one(MX25PDK_CAN_PWDN, GPIOF_OUT_INIT_LOW, "can-pwdn"); - imx25_add_flexcan0(); -} - -static void __init mx25pdk_timer_init(void) -{ - mx25_clocks_init(); -} - -MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx25_map_io, - .init_early = imx25_init_early, - .init_irq = mx25_init_irq, - .handle_irq = imx25_handle_irq, - .init_time = mx25pdk_timer_init, - .init_machine = mx25pdk_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c deleted file mode 100644 index 25b3e4c9bc0a..000000000000 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This machine is known as: - * - i.MX27 3-Stack Development System - * - i.MX27 Platform Development Kit (i.MX27 PDK) - */ - -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/delay.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/regulator/machine.h> -#include <linux/spi/l4f00242t03.h> - -#include <media/soc_camera.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" -#include "ulpi.h" - -#define SD1_EN_GPIO IMX_GPIO_NR(2, 25) -#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23) -#define SPI2_SS0 IMX_GPIO_NR(4, 21) -#define PMIC_INT IMX_GPIO_NR(3, 14) -#define SPI1_SS0 IMX_GPIO_NR(4, 28) -#define SD1_CD IMX_GPIO_NR(2, 26) -#define LCD_RESET IMX_GPIO_NR(1, 3) -#define LCD_ENABLE IMX_GPIO_NR(1, 31) -#define CSI_PWRDWN IMX_GPIO_NR(4, 19) -#define CSI_RESET IMX_GPIO_NR(3, 6) - -static const int mx27pdk_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, - /* OTG */ - OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* CSPI1 */ - PD31_PF_CSPI1_MOSI, - PD30_PF_CSPI1_MISO, - PD29_PF_CSPI1_SCLK, - PD25_PF_CSPI1_RDY, - SPI1_SS0 | GPIO_GPIO | GPIO_OUT, - /* CSPI2 */ - PD22_PF_CSPI2_SCLK, - PD23_PF_CSPI2_MISO, - PD24_PF_CSPI2_MOSI, - SPI2_SS0 | GPIO_GPIO | GPIO_OUT, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* PMIC INT */ - PMIC_INT | GPIO_GPIO | GPIO_IN, - /* LCD */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - LCD_ENABLE | GPIO_GPIO | GPIO_OUT, - LCD_RESET | GPIO_GPIO | GPIO_OUT, - /* CSI */ - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, - CSI_PWRDWN | GPIO_GPIO | GPIO_OUT, - CSI_RESET | GPIO_GPIO | GPIO_OUT, - /* SSI4 */ - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD, - PC18_PF_SSI4_TXD, - PC19_PF_SSI4_CLK, -}; - -static struct gpio mx27_3ds_camera_gpios[] = { - { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" }, - { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" }, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* - * Matrix keyboard - */ - -static const uint32_t mx27_3ds_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), -}; - -static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { - .keymap = mx27_3ds_keymap, - .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), -}; - -static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(SD1_CD), detect_irq, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); -} - -static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SD1_CD), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mx27_3ds_sdhc1_init, - .exit = mx27_3ds_sdhc1_exit, -}; - -static void mx27_3ds_sdhc1_enable_level_translator(void) -{ - /* Turn on TXB0108 OE pin */ - gpio_request(SD1_EN_GPIO, "sd1_enable"); - gpio_direction_output(SD1_EN_GPIO, 1); -} - - -static int otg_phy_init(void) -{ - gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); - gpio_direction_output(OTG_PHY_RESET_GPIO, 0); - mdelay(1); - gpio_set_value(OTG_PHY_RESET_GPIO, 1); - return 0; -} - -static int mx27_3ds_otg_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx27_3ds_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init mx27_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", mx27_3ds_otg_mode); - -/* Regulators */ -static struct regulator_init_data gpo_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("vcore", "spi0.0"), - REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vmmc1_init = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), - .consumer_supplies = vmmc1_consumers, -}; - -static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd", "spi0.0"), -}; - -static struct regulator_init_data vgen_init = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), - .consumer_supplies = vgen_consumers, -}; - -static struct regulator_consumer_supply vvib_consumers[] = { - REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vvib_init = { - .constraints = { - .min_uV = 1300000, - .max_uV = 1300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), - .consumer_supplies = vvib_consumers, -}; - -static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { - { - .id = MC13783_REG_VMMC1, - .init_data = &vmmc1_init, - }, { - .id = MC13783_REG_VGEN, - .init_data = &vgen_init, - }, { - .id = MC13783_REG_GPO1, /* Turn on 1.8V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_GPO3, /* Turn on 3.3V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_VVIB, /* Power OV2640 */ - .init_data = &vvib_init, - }, -}; - -/* MC13783 */ -static struct mc13xxx_codec_platform_data mx27_3ds_codec = { - .dac_ssi_port = MC13783_SSI1_PORT, - .adc_ssi_port = MC13783_SSI1_PORT, -}; - -static struct mc13xxx_platform_data mc13783_pdata = { - .regulators = { - .regulators = mx27_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), - - }, - .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | - MC13XXX_USE_CODEC, - .codec = &mx27_3ds_codec, -}; - -static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = { - .flags = IMX_SSI_DMA | IMX_SSI_NET, -}; - -/* SPI */ -static int spi1_chipselect[] = {SPI1_SS0}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi1_chipselect, - .num_chipselect = ARRAY_SIZE(spi1_chipselect), -}; - -static int spi2_chipselect[] = {SPI2_SS0}; - -static const struct spi_imx_master spi2_pdata __initconst = { - .chipselect = spi2_chipselect, - .num_chipselect = ARRAY_SIZE(spi2_chipselect), -}; - -static int mx27_3ds_camera_power(struct device *dev, int on) -{ - /* enable or disable the camera */ - pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); - gpio_set_value(CSI_PWRDWN, on ? 0 : 1); - - if (!on) - goto out; - - /* If enabled, give a reset impulse */ - gpio_set_value(CSI_RESET, 0); - msleep(20); - gpio_set_value(CSI_RESET, 1); - msleep(100); - -out: - return 0; -} - -static struct i2c_board_info mx27_3ds_i2c_camera = { - I2C_BOARD_INFO("ov2640", 0x30), -}; - -static struct regulator_bulk_data mx27_3ds_camera_regs[] = { - { .supply = "cmos_vcore" }, - { .supply = "cmos_2v8" }, -}; - -static struct soc_camera_link iclink_ov2640 = { - .bus_id = 0, - .board_info = &mx27_3ds_i2c_camera, - .i2c_adapter_id = 0, - .power = mx27_3ds_camera_power, - .regulators = mx27_3ds_camera_regs, - .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs), -}; - -static struct platform_device mx27_3ds_ov2640 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_ov2640, - }, -}; - -static struct imx_fb_videomode mx27_3ds_modes[] = { - { /* 480x640 @ 60 Hz */ - .mode = { - .name = "Epson-VGA", - .refresh = 60, - .xres = 480, - .yres = 640, - .pixclock = 41701, - .left_margin = 20, - .right_margin = 41, - .upper_margin = 10, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH | - FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - .bpp = 16, - .pcr = 0xFAC08B82, - }, -}; - -static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { - .mode = mx27_3ds_modes, - .num_modes = ARRAY_SIZE(mx27_3ds_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -/* LCD */ -static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = { - .reset_gpio = LCD_RESET, - .data_enable_gpio = LCD_ENABLE, -}; - -static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, /* SS0 */ - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ - .mode = SPI_CS_HIGH, - }, { - .modalias = "l4f00242t03", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, /* SS0 */ - .platform_data = &mx27_3ds_lcd_pdata, - }, -}; - -static struct platform_device *devices[] __initdata = { - &mx27_3ds_ov2640, -}; - -static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = { - .clk = 26000000, -}; - -static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static void __init mx27pdk_init(void) -{ - int ret; - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), - "mx27pdk"); - mx27_3ds_sdhc1_enable_level_translator(); - imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); - imx27_add_imx_keypad(&mx27_3ds_keymap_data); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_imx2_wdt(); - otg_phy_init(); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } - - if (!otg_mode_host) - imx27_add_fsl_usb2_udc(&otg_device_pdata); - - imx27_add_spi_imx1(&spi2_pdata); - imx27_add_spi_imx0(&spi1_pdata); - mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT); - spi_register_board_info(mx27_3ds_spi_devs, - ARRAY_SIZE(mx27_3ds_spi_devs)); - - if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28))) - pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); - imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx27_add_imx_fb(&mx27_3ds_fb_data); - - ret = gpio_request_array(mx27_3ds_camera_gpios, - ARRAY_SIZE(mx27_3ds_camera_gpios)); - if (ret) { - pr_err("Failed to request camera gpios"); - iclink_ov2640.power = NULL; - } - - imx27_add_mx2_camera(&mx27_3ds_cam_pdata); - imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata); - - imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); -} - -static void __init mx27pdk_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(MX27_3DS, "Freescale MX27PDK") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = mx27pdk_timer_init, - .init_machine = mx27pdk_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c deleted file mode 100644 index 9821b824dcaf..000000000000 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/irq.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -/* - * Base address of PBC controller, CS4 - */ -#define PBC_BASE_ADDRESS 0xf4300000 -#define PBC_REG_ADDR(offset) (void __force __iomem *) \ - (PBC_BASE_ADDRESS + (offset)) - -/* When the PBC address connection is fixed in h/w, defined as 1 */ -#define PBC_ADDR_SH 0 - -/* Offsets for the PBC Controller register */ -/* - * PBC Board version register offset - */ -#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 set address. - */ -#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 clear address. - */ -#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) - -/* PBC Board Control Register 1 bit definitions */ -#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ - -/* to determine the correct external crystal reference */ -#define CKIH_27MHZ_BIT_SET (1 << 3) - -static const int mx27ads_pins[] __initconst = { - /* UART0 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART1 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART2 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* UART3 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - /* UART4 */ - PB18_AF_UART5_TXD, - PB19_AF_UART5_RXD, - PB20_AF_UART5_CTS, - PB21_AF_UART5_RTS, - /* UART5 */ - PB10_AF_UART6_TXD, - PB12_AF_UART6_CTS, - PB11_AF_UART6_RXD, - PB13_AF_UART6_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* FB */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* OWIRE */ - PE16_AF_OWIRE, - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* SDHC2*/ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -}; - -static const struct mxc_nand_platform_data -mx27ads_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -/* ADS's NOR flash */ -static struct physmap_flash_data mx27ads_flash_data = { - .width = 2, -}; - -static struct resource mx27ads_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + 0x02000000 - 1, - .flags = IORESOURCE_MEM, - -}; - -static struct platform_device mx27ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx27ads_flash_data, - }, - .num_resources = 1, - .resource = &mx27ads_flash_resource, -}; - -static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mx27ads_i2c_devices[] = { -}; - -void lcd_power(int on) -{ - if (on) - __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); - else - __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); -} - -static struct imx_fb_videomode mx27ads_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 1, - .left_margin = 9, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - }, - .bpp = 16, - .pcr = 0xFB008BC0, - }, -}; - -static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { - .mode = mx27ads_modes, - .num_modes = ARRAY_SIZE(mx27ads_modes), - - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, - - .lcd_power = lcd_power, -}; - -static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq, - IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); -} - -static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq, - IRQF_TRIGGER_RISING, "sdhc2-card-detect", data); -} - -static void mx27ads_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data); -} - -static void mx27ads_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mx27ads_sdhc1_init, - .exit = mx27ads_sdhc1_exit, -}; - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .init = mx27ads_sdhc2_init, - .exit = mx27ads_sdhc2_exit, -}; - -static struct platform_device *platform_devices[] __initdata = { - &mx27ads_nor_mtd_device, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mx27ads_board_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), - "mx27ads"); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - imx27_add_imx_uart3(&uart_pdata); - imx27_add_imx_uart4(&uart_pdata); - imx27_add_imx_uart5(&uart_pdata); - imx27_add_mxc_nand(&mx27ads_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, mx27ads_i2c_devices, - ARRAY_SIZE(mx27ads_i2c_devices)); - imx27_add_imx_i2c(1, &mx27ads_i2c1_data); - imx27_add_imx_fb(&mx27ads_fb_data); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_mxc_mmc(1, &sdhc2_pdata); - - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx27_add_mxc_w1(); -} - -static void __init mx27ads_timer_init(void) -{ - unsigned long fref = 26000000; - - if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) - fref = 27000000; - - mx27_clocks_init(fref); -} - -static struct map_desc mx27ads_io_desc[] __initdata = { - { - .virtual = PBC_BASE_ADDRESS, - .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - -static void __init mx27ads_map_io(void) -{ - mx27_map_io(); - iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); -} - -MACHINE_START(MX27ADS, "Freescale i.MX27ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27ads_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = mx27ads_timer_init, - .init_machine = mx27ads_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c deleted file mode 100644 index 1ed916175d41..000000000000 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ /dev/null @@ -1,783 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/spi/l4f00242t03.h> -#include <linux/regulator/machine.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/memblock.h> - -#include <media/soc_camera.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static int mx31_3ds_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), - /*SPI0*/ - IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), - /* SPI 1 */ - MX31_PIN_CSPI2_SCLK__SCLK, - MX31_PIN_CSPI2_MOSI__MOSI, - MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, - MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ - /* MC13783 IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), - /* USB OTG reset */ - IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /*Keyboard*/ - MX31_PIN_KEY_ROW0_KEY_ROW0, - MX31_PIN_KEY_ROW1_KEY_ROW1, - MX31_PIN_KEY_ROW2_KEY_ROW2, - MX31_PIN_KEY_COL0_KEY_COL0, - MX31_PIN_KEY_COL1_KEY_COL1, - MX31_PIN_KEY_COL2_KEY_COL2, - MX31_PIN_KEY_COL3_KEY_COL3, - /* USB Host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), - /* USB Host2 reset */ - IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), - /* I2C1 */ - MX31_PIN_I2C_CLK__I2C1_SCL, - MX31_PIN_I2C_DAT__I2C1_SDA, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ - MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_CONTRAST__CONTRAST, - /* CSI */ - MX31_PIN_CSI_D6__CSI_D6, - MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, - MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, - MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, - MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, - MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, - MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, - MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */ - IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */ - /* SSI */ - MX31_PIN_STXD4__STXD4, - MX31_PIN_SRXD4__SRXD4, - MX31_PIN_SCK4__SCK4, - MX31_PIN_SFS4__SFS4, -}; - -/* - * Camera support - */ -static phys_addr_t mx3_camera_base __initdata; -#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M - -#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5) -#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1) - -static struct gpio mx31_3ds_camera_gpios[] = { - { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" }, - { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" }, -}; - -static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = { - .flags = MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 2600, -}; - -static int __init mx31_3ds_init_camera(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev = - imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata); - - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - if (!mx3_camera_base) - goto err; - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX31_3DS_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; -} - -static int mx31_3ds_camera_power(struct device *dev, int on) -{ - /* enable or disable the camera */ - pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE"); - gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1); - - if (!on) - goto out; - - /* If enabled, give a reset impulse */ - gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0); - msleep(20); - gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1); - msleep(100); - -out: - return 0; -} - -static struct i2c_board_info mx31_3ds_i2c_camera = { - I2C_BOARD_INFO("ov2640", 0x30), -}; - -static struct regulator_bulk_data mx31_3ds_camera_regs[] = { - { .supply = "cmos_vcore" }, - { .supply = "cmos_2v8" }, -}; - -static struct soc_camera_link iclink_ov2640 = { - .bus_id = 0, - .board_info = &mx31_3ds_i2c_camera, - .i2c_adapter_id = 0, - .power = mx31_3ds_camera_power, - .regulators = mx31_3ds_camera_regs, - .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs), -}; - -static struct platform_device mx31_3ds_ov2640 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_ov2640, - }, -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 480x640 @ 60 Hz */ - .name = "Epson-VGA", - .refresh = 60, - .xres = 480, - .yres = 640, - .pixclock = 41701, - .left_margin = 20, - .right_margin = 41, - .upper_margin = 10, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Epson-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* LCD */ -static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = { - .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1), - .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS), -}; - -/* - * Support for SD card slot in personality board - */ -#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) - -static struct gpio mx31_3ds_sdhc1_gpios[] = { - { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, - { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, -}; - -static int mx31_3ds_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); - if (ret) { - pr_warning("Unable to request the SD/MMC GPIOs.\n"); - return ret; - } - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), - detect_irq, IRQF_DISABLED | - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "sdhc1-detect", data); - if (ret) { - pr_warning("Unable to request the SD/MMC card-detect IRQ.\n"); - goto gpio_free; - } - - return 0; - -gpio_free: - gpio_free_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); - return ret; -} - -static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data); - gpio_free_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); -} - -static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) -{ - /* - * While the voltage stuff is done by the driver, activate the - * Buffer Enable Pin only if there is a card in slot to fix the card - * voltage issue caused by bi-directional chip TXB0108 on 3Stack. - * Done here because at this stage we have for sure a debounced value - * of the presence of the card, showed by the value of vdd. - * 7 == ilog2(MMC_VDD_165_195) - */ - if (vdd > 7) - gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); - else - gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); -} - -static struct imxmmc_platform_data sdhc1_pdata = { - .init = mx31_3ds_sdhc1_init, - .exit = mx31_3ds_sdhc1_exit, - .setpower = mx31_3ds_sdhc1_setpower, -}; - -/* - * Matrix keyboard - */ - -static const uint32_t mx31_3ds_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), -}; - -static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { - .keymap = mx31_3ds_keymap, - .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), -}; - -/* Regulators */ -static struct regulator_init_data pwgtx_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - }, -}; - -static struct regulator_init_data gpo_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_consumer_supply vmmc2_consumers[] = { - REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"), -}; - -static struct regulator_init_data vmmc2_init = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), - .consumer_supplies = vmmc2_consumers, -}; - -static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("vcore", "spi0.0"), - REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vmmc1_init = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), - .consumer_supplies = vmmc1_consumers, -}; - -static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd", "spi0.0"), -}; - -static struct regulator_init_data vgen_init = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), - .consumer_supplies = vgen_consumers, -}; - -static struct regulator_consumer_supply vvib_consumers[] = { - REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data vvib_init = { - .constraints = { - .min_uV = 1300000, - .max_uV = 1300000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vvib_consumers), - .consumer_supplies = vvib_consumers, -}; - -static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { - { - .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ - .init_data = &pwgtx_init, - }, { - .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ - .init_data = &pwgtx_init, - }, { - - .id = MC13783_REG_GPO1, /* Turn on 1.8V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_GPO3, /* Turn on 3.3V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ - .init_data = &vmmc2_init, - }, { - .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ - .init_data = &vmmc1_init, - }, { - .id = MC13783_REG_VGEN, /* Power LCD */ - .init_data = &vgen_init, - }, { - .id = MC13783_REG_VVIB, /* Power CMOS */ - .init_data = &vvib_init, - }, -}; - -/* MC13783 */ -static struct mc13xxx_codec_platform_data mx31_3ds_codec = { - .dac_ssi_port = MC13783_SSI1_PORT, - .adc_ssi_port = MC13783_SSI1_PORT, -}; - -static struct mc13xxx_platform_data mc13783_pdata = { - .regulators = { - .regulators = mx31_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - }, - .codec = &mx31_3ds_codec, - .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC, - -}; - -static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = { - .flags = IMX_SSI_DMA | IMX_SSI_NET, -}; - -/* SPI */ -static int spi0_internal_chipselect[] = { - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi0_pdata __initconst = { - .chipselect = spi0_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect), -}; - -static int spi1_internal_chipselect[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi1_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), -}; - -static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 1, /* SS2 */ - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ - .mode = SPI_CS_HIGH, - }, { - .modalias = "l4f00242t03", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, /* SS2 */ - .platform_data = &mx31_3ds_l4f00242t03_pdata, - }, -}; - -/* - * NAND Flash - */ -static const struct mxc_nand_platform_data -mx31_3ds_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT - .flash_bbt = 1, -#endif -}; - -/* - * USB OTG - */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) -#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) - -static int mx31_3ds_usbotg_init(void) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - err = gpio_request(USBOTG_RST_B, "otgusb-reset"); - if (err) { - pr_err("Failed to request the USB OTG reset gpio\n"); - return err; - } - - err = gpio_direction_output(USBOTG_RST_B, 0); - if (err) { - pr_err("Failed to drive the USB OTG reset gpio\n"); - goto usbotg_free_reset; - } - - mdelay(1); - gpio_set_value(USBOTG_RST_B, 1); - return 0; - -usbotg_free_reset: - gpio_free(USBOTG_RST_B); - return err; -} - -static int mx31_3ds_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static int mx31_3ds_host2_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); - - err = gpio_request(USBH2_RST_B, "usbh2-reset"); - if (err) { - pr_err("Failed to request the USB Host 2 reset gpio\n"); - return err; - } - - err = gpio_direction_output(USBH2_RST_B, 0); - if (err) { - pr_err("Failed to drive the USB Host 2 reset gpio\n"); - goto usbotg_free_reset; - } - - mdelay(1); - gpio_set_value(USBH2_RST_B, 1); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); - -usbotg_free_reset: - gpio_free(USBH2_RST_B); - return err; -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx31_3ds_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = mx31_3ds_host2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init mx31_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", mx31_3ds_otg_mode); - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static struct platform_device *devices[] __initdata = { - &mx31_3ds_ov2640, -}; - -static void __init mx31_3ds_init(void) -{ - int ret; - - imx31_soc_init(); - - /* Configure SPI1 IOMUX */ - mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); - - mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), - "mx31_3ds"); - - imx31_add_imx_uart0(&uart_pdata); - imx31_add_mxc_nand(&mx31_3ds_nand_board_info); - - imx31_add_spi_imx1(&spi1_pdata); - mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(mx31_3ds_spi_devs, - ARRAY_SIZE(mx31_3ds_spi_devs)); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx31_add_imx_keypad(&mx31_3ds_keymap_data); - - mx31_3ds_usbotg_init(); - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx31_add_mxc_ehci_otg(&otg_pdata); - } - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - if (!otg_mode_host) - imx31_add_fsl_usb2_udc(&usbotg_pdata); - - if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))) - printk(KERN_WARNING "Init of the debug board failed, all " - "devices on the debug board are unusable.\n"); - imx31_add_imx2_wdt(); - imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); - imx31_add_mxc_mmc(0, &sdhc1_pdata); - - imx31_add_spi_imx0(&spi0_pdata); - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* CSI */ - /* Camera power: default - off */ - ret = gpio_request_array(mx31_3ds_camera_gpios, - ARRAY_SIZE(mx31_3ds_camera_gpios)); - if (ret) { - pr_err("Failed to request camera gpios"); - iclink_ov2640.power = NULL; - } - - mx31_3ds_init_camera(); - - imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata); - - imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); -} - -static void __init mx31_3ds_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static void __init mx31_3ds_reserve(void) -{ - /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE, - MX31_3DS_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = mx31_3ds_timer_init, - .init_machine = mx31_3ds_init, - .reserve = mx31_3ds_reserve, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c deleted file mode 100644 index daf8889125cc..000000000000 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ /dev/null @@ -1,589 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -#include <linux/mfd/wm8350/audio.h> -#include <linux/mfd/wm8350/core.h> -#include <linux/mfd/wm8350/pmic.h> -#endif - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* Base address of PBC controller */ -#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT - -/* PBC Board interrupt status register */ -#define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ -#define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ -#define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ -#define PBC_INTMASK_CLEAR 0x00001C - -/* External UART A */ -#define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ -#define PBC_SC16C652_UARTB 0x010010 - -#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) -#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) -#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) - -#define EXPIO_INT_XUART_INTA 10 -#define EXPIO_INT_XUART_INTB 11 - -#define MXC_MAX_EXP_IO_LINES 16 - -/* CS8900 */ -#define EXPIO_INT_ENET_INT 8 -#define CS4_CS8900_MMIO_START 0x20000 - -static struct irq_domain *domain; - -/* - * The serial port definition structure. - */ -static struct plat_serial8250_port serial_platform_data[] = { - { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), - .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA), - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), - .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB), - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, - {}, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static struct resource mx31ads_cs8900_resources[] __initdata = { - DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K), - DEFINE_RES_IRQ(-1), -}; - -static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = { - .name = "cs89x0", - .id = 0, - .res = mx31ads_cs8900_resources, - .num_res = ARRAY_SIZE(mx31ads_cs8900_resources), -}; - -static int __init mxc_init_extuart(void) -{ - serial_platform_data[0].irq = irq_find_mapping(domain, - EXPIO_INT_XUART_INTA); - serial_platform_data[1].irq = irq_find_mapping(domain, - EXPIO_INT_XUART_INTB); - return platform_device_register(&serial_device); -} - -static void __init mxc_init_ext_ethernet(void) -{ - mx31ads_cs8900_resources[1].start = - irq_find_mapping(domain, EXPIO_INT_ENET_INT); - mx31ads_cs8900_resources[1].end = - irq_find_mapping(domain, EXPIO_INT_ENET_INT); - platform_device_register_full( - (struct platform_device_info *)&mx31ads_cs8900_devinfo); -} - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static unsigned int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 -}; - -static inline void mxc_init_imx_uart(void) -{ - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - imx31_add_imx_uart0(&uart_pdata); -} - -static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) -{ - u32 imr_val; - u32 int_valid; - u32 expio_irq; - - imr_val = __raw_readw(PBC_INTMASK_SET_REG); - int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val; - - expio_irq = 0; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - - generic_handle_irq(irq_find_mapping(domain, expio_irq)); - } -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param d an expio virtual irq description - */ -static void expio_mask_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - /* mask the interrupt */ - __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG); - __raw_readw(PBC_INTMASK_CLEAR_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param d an expio virtual irq description - */ -static void expio_ack_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - /* clear the interrupt status */ - __raw_writew(1 << expio, PBC_INTSTATUS_REG); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param d an expio virtual irq description - */ -static void expio_unmask_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - /* unmask the interrupt */ - __raw_writew(1 << expio, PBC_INTMASK_SET_REG); -} - -static struct irq_chip expio_irq_chip = { - .name = "EXPIO(CPLD)", - .irq_ack = expio_ack_irq, - .irq_mask = expio_mask_irq, - .irq_unmask = expio_unmask_irq, -}; - -static void __init mx31ads_init_expio(void) -{ - int irq_base; - int i, irq; - - printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); - - /* - * Configure INT line as GPIO input - */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); - - /* disable the interrupt and clear the status */ - __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); - __raw_writew(0xFFFF, PBC_INTSTATUS_REG); - - irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); - WARN_ON(irq_base < 0); - - domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { - irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - set_irq_flags(i, IRQF_VALID); - } - irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4)); - irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - irq_set_chained_handler(irq, mx31ads_expio_irq_handler); -} - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -/* This section defines setup for the Wolfson Microelectronics - * 1133-EV1 PMU/audio board. When other PMU boards are supported the - * regulator definitions may be shared with them, but for now they can - * only be used with this board so would generate warnings about - * unused statics and some of the configuration is specific to this - * module. - */ - -/* CPU */ -static struct regulator_consumer_supply sw1a_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_init_data sw1a_data = { - .constraints = { - .name = "SW1A", - .min_uV = 1275000, - .max_uV = 1600000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .state_mem = { - .uV = 1400000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), - .consumer_supplies = sw1a_consumers, -}; - -/* System IO - High */ -static struct regulator_init_data viohi_data = { - .constraints = { - .name = "VIOHO", - .min_uV = 2800000, - .max_uV = 2800000, - .state_mem = { - .uV = 2800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* System IO - Low */ -static struct regulator_init_data violo_data = { - .constraints = { - .name = "VIOLO", - .min_uV = 1800000, - .max_uV = 1800000, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* DDR RAM */ -static struct regulator_init_data sw2a_data = { - .constraints = { - .name = "SW2A", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .state_disk = { - .mode = REGULATOR_MODE_NORMAL, - .enabled = 0, - }, - .always_on = 1, - .boot_on = 1, - .initial_state = PM_SUSPEND_MEM, - }, -}; - -static struct regulator_init_data ldo1_data = { - .constraints = { - .name = "VCAM/VMMC1/VMMC2", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, -}; - -static struct regulator_consumer_supply ldo2_consumers[] = { - { .supply = "AVDD", .dev_name = "1-001a" }, - { .supply = "HPVDD", .dev_name = "1-001a" }, -}; - -/* CODEC and SIM */ -static struct regulator_init_data ldo2_data = { - .constraints = { - .name = "VESIM/VSIM/AVDD", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), - .consumer_supplies = ldo2_consumers, -}; - -/* General */ -static struct regulator_init_data vdig_data = { - .constraints = { - .name = "VDIG", - .min_uV = 1500000, - .max_uV = 1500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* Tranceivers */ -static struct regulator_init_data ldo4_data = { - .constraints = { - .name = "VRF1/CVDD_2.775", - .min_uV = 2500000, - .max_uV = 2500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - .boot_on = 1, - }, -}; - -static struct wm8350_led_platform_data wm8350_led_data = { - .name = "wm8350:white", - .default_trigger = "heartbeat", - .max_uA = 27899, -}; - -static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { - .vmid_discharge_msecs = 1000, - .drain_msecs = 30, - .cap_discharge_msecs = 700, - .vmid_charge_msecs = 700, - .vmid_s_curve = WM8350_S_CURVE_SLOW, - .dis_out4 = WM8350_DISCHARGE_SLOW, - .dis_out3 = WM8350_DISCHARGE_SLOW, - .dis_out2 = WM8350_DISCHARGE_SLOW, - .dis_out1 = WM8350_DISCHARGE_SLOW, - .vroi_out4 = WM8350_TIE_OFF_500R, - .vroi_out3 = WM8350_TIE_OFF_500R, - .vroi_out2 = WM8350_TIE_OFF_500R, - .vroi_out1 = WM8350_TIE_OFF_500R, - .vroi_enable = 0, - .codec_current_on = WM8350_CODEC_ISEL_1_0, - .codec_current_standby = WM8350_CODEC_ISEL_0_5, - .codec_current_charge = WM8350_CODEC_ISEL_1_5, -}; - -static int mx31_wm8350_init(struct wm8350 *wm8350) -{ - wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, - WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_ON); - - wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, - WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_ON); - - wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, - WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, - WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, - WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, - WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, - WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data); - wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data); - wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data); - wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data); - wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data); - - /* LEDs */ - wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1, - WM8350_DC5_ERRACT_SHUTDOWN_CONV); - wm8350_isink_set_flash(wm8350, WM8350_ISINK_A, - WM8350_ISINK_FLASH_DISABLE, - WM8350_ISINK_FLASH_TRIG_BIT, - WM8350_ISINK_FLASH_DUR_32MS, - WM8350_ISINK_FLASH_ON_INSTANT, - WM8350_ISINK_FLASH_OFF_INSTANT, - WM8350_ISINK_FLASH_MODE_EN); - wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5, - WM8350_ISINK_MODE_BOOST, - WM8350_ISINK_ILIM_NORMAL, - WM8350_DC5_RMP_20V, - WM8350_DC5_FBSRC_ISINKA); - wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A, - &wm8350_led_data); - - wm8350->codec.platform_data = &imx32ads_wm8350_setup; - - regulator_has_full_constraints(); - - return 0; -} - -static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { - .init = mx31_wm8350_init, -}; -#endif - -static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 - { - I2C_BOARD_INFO("wm8350", 0x1a), - .platform_data = &mx31_wm8350_pdata, - /* irq number is run-time assigned */ - }, -#endif -}; - -static void __init mxc_init_i2c(void) -{ -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 - mx31ads_i2c1_devices[0].irq = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); -#endif - i2c_register_board_info(1, mx31ads_i2c1_devices, - ARRAY_SIZE(mx31ads_i2c1_devices)); - - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); - - imx31_add_imx_i2c1(NULL); -} - -static unsigned int ssi_pins[] = { - MX31_PIN_SFS5__SFS5, - MX31_PIN_SCK5__SCK5, - MX31_PIN_SRXD5__SRXD5, - MX31_PIN_STXD5__STXD5, -}; - -static void __init mxc_init_audio(void) -{ - imx31_add_imx_ssi(0, NULL); - mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); -} - -/* - * Static mappings, starting from the CS4 start address up to the start address - * of the CS8900. - */ -static struct map_desc mx31ads_io_desc[] __initdata = { - { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = CS4_CS8900_MMIO_START, - .type = MT_DEVICE - }, -}; - -static void __init mx31ads_map_io(void) -{ - mx31_map_io(); - iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); -} - -static void __init mx31ads_init_irq(void) -{ - mx31_init_irq(); - mx31ads_init_expio(); -} - -static void __init mx31ads_init(void) -{ - imx31_soc_init(); - - mxc_init_extuart(); - mxc_init_imx_uart(); - mxc_init_i2c(); - mxc_init_audio(); - mxc_init_ext_ethernet(); -} - -static void __init mx31ads_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(MX31ADS, "Freescale MX31ADS") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31ads_map_io, - .init_early = imx31_init_early, - .init_irq = mx31ads_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = mx31ads_timer_init, - .init_machine = mx31ads_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c deleted file mode 100644 index 832b1e2f964e..000000000000 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * LILLY-1131 module support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/moduleparam.h> -#include <linux/smsc911x.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13783.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "board-mx31lilly.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -/* - * This file contains module-specific initialization routines for LILLY-1131. - * Initialization of peripherals found on the baseboard is implemented in the - * appropriate baseboard support code. - */ - -/* SMSC ethernet support */ - -static struct resource smsc91x_resources[] = { - { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 0xffff, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, - } -}; - -static struct smsc911x_platform_config smsc911x_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT | - SMSC911X_SAVE_MAC_ADDRESS | - SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc91x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc91x_resources), - .resource = smsc91x_resources, - .dev = { - .platform_data = &smsc911x_config, - } -}; - -/* NOR flash */ -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - -/* USB */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbh1_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_MISO__USBH1_RXDP, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, - MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, - MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -static int usbh2_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_USBH2_CLK__USBH2_CLK, - MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, - MX31_PIN_USBH2_STP__USBH2_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), - "USBH2_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = usbh1_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static void __init lilly1131_usb_init(void) -{ - imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -/* SPI */ - -static int spi_internal_chipselect[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(1), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi0_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, -}; - -static struct spi_board_info mc13783_dev __initdata = { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ -}; - -static struct platform_device *devices[] __initdata = { - &smsc91x_device, - &physmap_flash_device, -}; - -static int mx31lilly_baseboard; -core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static void __init mx31lilly_board_init(void) -{ - imx31_soc_init(); - - switch (mx31lilly_baseboard) { - case MX31LILLY_NOBOARD: - break; - case MX31LILLY_DB: - mx31lilly_db_init(); - break; - default: - printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n", - mx31lilly_baseboard); - } - - mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); - - /* SPI */ - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2"); - - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); - - imx31_add_spi_imx0(&spi0_pdata); - imx31_add_spi_imx1(&spi1_pdata); - mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(&mc13783_dev, 1); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - smsc91x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - smsc91x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* USB */ - lilly1131_usb_init(); -} - -static void __init mx31lilly_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = mx31lilly_timer_init, - .init_machine = mx31lilly_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c deleted file mode 100644 index bea07299b61a..000000000000 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/memory.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/moduleparam.h> -#include <linux/smsc911x.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/mtd/physmap.h> -#include <linux/delay.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/page.h> -#include <asm/setup.h> - -#include "board-mx31lite.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -/* - * This file contains the module-specific initialization routines. - */ - -static unsigned int mx31lite_pins[] = { - /* LAN9117 IRQ pin */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), - /* SPI 1 */ - MX31_PIN_CSPI2_SCLK__SCLK, - MX31_PIN_CSPI2_MOSI__MOSI, - MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, - MX31_PIN_CSPI2_SS1__SS1, - MX31_PIN_CSPI2_SS2__SS2, -}; - -static const struct mxc_nand_platform_data -mx31lite_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT, -}; - -static struct resource smsc911x_resources[] = { - { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 0x100, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -/* - * SPI - * - * The MC13783 is the only hard-wired SPI device on the module. - */ - -static int spi_internal_chipselect[] = { - MXC_SPI_CS(0), -}; - -static const struct spi_imx_master spi1_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .flags = MC13XXX_USE_RTC, -}; - -static struct spi_board_info mc13783_spi_dev __initdata = { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ -}; - -/* - * USB - */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbh2_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_USBH2_CLK__USBH2_CLK, - MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, - MX31_PIN_USBH2_STP__USBH2_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), - "USBH2_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* - * NOR flash - */ - -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - - - -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31lite_io_desc[] __initdata = { - { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = MX31_CS4_SIZE, - .type = MT_DEVICE - } -}; - -/* - * Set up static virtual mappings. - */ -void __init mx31lite_map_io(void) -{ - mx31_map_io(); - iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); -} - -static int mx31lite_baseboard; -core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static void __init mx31lite_init(void) -{ - int ret; - - imx31_soc_init(); - - switch (mx31lite_baseboard) { - case MX31LITE_NOBOARD: - break; - case MX31LITE_DB: - mx31lite_db_init(); - break; - default: - printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n", - mx31lite_baseboard); - } - - mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), - "mx31lite"); - - /* NOR and NAND flash */ - platform_device_register(&physmap_flash_device); - imx31_add_mxc_nand(&mx31lite_nand_board_info); - - imx31_add_spi_imx1(&spi1_pdata); - mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(&mc13783_spi_dev, 1); - - /* USB */ - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - /* SMSC9117 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - smsc911x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - smsc911x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - platform_device_register(&smsc911x_device); - } -} - -static void __init mx31lite_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31lite_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = mx31lite_timer_init, - .init_machine = mx31lite_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c deleted file mode 100644 index 6f424eced181..000000000000 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ /dev/null @@ -1,618 +0,0 @@ -/* - * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/gfp.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/moduleparam.h> -#include <linux/leds.h> -#include <linux/memory.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/types.h> -#include <linux/memblock.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/input.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> -#include <linux/platform_data/asoc-imx-ssi.h> - -#include "board-mx31moboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int moboard_pins[] = { - /* UART0 */ - MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS1__GPIO2_7, - /* UART4 */ - MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, - /* I2C0 */ - MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL, - /* I2C1 */ - MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, - /* USB reset */ - MX31_PIN_GPIO1_0__GPIO1_0, - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, - MX31_PIN_USB_OC__GPIO1_30, - /* USB H2 */ - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3, - MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5, - MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7, - MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP, - MX31_PIN_SCK6__GPIO1_25, - /* LEDs */ - MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, - MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, - /* SPI1 */ - MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2, - /* Atlas IRQ */ - MX31_PIN_GPIO1_3__GPIO1_3, - /* SPI2 */ - MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO, - MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS1__CSPI3_SS1, - /* SSI */ - MX31_PIN_STXD4__STXD4, MX31_PIN_SRXD4__SRXD4, - MX31_PIN_SCK4__SCK4, MX31_PIN_SFS4__SFS4, -}; - -static struct physmap_flash_data mx31moboard_flash_data = { - .width = 2, -}; - -static struct resource mx31moboard_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx31moboard_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx31moboard_flash_data, - }, - .resource = &mx31moboard_flash_resource, - .num_resources = 1, -}; - -static int moboard_uart0_init(struct platform_device *pdev) -{ - int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); - if (ret) - return ret; - - ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - if (ret) - gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); - - return ret; -} - -static void moboard_uart0_exit(struct platform_device *pdev) -{ - gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); -} - -static const struct imxuart_platform_data uart0_pdata __initconst = { - .init = moboard_uart0_init, - .exit = moboard_uart0_exit, -}; - -static const struct imxuart_platform_data uart4_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data moboard_i2c0_data __initconst = { - .bitrate = 400000, -}; - -static const struct imxi2c_platform_data moboard_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static int moboard_spi1_cs[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master moboard_spi1_pdata __initconst = { - .chipselect = moboard_spi1_cs, - .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), -}; - -static struct regulator_consumer_supply sdhc_consumers[] = { - { - .dev_name = "imx31-mmc.0", - .supply = "sdhc0_vcc", - }, - { - .dev_name = "imx31-mmc.1", - .supply = "sdhc1_vcc", - }, -}; - -static struct regulator_init_data sdhc_vreg_data = { - .constraints = { - .min_uV = 2700000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers), - .consumer_supplies = sdhc_consumers, -}; - -static struct regulator_consumer_supply cam_consumers[] = { - { - .dev_name = "mx3_camera.0", - .supply = "cam_vcc", - }, -}; - -static struct regulator_init_data cam_vreg_data = { - .constraints = { - .min_uV = 2700000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(cam_consumers), - .consumer_supplies = cam_consumers, -}; - -static struct mc13xxx_regulator_init_data moboard_regulators[] = { - { - .id = MC13783_REG_VMMC1, - .init_data = &sdhc_vreg_data, - }, - { - .id = MC13783_REG_VCAM, - .init_data = &cam_vreg_data, - }, -}; - -static struct mc13xxx_led_platform_data moboard_led[] = { - { - .id = MC13783_LED_R1, - .name = "coreboard-led-4:red", - .max_current = 2, - }, - { - .id = MC13783_LED_G1, - .name = "coreboard-led-4:green", - .max_current = 2, - }, - { - .id = MC13783_LED_B1, - .name = "coreboard-led-4:blue", - .max_current = 2, - }, - { - .id = MC13783_LED_R2, - .name = "coreboard-led-5:red", - .max_current = 3, - }, - { - .id = MC13783_LED_G2, - .name = "coreboard-led-5:green", - .max_current = 3, - }, - { - .id = MC13783_LED_B2, - .name = "coreboard-led-5:blue", - .max_current = 3, - }, -}; - -static struct mc13xxx_leds_platform_data moboard_leds = { - .num_leds = ARRAY_SIZE(moboard_led), - .led = moboard_led, - .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0), - .led_control[1] = MC13783_LED_C1_SLEWLIM, - .led_control[2] = MC13783_LED_C2_SLEWLIM, - .led_control[3] = MC13783_LED_C3_PERIOD(0), - .led_control[4] = MC13783_LED_C3_PERIOD(0), -}; - -static struct mc13xxx_buttons_platform_data moboard_buttons = { - .b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE | - MC13783_BUTTON_POL_INVERT, - .b1on_key = KEY_POWER, -}; - -static struct mc13xxx_codec_platform_data moboard_codec = { - .dac_ssi_port = MC13783_SSI1_PORT, - .adc_ssi_port = MC13783_SSI1_PORT, -}; - -static struct mc13xxx_platform_data moboard_pmic = { - .regulators = { - .regulators = moboard_regulators, - .num_regulators = ARRAY_SIZE(moboard_regulators), - }, - .leds = &moboard_leds, - .buttons = &moboard_buttons, - .codec = &moboard_codec, - .flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC | MC13XXX_USE_CODEC, -}; - -static struct imx_ssi_platform_data moboard_ssi_pdata = { - .flags = IMX_SSI_DMA | IMX_SSI_NET, -}; - -static struct spi_board_info moboard_spi_board_info[] __initdata = { - { - .modalias = "mc13783", - /* irq number is run-time assigned */ - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &moboard_pmic, - .mode = SPI_CS_HIGH, - }, -}; - -static int moboard_spi2_cs[] = { - MXC_SPI_CS(1), -}; - -static const struct spi_imx_master moboard_spi2_pdata __initconst = { - .chipselect = moboard_spi2_cs, - .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), -}; - -#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) -#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) - -static int moboard_sdhc1_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC1_WP); -} - -static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_CD); - - ret = gpio_request(SDHC1_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_WP); - - ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc1-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC1_WP); -err_gpio_free: - gpio_free(SDHC1_CD); - - return ret; -} - -static void moboard_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC1_CD), data); - gpio_free(SDHC1_WP); - gpio_free(SDHC1_CD); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .get_ro = moboard_sdhc1_get_ro, - .init = moboard_sdhc1_init, - .exit = moboard_sdhc1_exit, -}; - -/* - * this pin is dedicated for all mx31moboard systems, so we do it here - */ -#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS) - -#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) -#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) - -static void usb_xcvr_reset(void) -{ - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - - gpio_request(OTG_EN_B, "usb-udc-en"); - gpio_direction_output(OTG_EN_B, 0); - gpio_request(USBH2_EN_B, "usbh2-en"); - gpio_direction_output(USBH2_EN_B, 0); - - gpio_request(USB_RESET_B, "usb-reset"); - gpio_direction_output(USB_RESET_B, 0); - mdelay(1); - gpio_set_value(USB_RESET_B, 1); - mdelay(1); -} - -static int moboard_usbh2_init_hw(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = moboard_usbh2_init_hw, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static int __init moboard_usbh2_init(void) -{ - struct platform_device *pdev; - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (!usbh2_pdata.otg) - return -ENODEV; - - pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - -static const struct gpio_led mx31moboard_leds[] __initconst = { - { - .name = "coreboard-led-0:red:running", - .default_trigger = "heartbeat", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), - }, { - .name = "coreboard-led-1:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), - }, { - .name = "coreboard-led-2:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0), - }, { - .name = "coreboard-led-3:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0), - }, -}; - -static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = { - .num_leds = ARRAY_SIZE(mx31moboard_leds), - .leds = mx31moboard_leds, -}; - -static struct platform_device *devices[] __initdata = { - &mx31moboard_flash, -}; - -static struct mx3_camera_pdata camera_pdata __initdata = { - .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 4800, -}; - -static phys_addr_t mx3_camera_base __initdata; -#define MX3_CAMERA_BUF_SIZE SZ_4M - -static int __init mx31moboard_init_cam(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev; - - imx31_add_ipu_core(); - - pdev = imx31_alloc_mx3_camera(&camera_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX3_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; - -} - -static void mx31moboard_poweroff(void) -{ - struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); - - if (!IS_ERR(clk)) - clk_prepare_enable(clk); - - mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); - - __raw_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); -} - -static int mx31moboard_baseboard; -core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); - -/* - * Board specific initialization. - */ -static void __init mx31moboard_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), - "moboard"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - gpio_led_register_device(-1, &mx31moboard_led_pdata); - - imx31_add_imx2_wdt(); - - imx31_add_imx_uart0(&uart0_pdata); - imx31_add_imx_uart4(&uart4_pdata); - - imx31_add_imx_i2c0(&moboard_i2c0_data); - imx31_add_imx_i2c1(&moboard_i2c1_data); - - imx31_add_spi_imx1(&moboard_spi1_pdata); - imx31_add_spi_imx2(&moboard_spi2_pdata); - - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - moboard_spi_board_info[0].irq = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(moboard_spi_board_info, - ARRAY_SIZE(moboard_spi_board_info)); - - imx31_add_mxc_mmc(0, &sdhc1_pdata); - - mx31moboard_init_cam(); - - usb_xcvr_reset(); - - moboard_usbh2_init(); - - imx31_add_imx_ssi(0, &moboard_ssi_pdata); - - imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); - - pm_power_off = mx31moboard_poweroff; - - switch (mx31moboard_baseboard) { - case MX31NOBOARD: - break; - case MX31DEVBOARD: - mx31moboard_devboard_init(); - break; - case MX31MARXBOT: - mx31moboard_marxbot_init(); - break; - case MX31SMARTBOT: - case MX31EYEBOT: - mx31moboard_smartbot_init(mx31moboard_baseboard); - break; - default: - printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", - mx31moboard_baseboard); - } -} - -static void __init mx31moboard_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static void __init mx31moboard_reserve(void) -{ - /* reserve 4 MiB for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE, - MX3_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") - /* Maintainer: Philippe Retornaz, EPFL Mobots group */ - .atag_offset = 0x100, - .reserve = mx31moboard_reserve, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = mx31moboard_timer_init, - .init_machine = mx31moboard_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c deleted file mode 100644 index a42f4f07051f..000000000000 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * Copyright (C) 2011 Meprolight, Ltd. - * Alex Gershgorin <alexg@meprolight.com> - * - * Modified from i.MX31 3-Stack Development System - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This machine is known as: - * - i.MX35 3-Stack Development System - * - i.MX35 Platform Development Kit (i.MX35 PDK) - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> - -#include <linux/mtd/physmap.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> - -#include <video/platform_lcd.h> - -#include <media/soc_camera.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx35.h" -#include "hardware.h" -#include "iomux-mx35.h" - -#define GPIO_MC9S08DZ60_GPS_ENABLE 0 -#define GPIO_MC9S08DZ60_HDD_ENABLE 4 -#define GPIO_MC9S08DZ60_WIFI_ENABLE 5 -#define GPIO_MC9S08DZ60_LCD_ENABLE 6 -#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8 - -static const struct fb_videomode fb_modedb[] = { - { - /* 800x480 @ 55 Hz */ - .name = "Ceramate-CLAA070VC01", - .refresh = 55, - .xres = 800, - .yres = 480, - .pixclock = 40000, - .left_margin = 40, - .right_margin = 40, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Ceramate-CLAA070VC01", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct i2c_board_info __initdata i2c_devices_3ds[] = { - { - I2C_BOARD_INFO("mc9s08dz60", 0x69), - }, -}; - -static int lcd_power_gpio = -ENXIO; - -static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, void *data) -{ - return !strcmp(chip->label, data); -} - -static void mx35_3ds_lcd_set_power( - struct plat_lcd_data *pd, unsigned int power) -{ - struct gpio_chip *chip; - - if (!gpio_is_valid(lcd_power_gpio)) { - chip = gpiochip_find( - "mc9s08dz60", mc9s08dz60_gpiochip_match); - if (chip) { - lcd_power_gpio = - chip->base + GPIO_MC9S08DZ60_LCD_ENABLE; - if (gpio_request(lcd_power_gpio, "lcd_power") < 0) { - pr_err("error: gpio already requested!\n"); - lcd_power_gpio = -ENXIO; - } - } else { - pr_err("error: didn't find mc9s08dz60 gpio chip\n"); - } - } - - if (gpio_is_valid(lcd_power_gpio)) - gpio_set_value_cansleep(lcd_power_gpio, power); -} - -static struct plat_lcd_data mx35_3ds_lcd_data = { - .set_power = mx35_3ds_lcd_set_power, -}; - -static struct platform_device mx35_3ds_lcd = { - .name = "platform-lcd", - .dev.platform_data = &mx35_3ds_lcd_data, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct physmap_flash_data mx35pdk_flash_data = { - .width = 2, -}; - -static struct resource mx35pdk_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx35pdk_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx35pdk_flash_data, - }, - .resource = &mx35pdk_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct platform_device *devices[] __initdata = { - &mx35pdk_flash, -}; - -static iomux_v3_cfg_t mx35pdk_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* USBH1 */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - /* CSI */ - MX35_PAD_TX1__IPU_CSI_D_6, - MX35_PAD_TX0__IPU_CSI_D_7, - MX35_PAD_CSI_D8__IPU_CSI_D_8, - MX35_PAD_CSI_D9__IPU_CSI_D_9, - MX35_PAD_CSI_D10__IPU_CSI_D_10, - MX35_PAD_CSI_D11__IPU_CSI_D_11, - MX35_PAD_CSI_D12__IPU_CSI_D_12, - MX35_PAD_CSI_D13__IPU_CSI_D_13, - MX35_PAD_CSI_D14__IPU_CSI_D_14, - MX35_PAD_CSI_D15__IPU_CSI_D_15, - MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC, - MX35_PAD_CSI_MCLK__IPU_CSI_MCLK, - MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK, - MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC, - /*PMIC IRQ*/ - MX35_PAD_GPIO2_0__GPIO2_0, -}; - -/* - * Camera support -*/ -static phys_addr_t mx3_camera_base __initdata; -#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M - -static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = { - .flags = MX3_CAMERA_DATAWIDTH_8, - .mclk_10khz = 2000, -}; - -static int __init imx35_3ds_init_camera(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev = - imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata); - - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - if (!mx3_camera_base) - goto err; - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX35_3DS_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; -} - -static struct i2c_board_info mx35_3ds_i2c_camera = { - I2C_BOARD_INFO("ov2640", 0x30), -}; - -static struct soc_camera_link iclink_ov2640 = { - .bus_id = 0, - .board_info = &mx35_3ds_i2c_camera, - .i2c_adapter_id = 0, - .power = NULL, -}; - -static struct platform_device mx35_3ds_ov2640 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_ov2640, - }, -}; - -static struct regulator_consumer_supply sw1_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_consumer_supply vcam_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDA", "0-000a"), -}; - -static struct regulator_consumer_supply vaudio_consumers[] = { - REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"), -}; - -static struct regulator_init_data sw1_init = { - .constraints = { - .name = "SW1", - .min_uV = 600000, - .max_uV = 1375000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .valid_modes_mask = 0, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), - .consumer_supplies = sw1_consumers, -}; - -static struct regulator_init_data sw2_init = { - .constraints = { - .name = "SW2", - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw3_init = { - .constraints = { - .name = "SW3", - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw4_init = { - .constraints = { - .name = "SW4", - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data viohi_init = { - .constraints = { - .name = "VIOHI", - .boot_on = 1, - } -}; - -static struct regulator_init_data vusb_init = { - .constraints = { - .name = "VUSB", - .boot_on = 1, - } -}; - -static struct regulator_init_data vdig_init = { - .constraints = { - .name = "VDIG", - .boot_on = 1, - } -}; - -static struct regulator_init_data vpll_init = { - .constraints = { - .name = "VPLL", - .boot_on = 1, - } -}; - -static struct regulator_init_data vusb2_init = { - .constraints = { - .name = "VUSB2", - .boot_on = 1, - } -}; - -static struct regulator_init_data vvideo_init = { - .constraints = { - .name = "VVIDEO", - .boot_on = 1 - } -}; - -static struct regulator_init_data vaudio_init = { - .constraints = { - .name = "VAUDIO", - .min_uV = 2300000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .boot_on = 1 - }, - .num_consumer_supplies = ARRAY_SIZE(vaudio_consumers), - .consumer_supplies = vaudio_consumers, -}; - -static struct regulator_init_data vcam_init = { - .constraints = { - .name = "VCAM", - .min_uV = 2500000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, - .boot_on = 1 - }, - .num_consumer_supplies = ARRAY_SIZE(vcam_consumers), - .consumer_supplies = vcam_consumers, -}; - -static struct regulator_init_data vgen1_init = { - .constraints = { - .name = "VGEN1", - } -}; - -static struct regulator_init_data vgen2_init = { - .constraints = { - .name = "VGEN2", - .boot_on = 1, - } -}; - -static struct regulator_init_data vgen3_init = { - .constraints = { - .name = "VGEN3", - } -}; - -static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = { - { .id = MC13892_SW1, .init_data = &sw1_init }, - { .id = MC13892_SW2, .init_data = &sw2_init }, - { .id = MC13892_SW3, .init_data = &sw3_init }, - { .id = MC13892_SW4, .init_data = &sw4_init }, - { .id = MC13892_VIOHI, .init_data = &viohi_init }, - { .id = MC13892_VPLL, .init_data = &vpll_init }, - { .id = MC13892_VDIG, .init_data = &vdig_init }, - { .id = MC13892_VUSB2, .init_data = &vusb2_init }, - { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, - { .id = MC13892_VAUDIO, .init_data = &vaudio_init }, - { .id = MC13892_VCAM, .init_data = &vcam_init }, - { .id = MC13892_VGEN1, .init_data = &vgen1_init }, - { .id = MC13892_VGEN2, .init_data = &vgen2_init }, - { .id = MC13892_VGEN3, .init_data = &vgen3_init }, - { .id = MC13892_VUSB, .init_data = &vusb_init }, -}; - -static struct mc13xxx_platform_data mx35_3ds_mc13892_data = { - .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, - .regulators = { - .num_regulators = ARRAY_SIZE(mx35_3ds_regulators), - .regulators = mx35_3ds_regulators, - }, -}; - -#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) - -static struct i2c_board_info mx35_3ds_i2c_mc13892 = { - - I2C_BOARD_INFO("mc13892", 0x08), - .platform_data = &mx35_3ds_mc13892_data, - /* irq number is run-time assigned */ -}; - -static void __init imx35_3ds_init_mc13892(void) -{ - int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq"); - - if (ret) { - pr_err("failed to get pmic irq: %d\n", ret); - return; - } - - mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT); - i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1); -} - -static int mx35_3ds_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -/* OTG config */ -static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -/* - * ENGCM09152 also requires a hardware change. - * Please check the MX35 Chip Errata document for details. - */ -}; - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx35_3ds_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int mx35_3ds_usbh_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY); -} - -/* USB HOST config */ -static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .init = mx35_3ds_usbh_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static bool otg_mode_host __initdata; - -static int __init mx35_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", mx35_3ds_otg_mode); - -static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -/* - * Board specific initialization. - */ -static void __init mx35_3ds_init(void) -{ - struct platform_device *imx35_fb_pdev; - - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(); - imx35_add_mxc_rtc(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx35_add_imx_uart0(&uart_pdata); - - if (otg_mode_host) - imx35_add_mxc_ehci_otg(&otg_pdata); - - imx35_add_mxc_ehci_hs(&usb_host_pdata); - - if (!otg_mode_host) - imx35_add_fsl_usb2_udc(&usb_otg_pdata); - - imx35_add_mxc_nand(&mx35pdk_nand_board_info); - imx35_add_sdhci_esdhc_imx(0, NULL); - - if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1))) - pr_warn("Init of the debugboard failed, all " - "devices on the debugboard are unusable.\n"); - imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); - - i2c_register_board_info( - 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds)); - - imx35_add_ipu_core(); - platform_device_register(&mx35_3ds_ov2640); - imx35_3ds_init_camera(); - - imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata); - mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev; - platform_device_register(&mx35_3ds_lcd); - - imx35_3ds_init_mc13892(); -} - -static void __init mx35pdk_timer_init(void) -{ - mx35_clocks_init(); -} - -static void __init mx35_3ds_reserve(void) -{ - /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE, - MX35_3DS_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX35_3DS, "Freescale MX35PDK") - /* Maintainer: Freescale Semiconductor, Inc */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .init_time = mx35pdk_timer_init, - .init_machine = mx35_3ds_init, - .reserve = mx35_3ds_reserve, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c deleted file mode 100644 index f3d264a636fa..000000000000 --- a/arch/arm/mach-imx/mach-mx51_babbage.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/spi/flash.h> -#include <linux/spi/spi.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx51.h" -#include "hardware.h" -#include "iomux-mx51.h" - -#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7) -#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27) -#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5) -#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14) -#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21) -#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24) -#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25) -#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6) -#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5) - -/* USB_CTRL_1 */ -#define MX51_USB_CTRL_1_OFFSET 0x10 -#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) - -#define MX51_USB_PLLDIV_12_MHZ 0x00 -#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 -#define MX51_USB_PLL_DIV_24_MHZ 0x02 - -static struct gpio_keys_button babbage_buttons[] = { - { - .gpio = BABBAGE_POWER_KEY, - .code = BTN_0, - .desc = "PWR", - .active_low = 1, - .wakeup = 1, - }, -}; - -static const struct gpio_keys_platform_data imx_button_data __initconst = { - .buttons = babbage_buttons, - .nbuttons = ARRAY_SIZE(babbage_buttons), -}; - -static iomux_v3_cfg_t mx51babbage_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* UART2 */ - MX51_PAD_UART2_RXD__UART2_RXD, - MX51_PAD_UART2_TXD__UART2_TXD, - - /* UART3 */ - MX51_PAD_EIM_D25__UART3_RXD, - MX51_PAD_EIM_D26__UART3_TXD, - MX51_PAD_EIM_D27__UART3_RTS, - MX51_PAD_EIM_D24__UART3_CTS, - - /* I2C1 */ - MX51_PAD_EIM_D16__I2C1_SDA, - MX51_PAD_EIM_D19__I2C1_SCL, - - /* I2C2 */ - MX51_PAD_KEY_COL4__I2C2_SCL, - MX51_PAD_KEY_COL5__I2C2_SDA, - - /* HSI2C */ - MX51_PAD_I2C1_CLK__I2C1_CLK, - MX51_PAD_I2C1_DAT__I2C1_DAT, - - /* USB HOST1 */ - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - /* USB HUB reset line*/ - MX51_PAD_GPIO1_7__GPIO1_7, - - /* USB PHY reset line */ - MX51_PAD_EIM_D21__GPIO2_5, - - /* FEC */ - MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDATA1, - MX51_PAD_EIM_CS2__FEC_RDATA2, - MX51_PAD_EIM_CS3__FEC_RDATA3, - MX51_PAD_EIM_CS4__FEC_RX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RX_CLK, - MX51_PAD_NANDF_D9__FEC_RDATA0, - MX51_PAD_NANDF_D8__FEC_TDATA0, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDATA1, - MX51_PAD_NANDF_CS5__FEC_TDATA2, - MX51_PAD_NANDF_CS6__FEC_TDATA3, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - - /* FEC PHY reset line */ - MX51_PAD_EIM_A20__GPIO2_14, - - /* SD 1 */ - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - /* CD/WP from controller */ - MX51_PAD_GPIO1_0__SD1_CD, - MX51_PAD_GPIO1_1__SD1_WP, - - /* SD 2 */ - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - /* CD/WP gpio */ - MX51_PAD_GPIO1_6__GPIO1_6, - MX51_PAD_GPIO1_5__GPIO1_5, - - /* eCSPI1 */ - MX51_PAD_CSPI1_MISO__ECSPI1_MISO, - MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, - MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, - MX51_PAD_CSPI1_SS0__GPIO4_24, - MX51_PAD_CSPI1_SS1__GPIO4_25, - - /* Audio */ - MX51_PAD_AUD3_BB_TXD__AUD3_TXD, - MX51_PAD_AUD3_BB_RXD__AUD3_RXD, - MX51_PAD_AUD3_BB_CK__AUD3_TXC, - MX51_PAD_AUD3_BB_FS__AUD3_TXFS, -}; - -/* Serial ports */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data babbage_i2c_data __initconst = { - .bitrate = 100000, -}; - -static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = { - .bitrate = 400000, -}; - -static struct gpio mx51_babbage_usbh1_gpios[] = { - { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" }, - { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" }, -}; - -static int gpio_usbh1_active(void) -{ - iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27; - int ret; - - /* Set USBH1_STP to GPIO and toggle it */ - mxc_iomux_v3_setup_pad(usbh1stp_gpio); - ret = gpio_request_array(mx51_babbage_usbh1_gpios, - ARRAY_SIZE(mx51_babbage_usbh1_gpios)); - - if (ret) { - pr_debug("failed to get USBH1 pins: %d\n", ret); - return ret; - } - - msleep(100); - gpio_set_value(BABBAGE_USBH1_STP, 1); - gpio_set_value(BABBAGE_USB_PHY_RESET, 1); - gpio_free_array(mx51_babbage_usbh1_gpios, - ARRAY_SIZE(mx51_babbage_usbh1_gpios)); - return 0; -} - -static inline void babbage_usbhub_reset(void) -{ - int ret; - - /* Reset USB hub */ - ret = gpio_request_one(BABBAGE_USB_HUB_RESET, - GPIOF_OUT_INIT_LOW, "GPIO1_7"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); - return; - } - - msleep(2); - /* Deassert reset */ - gpio_set_value(BABBAGE_USB_HUB_RESET, 1); -} - -static inline void babbage_fec_reset(void) -{ - int ret; - - /* reset FEC PHY */ - ret = gpio_request_one(BABBAGE_FEC_PHY_RESET, - GPIOF_OUT_INIT_LOW, "fec-phy-reset"); - if (ret) { - printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); - return; - } - msleep(1); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); -} - -/* This function is board specific as the bit mask for the plldiv will also -be different for other Freescale SoCs, thus a common bitmask is not -possible and cannot get place in /plat-mxc/ehci.c.*/ -static int initialize_otg_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* Set the PHY clock to 19.2MHz */ - v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; - v |= MX51_USB_PLL_DIV_19_2_MHZ; - __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY); -} - -static int initialize_usbh1_port(struct platform_device *pdev) -{ - u32 v; - void __iomem *usb_base; - void __iomem *usbother_base; - - usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); - if (!usb_base) - return -ENOMEM; - usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; - - /* The clock for the USBH1 ULPI port will come externally from the PHY. */ - v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); - __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); - iounmap(usb_base); - - mdelay(10); - - return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_ITC_NO_THRESHOLD); -} - -static const struct mxc_usbh_platform_data dr_utmi_config __initconst = { - .init = initialize_otg_port, - .portsc = MXC_EHCI_UTMI_16BIT, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, -}; - -static const struct mxc_usbh_platform_data usbh1_config __initconst = { - .init = initialize_usbh1_port, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init babbage_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", babbage_otg_mode); - -static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = { - { - .modalias = "mtd_dataflash", - .max_speed_hz = 25000000, - .bus_num = 0, - .chip_select = 1, - .mode = SPI_MODE_0, - .platform_data = NULL, - }, -}; - -static int mx51_babbage_spi_cs[] = { - BABBAGE_ECSPI1_CS0, - BABBAGE_ECSPI1_CS1, -}; - -static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = { - .chipselect = mx51_babbage_spi_cs, - .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs), -}; - -static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = { - .cd_type = ESDHC_CD_CONTROLLER, - .wp_type = ESDHC_WP_CONTROLLER, -}; - -static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = { - .cd_gpio = BABBAGE_SD2_CD, - .wp_gpio = BABBAGE_SD2_WP, - .cd_type = ESDHC_CD_GPIO, - .wp_type = ESDHC_WP_GPIO, -}; - -void __init imx51_babbage_common_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, - ARRAY_SIZE(mx51babbage_pads)); -} - -/* - * Board specific initialization. - */ -static void __init mx51_babbage_init(void) -{ - iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; - iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21, - PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH); - - imx51_soc_init(); - - imx51_babbage_common_init(); - - imx51_add_imx_uart(0, &uart_pdata); - imx51_add_imx_uart(1, NULL); - imx51_add_imx_uart(2, &uart_pdata); - - babbage_fec_reset(); - imx51_add_fec(NULL); - - /* Set the PAD settings for the pwr key. */ - mxc_iomux_v3_setup_pad(power_key); - imx_add_gpio_keys(&imx_button_data); - - imx51_add_imx_i2c(0, &babbage_i2c_data); - imx51_add_imx_i2c(1, &babbage_i2c_data); - imx51_add_hsi2c(&babbage_hsi2c_data); - - if (otg_mode_host) - imx51_add_mxc_ehci_otg(&dr_utmi_config); - else { - initialize_otg_port(NULL); - imx51_add_fsl_usb2_udc(&usb_pdata); - } - - gpio_usbh1_active(); - imx51_add_mxc_ehci_hs(1, &usbh1_config); - /* setback USBH1_STP to be function */ - mxc_iomux_v3_setup_pad(usbh1stp); - babbage_usbhub_reset(); - - imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data); - imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data); - - spi_register_board_info(mx51_babbage_spi_board_info, - ARRAY_SIZE(mx51_babbage_spi_board_info)); - imx51_add_ecspi(0, &mx51_babbage_spi_pdata); - imx51_add_imx2_wdt(0); -} - -static void __init mx51_babbage_timer_init(void) -{ - mx51_clocks_init(32768, 24000000, 22579200, 0); -} - -MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") - /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ - .atag_offset = 0x100, - .map_io = mx51_map_io, - .init_early = imx51_init_early, - .init_irq = mx51_init_irq, - .handle_irq = imx51_handle_irq, - .init_time = mx51_babbage_timer_init, - .init_machine = mx51_babbage_init, - .init_late = imx51_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c deleted file mode 100644 index a27faaba98ec..000000000000 --- a/arch/arm/mach-imx/mach-mxt_td60.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/irq.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <linux/gpio.h> -#include <linux/i2c/pca953x.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -static const int mxt_td60_pins[] __initconst = { - /* UART0 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART1 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART2 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* FB */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA25_PF_CLS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* OWIRE */ - PE16_AF_OWIRE, - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - PF8_AF_ATA_IORDY, - /* SDHC2*/ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -}; - -static const struct mxc_nand_platform_data -mxt_td60_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = { - .bitrate = 100000, -}; - -/* PCA9557 */ -static int mxt_td60_pca9557_setup(struct i2c_client *client, - unsigned gpio_base, unsigned ngpio, - void *context) -{ - static int mxt_td60_gpio_value[] = { - -1, -1, -1, -1, -1, -1, -1, 1 - }; - int n; - - for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) { - gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp"); - if (mxt_td60_gpio_value[n] < 0) - gpio_direction_input(gpio_base + n); - else - gpio_direction_output(gpio_base + n, - mxt_td60_gpio_value[n]); - gpio_export(gpio_base + n, 0); - } - - return 0; -} - -static struct pca953x_platform_data mxt_td60_pca9557_pdata = { - .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */ - .invert = 0, /* Do not invert */ - .setup = mxt_td60_pca9557_setup, -}; - -static struct i2c_board_info mxt_td60_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9557", 0x18), - .platform_data = &mxt_td60_pca9557_pdata, - }, -}; - -static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mxt_td60_i2c2_devices[] = { -}; - -static struct imx_fb_videomode mxt_td60_modes[] = { - { - .mode = { - .name = "Chimei LW700AT9003", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 30303, - .hsync_len = 64, - .left_margin = 0x67, - .right_margin = 0x68, - .vsync_len = 16, - .upper_margin = 0x0f, - .lower_margin = 0x0f, - }, - .bpp = 16, - .pcr = 0xFA208B83, - }, -}; - -static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = { - .mode = mxt_td60_modes, - .num_modes = ARRAY_SIZE(mxt_td60_modes), - - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq, - IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data); -} - -static void mxt_td60_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mxt_td60_sdhc1_init, - .exit = mxt_td60_sdhc1_exit, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mxt_td60_board_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), - "MXT_TD60"); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - imx27_add_mxc_nand(&mxt_td60_nand_board_info); - - i2c_register_board_info(0, mxt_td60_i2c_devices, - ARRAY_SIZE(mxt_td60_i2c_devices)); - - i2c_register_board_info(1, mxt_td60_i2c2_devices, - ARRAY_SIZE(mxt_td60_i2c2_devices)); - - imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); - imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); - imx27_add_imx_fb(&mxt_td60_fb_data); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_fec(NULL); -} - -static void __init mxt_td60_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") - /* maintainer: Maxtrack Industrial */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = mxt_td60_timer_init, - .init_machine = mxt_td60_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c deleted file mode 100644 index 19bb6441a7d4..000000000000 --- a/arch/arm/mach-imx/mach-pca100.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/dma-mapping.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" -#include "ulpi.h" - -#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) -#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) -#define SPI1_SS0 (GPIO_PORTD + 28) -#define SPI1_SS1 (GPIO_PORTD + 27) -#define SD2_CD (GPIO_PORTC + 29) - -static const int pca100_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* SDHC */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - SD2_CD | GPIO_GPIO | GPIO_IN, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* onboard I2C */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* external I2C */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* SPI1 */ - PD25_PF_CSPI1_RDY, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* USBH2 */ - USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA26_PF_PS, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA31_PF_OE_ACD, - /* free GPIO */ - GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */ - GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */ - GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */ -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -pca100_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pca100_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("lm75", 0x4a), - } -}; - -static struct spi_eeprom at25320 = { - .name = "at25320an", - .byte_len = 4096, - .page_size = 32, - .flags = EE_ADDR2, -}; - -static struct spi_board_info pca100_spi_board_info[] __initdata = { - { - .modalias = "at25", - .max_speed_hz = 30000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &at25320, - }, -}; - -static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1}; - -static const struct spi_imx_master pca100_spi0_data __initconst = { - .chipselect = pca100_spi_cs, - .num_chipselect = ARRAY_SIZE(pca100_spi_cs), -}; - -static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) -{ - mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); - gpio_set_value(GPIO_PORTC + 20, 1); - udelay(2); - gpio_set_value(GPIO_PORTC + 20, 0); - mxc_gpio_mode(PC20_PF_SSI1_FS); - msleep(2); -} - -static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) -{ - mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */ - gpio_set_value(GPIO_PORTC + 20, 0); - mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */ - gpio_set_value(GPIO_PORTC + 22, 0); - mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */ - gpio_set_value(GPIO_PORTC + 28, 0); - udelay(10); - gpio_set_value(GPIO_PORTC + 28, 1); - mxc_gpio_mode(PC20_PF_SSI1_FS); - mxc_gpio_mode(PC22_PF_SSI1_TXD); - msleep(2); -} - -static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = { - .ac97_reset = pca100_ac97_cold_reset, - .ac97_warm_reset = pca100_ac97_warm_reset, - .flags = IMX_SSI_USE_AC97, -}; - -static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "imx-mmc-detect", data); - if (ret) - printk(KERN_ERR - "pca100: Failed to reuest irq for sd/mmc detection\n"); - - return ret; -} - -static void pca100_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .init = pca100_sdhc2_init, - .exit = pca100_sdhc2_exit, -}; - -static int otg_phy_init(struct platform_device *pdev) -{ - gpio_set_value(OTG_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int usbh2_phy_init(struct platform_device *pdev) -{ - gpio_set_value(USBH2_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_phy_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init pca100_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", pca100_otg_mode); - -/* framebuffer info */ -static struct imx_fb_videomode pca100_fb_modes[] = { - { - .mode = { - .name = "EMERGING-ETV570G0DHU", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39722, /* in ps (25.175 MHz) */ - .hsync_len = 30, - .left_margin = 114, - .right_margin = 16, - .vsync_len = 3, - .upper_margin = 32, - .lower_margin = 0, - }, - /* - * TFT - * Pixel pol active high - * HSYNC active low - * VSYNC active low - * use HSYNC for ACD count - * line clock disable while idle - * always enable line clock even if no data - */ - .pcr = 0xf0c08080, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data pca100_fb_data __initconst = { - .mode = pca100_fb_modes, - .num_modes = ARRAY_SIZE(pca100_fb_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static void __init pca100_init(void) -{ - int ret; - - imx27_soc_init(); - - ret = mxc_gpio_setup_multiple_pins(pca100_pins, - ARRAY_SIZE(pca100_pins), "PCA100"); - if (ret) - printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); - - imx27_add_imx_ssi(0, &pca100_ssi_pdata); - - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_mxc_mmc(1, &sdhc_pdata); - - imx27_add_mxc_nand(&pca100_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, pca100_i2c_devices, - ARRAY_SIZE(pca100_i2c_devices)); - - imx27_add_imx_i2c(1, &pca100_i2c1_data); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); - mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); - spi_register_board_info(pca100_spi_board_info, - ARRAY_SIZE(pca100_spi_board_info)); - imx27_add_spi_imx0(&pca100_spi0_data); - - gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); - gpio_direction_output(OTG_PHY_CS_GPIO, 1); - gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); - gpio_direction_output(USBH2_PHY_CS_GPIO, 1); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } else { - gpio_set_value(OTG_PHY_CS_GPIO, 0); - imx27_add_fsl_usb2_udc(&otg_device_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create( - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - if (usbh2_pdata.otg) - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); - - imx27_add_imx_fb(&pca100_fb_data); - - imx27_add_fec(NULL); - imx27_add_imx2_wdt(); - imx27_add_mxc_w1(); -} - -static void __init pca100_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(PCA100, "phyCARD-i.MX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_machine = pca100_init, - .init_time = pca100_timer_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c deleted file mode 100644 index bc0261e99d39..000000000000 --- a/arch/arm/mach-imx/mach-pcm037.c +++ /dev/null @@ -1,712 +0,0 @@ -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/delay.h> -#include <linux/spi/spi.h> -#include <linux/irq.h> -#include <linux/can/platform/sja1000.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/gfp.h> -#include <linux/memblock.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <media/soc_camera.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "pcm037.h" -#include "ulpi.h" - -static enum pcm037_board_variant pcm037_instance = PCM037_PCM970; - -static int __init pcm037_variant_setup(char *str) -{ - if (!strcmp("eet", str)) - pcm037_instance = PCM037_EET; - else if (strcmp("pcm970", str)) - pr_warning("Unknown pcm037 baseboard variant %s\n", str); - - return 1; -} - -/* Supported values: "pcm970" (default) and "eet" */ -__setup("pcm037_variant=", pcm037_variant_setup); - -enum pcm037_board_variant pcm037_variant(void) -{ - return pcm037_instance; -} - -/* UART1 with RTS/CTS handshake signals */ -static unsigned int pcm037_uart1_handshake_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, -}; - -/* UART1 without RTS/CTS handshake signals */ -static unsigned int pcm037_uart1_pins[] = { - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, -}; - -static unsigned int pcm037_pins[] = { - /* I2C */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - MX31_PIN_CSPI2_SS2__I2C3_SDA, - MX31_PIN_CSPI2_SCLK__I2C3_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ - /* SPI1 */ - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* UART2 */ - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - /* UART3 */ - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - /* LAN9217 irq pin */ - IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), - /* Onewire */ - MX31_PIN_BATT_LINE__OWIRE, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_D3_REV__D3_REV, - MX31_PIN_CONTRAST__CONTRAST, - MX31_PIN_D3_SPL__D3_SPL, - MX31_PIN_D3_CLS__D3_CLS, - MX31_PIN_LCS0__GPI03_23, - /* CSI */ - IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO), - MX31_PIN_CSI_D6__CSI_D6, - MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, - MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, - MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, - MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, - MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, - MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, - MX31_PIN_CSI_VSYNC__CSI_VSYNC, - /* GPIO */ - IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), - /* OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /* USB host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), -}; - -static struct physmap_flash_data pcm037_flash_data = { - .width = 2, -}; - -static struct resource pcm037_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm037_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm037_flash_data, - }, - .resource = &pcm037_flash_resource, - .num_resources = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct resource smsc911x_resources[] = { - { - .start = MX31_CS1_BASE_ADDR + 0x300, - .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY | - SMSC911X_SAVE_MAC_ADDRESS, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device pcm037_eth = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -static struct platdata_mtd_ram pcm038_sram_data = { - .bankwidth = 2, -}; - -static struct resource pcm038_sram_resource = { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm037_sram_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &pcm038_sram_data, - }, - .num_resources = 1, - .resource = &pcm038_sram_resource, -}; - -static const struct mxc_nand_platform_data -pcm037_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = { - .bitrate = 20000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static int pcm037_camera_power(struct device *dev, int on) -{ - /* disable or enable the camera in X7 or X8 PCM970 connector */ - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on); - return 0; -} - -static struct i2c_board_info pcm037_i2c_camera[] = { - { - I2C_BOARD_INFO("mt9t031", 0x5d), - }, { - I2C_BOARD_INFO("mt9v022", 0x48), - }, -}; - -static struct soc_camera_link iclink_mt9v022 = { - .bus_id = 0, /* Must match with the camera ID */ - .board_info = &pcm037_i2c_camera[1], - .i2c_adapter_id = 2, -}; - -static struct soc_camera_link iclink_mt9t031 = { - .bus_id = 0, /* Must match with the camera ID */ - .power = pcm037_camera_power, - .board_info = &pcm037_i2c_camera[0], - .i2c_adapter_id = 2, -}; - -static struct i2c_board_info pcm037_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - } -}; - -static struct platform_device pcm037_mt9t031 = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &iclink_mt9t031, - }, -}; - -static struct platform_device pcm037_mt9v022 = { - .name = "soc-camera-pdrv", - .id = 1, - .dev = { - .platform_data = &iclink_mt9v022, - }, -}; - -/* Not connected by default */ -#ifdef PCM970_SDHC_RW_SWITCH -static int pcm970_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6)); -} -#endif - -#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6) -#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6) - -static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_GPIO_DET); - -#ifdef PCM970_SDHC_RW_SWITCH - ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_GPIO_WP); -#endif - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: -#ifdef PCM970_SDHC_RW_SWITCH - gpio_free(SDHC1_GPIO_WP); -err_gpio_free: -#endif - gpio_free(SDHC1_GPIO_DET); - - return ret; -} - -static void pcm970_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data); - gpio_free(SDHC1_GPIO_DET); - gpio_free(SDHC1_GPIO_WP); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { -#ifdef PCM970_SDHC_RW_SWITCH - .get_ro = pcm970_sdhc1_get_ro, -#endif - .init = pcm970_sdhc1_init, - .exit = pcm970_sdhc1_exit, -}; - -struct mx3_camera_pdata camera_pdata __initdata = { - .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 2000, -}; - -static phys_addr_t mx3_camera_base __initdata; -#define MX3_CAMERA_BUF_SIZE SZ_4M - -static int __init pcm037_init_camera(void) -{ - int dma, ret = -ENOMEM; - struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata); - - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - dma = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX3_CAMERA_BUF_SIZE, - DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); - if (!(dma & DMA_MEMORY_MAP)) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; -} - -static struct platform_device *devices[] __initdata = { - &pcm037_flash, - &pcm037_sram_device, - &pcm037_mt9t031, - &pcm037_mt9v022, -}; - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz Sharp */ - .name = "Sharp-LQ035Q7DH06-QVGA", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | - FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "CMEL-OLED", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata = { - .name = "Sharp-LQ035Q7DH06-QVGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct resource pcm970_sja1000_resources[] = { - { - .start = MX31_CS5_BASE_ADDR, - .end = MX31_CS5_BASE_ADDR + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -struct sja1000_platform_data pcm970_sja1000_platform_data = { - .osc_freq = 16000000, - .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, - .cdr = CDR_CBP, -}; - -static struct platform_device pcm970_sja1000 = { - .name = "sja1000_platform", - .dev = { - .platform_data = &pcm970_sja1000_platform_data, - }, - .resource = pcm970_sja1000_resources, - .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), -}; - -static int pcm037_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = pcm037_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int pcm037_usbh2_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = pcm037_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init pcm037_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", pcm037_otg_mode); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -/* - * Board specific initialization. - */ -static void __init pcm037_init(void) -{ - int ret; - - imx31_soc_init(); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - mxc_iomux_set_gpr(MUX_PGP_UH2, 1); - - mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), - "pcm037"); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ - | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - if (pcm037_variant() == PCM037_EET) - mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, - ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); - else - mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins, - ARRAY_SIZE(pcm037_uart1_handshake_pins), - "pcm037_uart1"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx31_add_imx2_wdt(); - imx31_add_imx_uart0(&uart_pdata); - /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ - imx31_add_imx_uart1(&uart_pdata); - imx31_add_imx_uart2(&uart_pdata); - - imx31_add_mxc_w1(); - - /* LAN9217 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); - if (ret) - pr_warning("could not get LAN irq gpio\n"); - else { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - smsc911x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - smsc911x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - platform_device_register(&pcm037_eth); - } - - - /* I2C adapters and devices */ - i2c_register_board_info(1, pcm037_i2c_devices, - ARRAY_SIZE(pcm037_i2c_devices)); - - imx31_add_imx_i2c1(&pcm037_i2c1_data); - imx31_add_imx_i2c2(&pcm037_i2c2_data); - - imx31_add_mxc_nand(&pcm037_nand_board_info); - imx31_add_mxc_mmc(0, &sdhc_pdata); - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* CSI */ - /* Camera power: default - off */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power"); - if (!ret) - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); - else - iclink_mt9t031.power = NULL; - - pcm037_init_camera(); - - pcm970_sja1000_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105))); - pcm970_sja1000_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105))); - platform_device_register(&pcm970_sja1000); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx31_add_mxc_ehci_otg(&otg_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - if (!otg_mode_host) - imx31_add_fsl_usb2_udc(&otg_device_pdata); - -} - -static void __init pcm037_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static void __init pcm037_reserve(void) -{ - /* reserve 4 MiB for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE, - MX3_CAMERA_BUF_SIZE); -} - -static void __init pcm037_init_late(void) -{ - pcm037_eet_init_devices(); -} - -MACHINE_START(PCM037, "Phytec Phycore pcm037") - /* Maintainer: Pengutronix */ - .atag_offset = 0x100, - .reserve = pcm037_reserve, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = pcm037_timer_init, - .init_machine = pcm037_init, - .init_late = pcm037_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c deleted file mode 100644 index 8fd8255068ee..000000000000 --- a/arch/arm/mach-imx/mach-pcm037_eet.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> - -#include <asm/mach-types.h> - -#include "pcm037.h" -#include "common.h" -#include "devices-imx31.h" -#include "iomux-mx3.h" - -static unsigned int pcm037_eet_pins[] = { - /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */ - IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO), - /* GPIO keys */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */ - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */ - IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */ - IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */ - IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */ - IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */ - IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */ - IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */ - IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */ - IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */ - IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */ - IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */ - IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */ - IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */ - - /* LEDs */ - IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */ - IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */ - IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */ - IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */ -}; - -/* SPI */ -static struct spi_board_info pcm037_spi_dev[] = { - { - .modalias = "dac124s085", - .max_speed_hz = 400000, - .bus_num = 0, - .chip_select = 0, /* Index in pcm037_spi1_cs[] */ - .mode = SPI_CPHA, - }, -}; - -/* Platform Data for MXC CSPI */ -static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)}; - -static const struct spi_imx_master pcm037_spi1_pdata __initconst = { - .chipselect = pcm037_spi1_cs, - .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs), -}; - -/* GPIO-keys input device */ -static struct gpio_keys_button pcm037_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_L, - .gpio = 0, - .desc = "Wheel Manual", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_A, - .gpio = 1, - .desc = "Wheel AF", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_V, - .gpio = 2, - .desc = "Wheel View", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_M, - .gpio = 3, - .desc = "Wheel Menu", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_UP, - .gpio = 32, - .desc = "Nav Pad Up", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_RIGHT, - .gpio = 33, - .desc = "Nav Pad Right", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_DOWN, - .gpio = 34, - .desc = "Nav Pad Down", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_LEFT, - .gpio = 35, - .desc = "Nav Pad Left", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_ENTER, - .gpio = 38, - .desc = "Nav Pad Ok", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_O, - .gpio = 39, - .desc = "Wheel Off", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_FORWARD, - .gpio = 50, - .desc = "Focus Forward", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_BACK, - .gpio = 51, - .desc = "Focus Backward", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_MIDDLE, - .gpio = 52, - .desc = "Release Half", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_EXTRA, - .gpio = 53, - .desc = "Release Full", - .wakeup = 0, - }, -}; - -static const struct gpio_keys_platform_data - pcm037_gpio_keys_platform_data __initconst = { - .buttons = pcm037_gpio_keys, - .nbuttons = ARRAY_SIZE(pcm037_gpio_keys), - .rep = 0, /* No auto-repeat */ -}; - -int __init pcm037_eet_init_devices(void) -{ - if (pcm037_variant() != PCM037_EET) - return 0; - - mxc_iomux_setup_multiple_pins(pcm037_eet_pins, - ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet"); - - /* SPI */ - spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); - imx31_add_spi_imx0(&pcm037_spi1_pdata); - - imx_add_gpio_keys(&pcm037_gpio_keys_platform_data); - - return 0; -} diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c deleted file mode 100644 index e805ac273e9c..000000000000 --- a/arch/arm/mach-imx/mach-pcm038.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/io.h> -#include <linux/mtd/plat-ram.h> -#include <linux/mtd/physmap.h> -#include <linux/platform_device.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/irq.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "board-pcm038.h" -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" -#include "ulpi.h" - -static const int pcm038_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART2 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART3 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* SPI1 */ - PD25_PF_CSPI1_RDY, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* SSI4 */ - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD, - PC18_PF_SSI4_TXD, - PC19_PF_SSI4_CLK, - /* USB host */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, -}; - -/* - * Phytec's PCM038 comes with 2MiB battery buffered SRAM, - * 16 bit width - */ - -static struct platdata_mtd_ram pcm038_sram_data = { - .bankwidth = 2, -}; - -static struct resource pcm038_sram_resource = { - .start = MX27_CS1_BASE_ADDR, - .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm038_sram_mtd_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &pcm038_sram_data, - }, - .num_resources = 1, - .resource = &pcm038_sram_resource, -}; - -/* - * Phytec's phyCORE-i.MX27 comes with 32MiB flash, - * 16 bit width - */ -static struct physmap_flash_data pcm038_flash_data = { - .width = 2, -}; - -static struct resource pcm038_flash_resource = { - .start = 0xc0000000, - .end = 0xc1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm038_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm038_flash_data, - }, - .num_resources = 1, - .resource = &pcm038_flash_resource, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -pcm038_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct platform_device *platform_devices[] __initdata = { - &pcm038_nor_mtd_device, - &pcm038_sram_mtd_device, -}; - -/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and - * setup other stuffs to access the sram. */ -static void __init pcm038_init_sram(void) -{ - __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1))); - __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1))); - __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1))); -} - -static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pcm038_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("lm75", 0x4a), - } -}; - -static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; - -static const struct spi_imx_master pcm038_spi0_data __initconst = { - .chipselect = pcm038_spi_cs, - .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), -}; - -static struct regulator_consumer_supply sdhc1_consumers[] = { - { - .dev_name = "imx21-mmc.1", - .supply = "sdhc_vcc", - }, -}; - -static struct regulator_init_data sdhc1_data = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3400000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 0, - }, - .num_consumer_supplies = ARRAY_SIZE(sdhc1_consumers), - .consumer_supplies = sdhc1_consumers, -}; - -static struct regulator_consumer_supply cam_consumers[] = { - { - .dev_name = NULL, - .supply = "imx_cam_vcc", - }, -}; - -static struct regulator_init_data cam_data = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3400000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 0, - }, - .num_consumer_supplies = ARRAY_SIZE(cam_consumers), - .consumer_supplies = cam_consumers, -}; - -static struct mc13xxx_regulator_init_data pcm038_regulators[] = { - { - .id = MC13783_REG_VCAM, - .init_data = &cam_data, - }, { - .id = MC13783_REG_VMMC1, - .init_data = &sdhc1_data, - }, -}; - -static struct mc13xxx_platform_data pcm038_pmic = { - .regulators = { - .regulators = pcm038_regulators, - .num_regulators = ARRAY_SIZE(pcm038_regulators), - }, - .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, -}; - -static struct spi_board_info pcm038_spi_board_info[] __initdata = { - { - .modalias = "mc13783", - /* irq number is run-time assigned */ - .max_speed_hz = 300000, - .bus_num = 0, - .chip_select = 0, - .platform_data = &pcm038_pmic, - .mode = SPI_CS_HIGH, - } -}; - -static int pcm038_usbh2_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { - .init = pcm038_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static void __init pcm038_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), - "PCM038"); - - pcm038_init_sram(); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - - mxc_gpio_mode(PE16_AF_OWIRE); - imx27_add_mxc_nand(&pcm038_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, pcm038_i2c_devices, - ARRAY_SIZE(pcm038_i2c_devices)); - - imx27_add_imx_i2c(1, &pcm038_i2c1_data); - - /* PE18 for user-LED D40 */ - mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); - - /* MC13783 IRQ */ - mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN); - - imx27_add_spi_imx0(&pcm038_spi0_data); - pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23)); - spi_register_board_info(pcm038_spi_board_info, - ARRAY_SIZE(pcm038_spi_board_info)); - - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); - - imx27_add_fec(NULL); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - imx27_add_imx2_wdt(); - imx27_add_mxc_w1(); - -#ifdef CONFIG_MACH_PCM970_BASEBOARD - pcm970_baseboard_init(); -#endif -} - -static void __init pcm038_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(PCM038, "phyCORE-i.MX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .handle_irq = imx27_handle_irq, - .init_time = pcm038_timer_init, - .init_machine = pcm038_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c deleted file mode 100644 index b726cb1c5fdd..000000000000 --- a/arch/arm/mach-imx/mach-pcm043.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright (C) 2009 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/smc911x.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx35.h" -#include "hardware.h" -#include "iomux-mx35.h" -#include "ulpi.h" - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz */ - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Sharp-LQ035Q7", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data pcm043_flash_data = { - .width = 2, -}; - -static struct resource pcm043_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm043_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm043_flash_data, - }, - .resource = &pcm043_flash_resource, - .num_resources = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { - .bitrate = 50000, -}; - -static struct at24_platform_data board_eeprom = { - .byte_len = 4096, - .page_size = 32, - .flags = AT24_FLAG_ADDR16, -}; - -static struct i2c_board_info pcm043_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ - .platform_data = &board_eeprom, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -static struct platform_device *devices[] __initdata = { - &pcm043_flash, -}; - -static iomux_v3_cfg_t pcm043_pads[] = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - /* gpio */ - MX35_PAD_ATA_CS0__GPIO2_6, - /* USB host */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, - /* SSI */ - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, - MX35_PAD_STXD4__AUDMUX_AUD4_TXD, - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, - MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* CAN2 */ - MX35_PAD_TX5_RX0__CAN2_TXCAN, - MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* esdhc */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ - MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ -}; - -#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) -#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) -#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) -#define SD1_GPIO_WP IMX_GPIO_NR(2, 23) -#define SD1_GPIO_CD IMX_GPIO_NR(2, 24) - -static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) -{ - iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - int ret; - - ret = gpio_request(AC97_GPIO_TXFS, "SSI"); - if (ret) { - printk("failed to get GPIO_TXFS: %d\n", ret); - return; - } - - mxc_iomux_v3_setup_pad(txfs_gpio); - - /* warm reset */ - gpio_direction_output(AC97_GPIO_TXFS, 1); - udelay(2); - gpio_set_value(AC97_GPIO_TXFS, 0); - - gpio_free(AC97_GPIO_TXFS); - mxc_iomux_v3_setup_pad(txfs); -} - -static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) -{ - iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; - iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; - iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; - int ret; - - ret = gpio_request(AC97_GPIO_TXFS, "SSI"); - if (ret) - goto err1; - - ret = gpio_request(AC97_GPIO_TXD, "SSI"); - if (ret) - goto err2; - - ret = gpio_request(AC97_GPIO_RESET, "SSI"); - if (ret) - goto err3; - - mxc_iomux_v3_setup_pad(txfs_gpio); - mxc_iomux_v3_setup_pad(txd_gpio); - mxc_iomux_v3_setup_pad(reset_gpio); - - gpio_direction_output(AC97_GPIO_TXFS, 0); - gpio_direction_output(AC97_GPIO_TXD, 0); - - /* cold reset */ - gpio_direction_output(AC97_GPIO_RESET, 0); - udelay(10); - gpio_direction_output(AC97_GPIO_RESET, 1); - - mxc_iomux_v3_setup_pad(txd); - mxc_iomux_v3_setup_pad(txfs); - - gpio_free(AC97_GPIO_RESET); -err3: - gpio_free(AC97_GPIO_TXD); -err2: - gpio_free(AC97_GPIO_TXFS); -err1: - if (ret) - printk("%s failed with %d\n", __func__, ret); - mdelay(1); -} - -static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { - .ac97_reset = pcm043_ac97_cold_reset, - .ac97_warm_reset = pcm043_ac97_warm_reset, - .flags = IMX_SSI_USE_AC97, -}; - -static const struct mxc_nand_platform_data -pcm037_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static int pcm043_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = pcm043_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int pcm043_usbh1_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = pcm043_usbh1_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -static bool otg_mode_host __initdata; - -static int __init pcm043_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", pcm043_otg_mode); - -static struct esdhc_platform_data sd1_pdata = { - .wp_gpio = SD1_GPIO_WP, - .cd_gpio = SD1_GPIO_CD, - .wp_type = ESDHC_WP_GPIO, - .cd_type = ESDHC_CD_GPIO, -}; - -/* - * Board specific initialization. - */ -static void __init pcm043_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - - imx35_add_fec(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx35_add_imx2_wdt(); - - imx35_add_imx_uart0(&uart_pdata); - imx35_add_mxc_nand(&pcm037_nand_board_info); - imx35_add_imx_ssi(0, &pcm043_ssi_pdata); - - imx35_add_imx_uart1(&uart_pdata); - - i2c_register_board_info(0, pcm043_i2c_devices, - ARRAY_SIZE(pcm043_i2c_devices)); - - imx35_add_imx_i2c0(&pcm043_i2c0_data); - - imx35_add_ipu_core(); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx35_add_mxc_ehci_otg(&otg_pdata); - } - imx35_add_mxc_ehci_hs(&usbh1_pdata); - - if (!otg_mode_host) - imx35_add_fsl_usb2_udc(&otg_device_pdata); - - imx35_add_flexcan1(); - imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); -} - -static void __init pcm043_timer_init(void) -{ - mx35_clocks_init(); -} - -MACHINE_START(PCM043, "Phytec Phycore pcm043") - /* Maintainer: Pengutronix */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .init_time = pcm043_timer_init, - .init_machine = pcm043_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c deleted file mode 100644 index 22af27ed457e..000000000000 --- a/arch/arm/mach-imx/mach-qong.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/memory.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/nand.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/page.h> -#include <asm/setup.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* FPGA defines */ -#define QONG_FPGA_VERSION(major, minor, rev) \ - (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) - -#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR -#define QONG_FPGA_PERIPH_SIZE (1 << 24) - -#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR -#define QONG_FPGA_CTRL_SIZE 0x10 -/* FPGA control registers */ -#define QONG_FPGA_CTRL_VERSION 0x00 - -#define QONG_DNET_ID 1 -#define QONG_DNET_BASEADDR \ - (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) -#define QONG_DNET_SIZE 0x00001000 - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 -}; - -static inline void __init mxc_init_imx_uart(void) -{ - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), - "uart-0"); - imx31_add_imx_uart0(&uart_pdata); -} - -static struct resource dnet_resources[] = { - { - .name = "dnet-memory", - .start = QONG_DNET_BASEADDR, - .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dnet_device = { - .name = "dnet", - .id = -1, - .num_resources = ARRAY_SIZE(dnet_resources), - .resource = dnet_resources, -}; - -static int __init qong_init_dnet(void) -{ - int ret; - - dnet_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)); - dnet_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)); - ret = platform_device_register(&dnet_device); - return ret; -} - -/* MTD NOR flash */ - -static struct physmap_flash_data qong_flash_data = { - .width = 2, -}; - -static struct resource qong_flash_resource = { - .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + SZ_128M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device qong_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &qong_flash_data, - }, - .resource = &qong_flash_resource, - .num_resources = 1, -}; - -static void qong_init_nor_mtd(void) -{ - (void)platform_device_register(&qong_nor_mtd_device); -} - -/* - * Hardware specific access to control-lines - */ -static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *nand_chip = mtd->priv; - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24)); - else - writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23)); -} - -/* - * Read the Device Ready pin. - */ -static int qong_nand_device_ready(struct mtd_info *mtd) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB)); -} - -static void qong_nand_select_chip(struct mtd_info *mtd, int chip) -{ - if (chip >= 0) - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); - else - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1); -} - -static struct platform_nand_data qong_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 20, - .options = 0, - }, - .ctrl = { - .cmd_ctrl = qong_nand_cmd_ctrl, - .dev_ready = qong_nand_device_ready, - .select_chip = qong_nand_select_chip, - } -}; - -static struct resource qong_nand_resource = { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device qong_nand_device = { - .name = "gen_nand", - .id = -1, - .dev = { - .platform_data = &qong_nand_data, - }, - .num_resources = 1, - .resource = &qong_nand_resource, -}; - -static void __init qong_init_nand_mtd(void) -{ - /* init CS */ - __raw_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); - __raw_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); - __raw_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); - - mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); - - /* enable pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); - - /* ready/busy pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); - - /* write protect pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); - - platform_device_register(&qong_nand_device); -} - -static void __init qong_init_fpga(void) -{ - void __iomem *regs; - u32 fpga_ver; - - regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE); - if (!regs) { - printk(KERN_ERR "%s: failed to map registers, aborting.\n", - __func__); - return; - } - - fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION); - iounmap(regs); - printk(KERN_INFO "Qong FPGA version %d.%d.%d\n", - (fpga_ver & 0xF000) >> 12, - (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF); - if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) { - printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based " - "devices won't be registered!\n"); - return; - } - - /* register FPGA-based devices */ - qong_init_nand_mtd(); - qong_init_dnet(); -} - -/* - * Board specific initialization. - */ -static void __init qong_init(void) -{ - imx31_soc_init(); - - mxc_init_imx_uart(); - qong_init_nor_mtd(); - qong_init_fpga(); - imx31_add_imx2_wdt(); -} - -static void __init qong_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") - /* Maintainer: DENX Software Engineering GmbH */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .handle_irq = imx31_handle_irq, - .init_time = qong_timer_init, - .init_machine = qong_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c deleted file mode 100644 index b0fa10dd79fe..000000000000 --- a/arch/arm/mach-imx/mach-scb9328.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * linux/arch/arm/mach-mx1/mach-scb9328.c - * - * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> - * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/interrupt.h> -#include <linux/dm9000.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx1.h" -#include "hardware.h" -#include "iomux-mx1.h" - -/* - * This scb9328 has a 32MiB flash - */ -static struct resource flash_resource = { - .start = MX1_CS0_PHYS, - .end = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1, - .flags = IORESOURCE_MEM, -}; - -static struct physmap_flash_data scb_flash_data = { - .width = 2, -}; - -static struct platform_device scb_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &scb_flash_data, - }, - .resource = &flash_resource, - .num_resources = 1, -}; - -/* - * scb9328 has a DM9000 network controller - * connected to CS5, with 16 bit data path - * and interrupt connected to GPIO 3 - */ - -/* - * internal datapath is fixed 16 bit - */ -static struct dm9000_plat_data dm9000_platdata = { - .flags = DM9000_PLATF_16BITONLY, -}; - -/* - * the DM9000 drivers wants two defined address spaces - * to gain access to address latch registers and the data path. - */ -static struct resource dm9000x_resources[] = { - { - .name = "address area", - .start = MX1_CS5_PHYS, - .end = MX1_CS5_PHYS + 1, - .flags = IORESOURCE_MEM, /* address access */ - }, { - .name = "data area", - .start = MX1_CS5_PHYS + 4, - .end = MX1_CS5_PHYS + 5, - .flags = IORESOURCE_MEM, /* data access */ - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct platform_device dm9000x_device = { - .name = "dm9000", - .id = 0, - .num_resources = ARRAY_SIZE(dm9000x_resources), - .resource = dm9000x_resources, - .dev = { - .platform_data = &dm9000_platdata, - } -}; - -static const int mxc_uart1_pins[] = { - PC9_PF_UART1_CTS, - PC10_PF_UART1_RTS, - PC11_PF_UART1_TXD, - PC12_PF_UART1_RXD, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &scb_flash_device, - &dm9000x_device, -}; - -/* - * scb9328_init - Init the CPU card itself - */ -static void __init scb9328_init(void) -{ - imx1_soc_init(); - - mxc_gpio_setup_multiple_pins(mxc_uart1_pins, - ARRAY_SIZE(mxc_uart1_pins), "UART1"); - - imx1_add_imx_uart0(&uart_pdata); - - printk(KERN_INFO"Scb9328: Adding devices\n"); - dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3)); - dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3)); - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -static void __init scb9328_timer_init(void) -{ - mx1_clocks_init(32000); -} - -MACHINE_START(SCB9328, "Synertronixx scb9328") - /* Sascha Hauer */ - .atag_offset = 100, - .map_io = mx1_map_io, - .init_early = imx1_init_early, - .init_irq = mx1_init_irq, - .handle_irq = imx1_handle_irq, - .init_time = scb9328_timer_init, - .init_machine = scb9328_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c index 816991deb9b8..208ff640698d 100644 --- a/arch/arm/mach-imx/mach-vf610.c +++ b/arch/arm/mach-imx/mach-vf610.c @@ -1,48 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2012-2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ +#include <linux/of_address.h> #include <linux/of_platform.h> -#include <linux/clocksource.h> +#include <linux/io.h> + #include <linux/irqchip.h> -#include <linux/clk-provider.h> #include <asm/mach/arch.h> #include <asm/hardware/cache-l2x0.h> #include "common.h" +#include "hardware.h" -static void __init vf610_init_machine(void) -{ - mxc_arch_reset_init_dt(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -} +#define MSCM_CPxCOUNT 0x00c +#define MSCM_CPxCFG1 0x014 -static void __init vf610_init_irq(void) +static void __init vf610_detect_cpu(void) { - l2x0_of_init(0, ~0UL); - irqchip_init(); + struct device_node *np; + u32 cpxcount, cpxcfg1; + unsigned int cpu_type; + void __iomem *mscm; + + np = of_find_compatible_node(NULL, NULL, "fsl,vf610-mscm-cpucfg"); + if (WARN_ON(!np)) + return; + + mscm = of_iomap(np, 0); + of_node_put(np); + + if (WARN_ON(!mscm)) + return; + + cpxcount = readl_relaxed(mscm + MSCM_CPxCOUNT); + cpxcfg1 = readl_relaxed(mscm + MSCM_CPxCFG1); + + iounmap(mscm); + + cpu_type = cpxcount ? MXC_CPU_VF600 : MXC_CPU_VF500; + + if (cpxcfg1) + cpu_type |= MXC_CPU_VFx10; + + mxc_set_cpu_type(cpu_type); } -static void __init vf610_init_time(void) +static void __init vf610_init_machine(void) { - of_clk_init(NULL); - clocksource_of_init(); + vf610_detect_cpu(); + + of_platform_default_populate(NULL, NULL, NULL); } -static const char *vf610_dt_compat[] __initdata = { +static const char * const vf610_dt_compat[] __initconst = { + "fsl,vf500", + "fsl,vf510", + "fsl,vf600", "fsl,vf610", + "fsl,vf610m4", NULL, }; -DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)") - .init_irq = vf610_init_irq, - .init_time = vf610_init_time, +DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF5xx/VF6xx (Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_machine = vf610_init_machine, .dt_compat = vf610_dt_compat, - .restart = mxc_restart, MACHINE_END diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c deleted file mode 100644 index 0910761e8280..000000000000 --- a/arch/arm/mach-imx/mach-vpr200.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix - * Copyright 2010 Creative Product Design - * - * Derived from mx35 3stack. - * Original author: Fabio Estevam <fabio.estevam@freescale.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/memory.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <linux/i2c.h> -#include <linux/i2c/at24.h> -#include <linux/mfd/mc13xxx.h> - -#include "common.h" -#include "devices-imx35.h" -#include "hardware.h" -#include "iomux-mx35.h" - -#define GPIO_LCDPWR IMX_GPIO_NR(1, 2) -#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) - -#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4) -#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5) -#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7) -#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8) -#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9) -#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10) -#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11) -#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12) - -static const struct fb_videomode fb_modedb[] = { - { - /* 800x480 @ 60 Hz */ - .name = "PT0708048", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(33260), - .left_margin = 50, - .right_margin = 156, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 800x480 @ 60 Hz */ - .name = "CTP-CLAA070LC0ACW", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(27000), - .left_margin = 50, - .right_margin = 50, /* whole line should have 900 clocks */ - .upper_margin = 10, - .lower_margin = 10, /* whole frame should have 500 lines */ - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - } -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "PT0708048", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data vpr200_flash_data = { - .width = 2, -}; - -static struct resource vpr200_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device vpr200_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &vpr200_flash_data, - }, - .resource = &vpr200_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data - vpr200_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#define VPR_KEY_DEBOUNCE 500 -static struct gpio_keys_button vpr200_gpio_keys_table[] = { - {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE}, - {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE}, - {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE}, - {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE}, - {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE}, - {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE}, - {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE}, - {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE}, -}; - -static const struct gpio_keys_platform_data - vpr200_gpio_keys_data __initconst = { - .buttons = vpr200_gpio_keys_table, - .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table), -}; - -static struct mc13xxx_platform_data vpr200_pmic = { - .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, -}; - -static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = { - .bitrate = 50000, -}; - -static struct at24_platform_data vpr200_eeprom = { - .byte_len = 2048 / 8, - .page_size = 1, -}; - -static struct i2c_board_info vpr200_i2c_devices[] = { - { - I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */ - .platform_data = &vpr200_eeprom, - }, { - I2C_BOARD_INFO("mc13892", 0x08), - .platform_data = &vpr200_pmic, - /* irq number is run-time assigned */ - } -}; - -static iomux_v3_cfg_t vpr200_pads[] = { - /* UART1 */ - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART3 */ - MX35_PAD_ATA_DATA10__UART3_RXD_MUX, - MX35_PAD_ATA_DATA11__UART3_TXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - /* LCD Enable */ - MX35_PAD_D3_VSYNC__GPIO1_2, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* PMIC */ - MX35_PAD_GPIO2_0__GPIO2_0, - /* GPIO keys */ - MX35_PAD_SCKR__GPIO1_4, - MX35_PAD_COMPARE__GPIO1_5, - MX35_PAD_SCKT__GPIO1_7, - MX35_PAD_FST__GPIO1_8, - MX35_PAD_HCKT__GPIO1_9, - MX35_PAD_TX5_RX0__GPIO1_10, - MX35_PAD_TX4_RX1__GPIO1_11, - MX35_PAD_TX3_RX2__GPIO1_12, -}; - -/* USB Device config */ -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -}; - -static int vpr200_usbh_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, - MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY); -} - -/* USB HOST config */ -static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .init = vpr200_usbh_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static struct platform_device *devices[] __initdata = { - &vpr200_flash, -}; - -/* - * Board specific initialization. - */ -static void __init vpr200_board_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(); - imx_add_gpio_keys(&vpr200_gpio_keys_data); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR")) - printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n"); - else - gpio_direction_output(GPIO_LCDPWR, 0); - - if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT")) - printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n"); - else - gpio_direction_input(GPIO_PMIC_INT); - - imx35_add_imx_uart0(NULL); - imx35_add_imx_uart2(NULL); - - imx35_add_ipu_core(); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - imx35_add_fsl_usb2_udc(&otg_device_pdata); - imx35_add_mxc_ehci_hs(&usb_host_pdata); - - imx35_add_mxc_nand(&vpr200_nand_board_info); - imx35_add_sdhci_esdhc_imx(0, NULL); - - vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT); - i2c_register_board_info(0, vpr200_i2c_devices, - ARRAY_SIZE(vpr200_i2c_devices)); - - imx35_add_imx_i2c0(&vpr200_i2c0_data); -} - -static void __init vpr200_timer_init(void) -{ - mx35_clocks_init(); -} - -MACHINE_START(VPR200, "VPR200") - /* Maintainer: Creative Product Design */ - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .handle_irq = imx35_handle_irq, - .init_time = vpr200_timer_init, - .init_machine = vpr200_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c deleted file mode 100644 index e065fedb3ad4..000000000000 --- a/arch/arm/mach-imx/mm-imx1.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX1 machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/pinctrl/machine.h> - -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v1.h" - -static struct map_desc imx_io_desc[] __initdata = { - imx_map_entry(MX1, IO, MT_DEVICE), -}; - -void __init mx1_map_io(void) -{ - iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); -} - -void __init imx1_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX1); - imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), - MX1_NUM_GPIO_PORT); -} - -void __init mx1_init_irq(void) -{ - mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); -} - -void __init imx1_soc_init(void) -{ - mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); - mxc_device_init(); - - mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTA, 0); - mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTB, 0); - mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTC, 0); - mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256, - MX1_GPIO_INT_PORTD, 0); - imx_add_imx_dma("imx1-dma", MX1_DMA_BASE_ADDR, - MX1_DMA_INT, MX1_DMA_ERR); - pinctrl_provide_dummies(); -} diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c deleted file mode 100644 index 2e91ab2ca378..000000000000 --- a/arch/arm/mach-imx/mm-imx21.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * arch/arm/mach-imx/mm-imx21.c - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/pinctrl/machine.h> -#include <asm/pgtable.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v1.h" - -/* MX21 memory map definition */ -static struct map_desc imx21_io_desc[] __initdata = { - /* - * this fixed mapping covers: - * - AIPI1 - * - AIPI2 - * - AITC - * - ROM Patch - * - and some reserved space - */ - imx_map_entry(MX21, AIPI, MT_DEVICE), - /* - * this fixed mapping covers: - * - CSI - * - ATA - */ - imx_map_entry(MX21, SAHB1, MT_DEVICE), - /* - * this fixed mapping covers: - * - EMI - */ - imx_map_entry(MX21, X_MEMC, MT_DEVICE), -}; - -/* - * Initialize the memory map. It is called during the - * system startup to create static physical to virtual - * memory map for the IO modules. - */ -void __init mx21_map_io(void) -{ - iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); -} - -void __init imx21_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX21); - imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), - MX21_NUM_GPIO_PORT); -} - -void __init mx21_init_irq(void) -{ - mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); -} - -static const struct resource imx21_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K), -}; - -void __init imx21_soc_init(void) -{ - mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); - mxc_device_init(); - - mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - - pinctrl_provide_dummies(); - imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, - MX21_INT_DMACH0, 0); /* No ERR irq */ - platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, - ARRAY_SIZE(imx21_audmux_res)); -} diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c deleted file mode 100644 index e065c117f5a6..000000000000 --- a/arch/arm/mach-imx/mm-imx25.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 1999,2000 Arm Limited - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/pinctrl/machine.h> - -#include <asm/pgtable.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v3.h" -#include "mx25.h" - -/* - * This table defines static virtual address mappings for I/O regions. - * These are the mappings common across all MX25 boards. - */ -static struct map_desc mx25_io_desc[] __initdata = { - imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED), - imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED), - imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx25_map_io(void) -{ - iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc)); -} - -void __init imx25_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX25); - mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); -} - -void __init mx25_init_irq(void) -{ - mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx25_sdma_script __initdata = { - .ap_2_ap_addr = 729, - .uart_2_mcu_addr = 904, - .per_2_app_addr = 1255, - .mcu_2_app_addr = 834, - .uartsh_2_mcu_addr = 1120, - .per_2_shp_addr = 1329, - .mcu_2_shp_addr = 1048, - .ata_2_mcu_addr = 1560, - .mcu_2_ata_addr = 1479, - .app_2_per_addr = 1189, - .app_2_mcu_addr = 770, - .shp_2_per_addr = 1407, - .shp_2_mcu_addr = 979, -}; - -static struct sdma_platform_data imx25_sdma_pdata __initdata = { - .fw_name = "sdma-imx25.bin", - .script_addrs = &imx25_sdma_script, -}; - -static const struct resource imx25_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX25_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx25_soc_init(void) -{ - mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); - mxc_device_init(); - - /* i.mx25 has the i.mx35 type gpio */ - mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0); - mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0); - mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0); - mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0); - - pinctrl_provide_dummies(); - /* i.mx25 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata); - /* i.mx25 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx25_audmux_res, - ARRAY_SIZE(imx25_audmux_res)); -} diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c deleted file mode 100644 index 7d82a5a5b16b..000000000000 --- a/arch/arm/mach-imx/mm-imx27.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * arch/arm/mach-imx/mm-imx27.c - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/pinctrl/machine.h> -#include <asm/pgtable.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v1.h" - -/* MX27 memory map definition */ -static struct map_desc imx27_io_desc[] __initdata = { - /* - * this fixed mapping covers: - * - AIPI1 - * - AIPI2 - * - AITC - * - ROM Patch - * - and some reserved space - */ - imx_map_entry(MX27, AIPI, MT_DEVICE), - /* - * this fixed mapping covers: - * - CSI - * - ATA - */ - imx_map_entry(MX27, SAHB1, MT_DEVICE), - /* - * this fixed mapping covers: - * - EMI - */ - imx_map_entry(MX27, X_MEMC, MT_DEVICE), -}; - -/* - * Initialize the memory map. It is called during the - * system startup to create static physical to virtual - * memory map for the IO modules. - */ -void __init mx27_map_io(void) -{ - iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); -} - -void __init imx27_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX27); - imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), - MX27_NUM_GPIO_PORT); -} - -void __init mx27_init_irq(void) -{ - mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); -} - -static const struct resource imx27_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K), -}; - -void __init imx27_soc_init(void) -{ - mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - mxc_device_init(); - - /* i.mx27 has the i.mx21 type gpio */ - mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - - pinctrl_provide_dummies(); - imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, - MX27_INT_DMACH0, 0); /* No ERR irq */ - /* imx27 has the imx21 type audmux */ - platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, - ARRAY_SIZE(imx27_audmux_res)); -} diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index 0884ca90d15a..0788c5cc7f9e 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -1,36 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 1999,2000 Arm Limited * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright (C) 2002 Shane Nay (shane@minirl.com) * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. * - add MX31 specific definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/mm.h> #include <linux/init.h> #include <linux/err.h> -#include <linux/pinctrl/machine.h> +#include <linux/io.h> +#include <linux/of_address.h> -#include <asm/pgtable.h> #include <asm/system_misc.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> #include "common.h" #include "crmregs-imx3.h" -#include "devices/devices-common.h" #include "hardware.h" -#include "iomux-v3.h" void __iomem *mx3_ccm_base; @@ -38,8 +27,6 @@ static void imx3_idle(void) { unsigned long reg = 0; - mx3_cpu_lp_set(MX3_WAIT); - __asm__ __volatile__( /* disable I and D cache */ "mrc p15, 0, %0, c1, c0, 0\n" @@ -82,40 +69,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size, return __arm_ioremap_caller(phys_addr, size, mtype, caller); } -static void __init imx3_init_l2x0(void) -{ -#ifdef CONFIG_CACHE_L2X0 - void __iomem *l2x0_base; - void __iomem *clkctl_base; - -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value. - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (!l2x0_base) { - printk(KERN_ERR "remapping L2 cache area failed\n"); - return; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); -#endif -} - #ifdef CONFIG_SOC_IMX31 static struct map_desc mx31_io_desc[] __initdata = { imx_map_entry(MX31, X_MEMC, MT_DEVICE), @@ -135,66 +88,25 @@ void __init mx31_map_io(void) iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc)); } -void __init imx31_init_early(void) +static void imx31_idle(void) { - mxc_set_cpu_type(MXC_CPU_MX31); - arch_ioremap_caller = imx3_ioremap_caller; - arm_pm_idle = imx3_idle; - mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); -} + int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_LPM_MASK; + imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); -void __init mx31_init_irq(void) -{ - mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); + imx3_idle(); } -static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { - .per_2_per_addr = 1677, -}; - -static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { - .ap_2_ap_addr = 423, - .ap_2_bp_addr = 829, - .bp_2_ap_addr = 1029, -}; - -static struct sdma_platform_data imx31_sdma_pdata __initdata = { - .fw_name = "sdma-imx31-to2.bin", - .script_addrs = &imx31_to2_sdma_script, -}; - -static const struct resource imx31_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx31_soc_init(void) +void __init imx31_init_early(void) { - int to_version = mx31_revision() >> 4; - - imx3_init_l2x0(); - - mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); - mxc_device_init(); - - mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); - - pinctrl_provide_dummies(); + struct device_node *np; - if (to_version == 1) { - strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", - strlen(imx31_sdma_pdata.fw_name)); - imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; - } - - imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); - - imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); - imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); - - platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, - ARRAY_SIZE(imx31_audmux_res)); + mxc_set_cpu_type(MXC_CPU_MX31); + arch_ioremap_caller = imx3_ioremap_caller; + arm_pm_idle = imx31_idle; + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); + mx3_ccm_base = of_iomap(np, 0); + BUG_ON(!mx3_ccm_base); } #endif /* ifdef CONFIG_SOC_IMX31 */ @@ -212,87 +124,25 @@ void __init mx35_map_io(void) iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc)); } -void __init imx35_init_early(void) +static void imx35_idle(void) { - mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); - arm_pm_idle = imx3_idle; - arch_ioremap_caller = imx3_ioremap_caller; - mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); -} + int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); + reg &= ~MXC_CCM_CCMR_LPM_MASK; + reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; + imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); -void __init mx35_init_irq(void) -{ - mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); + imx3_idle(); } -static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .uart_2_mcu_addr = 817, - .mcu_2_app_addr = 747, - .uartsh_2_mcu_addr = 1183, - .per_2_shp_addr = 1033, - .mcu_2_shp_addr = 961, - .ata_2_mcu_addr = 1333, - .mcu_2_ata_addr = 1252, - .app_2_mcu_addr = 683, - .shp_2_per_addr = 1111, - .shp_2_mcu_addr = 892, -}; - -static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { - .ap_2_ap_addr = 729, - .uart_2_mcu_addr = 904, - .per_2_app_addr = 1597, - .mcu_2_app_addr = 834, - .uartsh_2_mcu_addr = 1270, - .per_2_shp_addr = 1120, - .mcu_2_shp_addr = 1048, - .ata_2_mcu_addr = 1429, - .mcu_2_ata_addr = 1339, - .app_2_per_addr = 1531, - .app_2_mcu_addr = 770, - .shp_2_per_addr = 1198, - .shp_2_mcu_addr = 979, -}; - -static struct sdma_platform_data imx35_sdma_pdata __initdata = { - .fw_name = "sdma-imx35-to2.bin", - .script_addrs = &imx35_to2_sdma_script, -}; - -static const struct resource imx35_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx35_soc_init(void) +void __init imx35_init_early(void) { - int to_version = mx35_revision() >> 4; - - imx3_init_l2x0(); - - mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); - mxc_device_init(); + struct device_node *np; - mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); - mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); - mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); - - pinctrl_provide_dummies(); - if (to_version == 1) { - strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", - strlen(imx35_sdma_pdata.fw_name)); - imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; - } - - imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); - imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); - - /* i.mx35 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, - ARRAY_SIZE(imx35_audmux_res)); + mxc_set_cpu_type(MXC_CPU_MX35); + arm_pm_idle = imx35_idle; + arch_ioremap_caller = imx3_ioremap_caller; + np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm"); + mx3_ccm_base = of_iomap(np, 0); + BUG_ON(!mx3_ccm_base); } #endif /* ifdef CONFIG_SOC_IMX35 */ diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c deleted file mode 100644 index cf193d87274a..000000000000 --- a/arch/arm/mach-imx/mm-imx5.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - * - * Create static mapping between physical to virtual memory. - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/pinctrl/machine.h> - -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v3.h" - -/* - * Define the MX51 memory map. - */ -static struct map_desc mx51_io_desc[] __initdata = { - imx_map_entry(MX51, TZIC, MT_DEVICE), - imx_map_entry(MX51, IRAM, MT_DEVICE), - imx_map_entry(MX51, AIPS1, MT_DEVICE), - imx_map_entry(MX51, SPBA0, MT_DEVICE), - imx_map_entry(MX51, AIPS2, MT_DEVICE), -}; - -/* - * Define the MX53 memory map. - */ -static struct map_desc mx53_io_desc[] __initdata = { - imx_map_entry(MX53, TZIC, MT_DEVICE), - imx_map_entry(MX53, AIPS1, MT_DEVICE), - imx_map_entry(MX53, SPBA0, MT_DEVICE), - imx_map_entry(MX53, AIPS2, MT_DEVICE), -}; - -/* - * This function initializes the memory map. It is called during the - * system startup to create static physical to virtual memory mappings - * for the IO modules. - */ -void __init mx51_map_io(void) -{ - iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); -} - -void __init mx53_map_io(void) -{ - iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); -} - -/* - * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by - * the Freescale marketing division. However this did not remove the - * hardware from the chip which still needs to be configured for proper - * IPU support. - */ -static void __init imx51_ipu_mipi_setup(void) -{ - void __iomem *hsc_addr; - hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR); - - /* setup MIPI module to legacy mode */ - __raw_writel(0xf00, hsc_addr); - - /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ - __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, - hsc_addr + 0x800); -} - -void __init imx51_init_early(void) -{ - imx51_ipu_mipi_setup(); - mxc_set_cpu_type(MXC_CPU_MX51); - mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); - imx_src_init(); -} - -void __init imx53_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX53); - mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); - imx_src_init(); -} - -void __init mx51_init_irq(void) -{ - tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); -} - -void __init mx53_init_irq(void) -{ - tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx51_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .uart_2_mcu_addr = 817, - .mcu_2_app_addr = 747, - .mcu_2_shp_addr = 961, - .ata_2_mcu_addr = 1473, - .mcu_2_ata_addr = 1392, - .app_2_per_addr = 1033, - .app_2_mcu_addr = 683, - .shp_2_per_addr = 1251, - .shp_2_mcu_addr = 892, -}; - -static struct sdma_platform_data imx51_sdma_pdata __initdata = { - .fw_name = "sdma-imx51.bin", - .script_addrs = &imx51_sdma_script, -}; - -static const struct resource imx51_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx51_soc_init(void) -{ - mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); - mxc_device_init(); - - /* i.mx51 has the i.mx35 type gpio */ - mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH); - mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH); - mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH); - mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH); - - pinctrl_provide_dummies(); - - /* i.mx51 has the i.mx35 type sdma */ - imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata); - - /* Setup AIPS registers */ - imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR)); - imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); - - /* i.mx51 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res, - ARRAY_SIZE(imx51_audmux_res)); -} - -void __init imx51_init_late(void) -{ - mx51_neon_fixup(); - imx51_pm_init(); -} - -void __init imx53_init_late(void) -{ - imx53_pm_init(); -} diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 7a9686ad994c..94e4f4a2f73f 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -1,36 +1,573 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright 2011,2016 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ +#include <linux/clk.h> +#include <linux/hrtimer.h> #include <linux/init.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/perf_event.h> +#include <linux/slab.h> + +#include "common.h" #define MMDC_MAPSR 0x404 #define BP_MMDC_MAPSR_PSD 0 #define BP_MMDC_MAPSR_PSS 4 +#define MMDC_MDMISC 0x18 +#define BM_MMDC_MDMISC_DDR_TYPE 0x18 +#define BP_MMDC_MDMISC_DDR_TYPE 0x3 + +#define TOTAL_CYCLES 0x0 +#define BUSY_CYCLES 0x1 +#define READ_ACCESSES 0x2 +#define WRITE_ACCESSES 0x3 +#define READ_BYTES 0x4 +#define WRITE_BYTES 0x5 + +/* Enables, resets, freezes, overflow profiling*/ +#define DBG_DIS 0x0 +#define DBG_EN 0x1 +#define DBG_RST 0x2 +#define PRF_FRZ 0x4 +#define CYC_OVF 0x8 +#define PROFILE_SEL 0x10 + +#define MMDC_MADPCR0 0x410 +#define MMDC_MADPCR1 0x414 +#define MMDC_MADPSR0 0x418 +#define MMDC_MADPSR1 0x41C +#define MMDC_MADPSR2 0x420 +#define MMDC_MADPSR3 0x424 +#define MMDC_MADPSR4 0x428 +#define MMDC_MADPSR5 0x42C + +#define MMDC_NUM_COUNTERS 6 + +#define MMDC_FLAG_PROFILE_SEL 0x1 +#define MMDC_PRF_AXI_ID_CLEAR 0x0 + +#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu) + +static int ddr_type; + +struct fsl_mmdc_devtype_data { + unsigned int flags; +}; + +static const struct fsl_mmdc_devtype_data imx6q_data = { +}; + +static const struct fsl_mmdc_devtype_data imx6qp_data = { + .flags = MMDC_FLAG_PROFILE_SEL, +}; + +static const struct of_device_id imx_mmdc_dt_ids[] = { + { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data}, + { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data}, + { /* sentinel */ } +}; + +#ifdef CONFIG_PERF_EVENTS + +static enum cpuhp_state cpuhp_mmdc_state; +static DEFINE_IDA(mmdc_ida); + +PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00") +PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01") +PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02") +PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03") +PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04") +PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001"); +PMU_EVENT_ATTR_STRING(write-bytes, mmdc_pmu_write_bytes, "event=0x05") +PMU_EVENT_ATTR_STRING(write-bytes.unit, mmdc_pmu_write_bytes_unit, "MB"); +PMU_EVENT_ATTR_STRING(write-bytes.scale, mmdc_pmu_write_bytes_scale, "0.000001"); + +struct mmdc_pmu { + struct pmu pmu; + void __iomem *mmdc_base; + cpumask_t cpu; + struct hrtimer hrtimer; + unsigned int active_events; + int id; + struct device *dev; + struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; + struct hlist_node node; + const struct fsl_mmdc_devtype_data *devtype_data; + struct clk *mmdc_ipg_clk; +}; + +/* + * Polling period is set to one second, overflow of total-cycles (the fastest + * increasing counter) takes ten seconds so one second is safe + */ +static unsigned int mmdc_pmu_poll_period_us = 1000000; + +module_param_named(pmu_pmu_poll_period_us, mmdc_pmu_poll_period_us, uint, + S_IRUGO | S_IWUSR); + +static ktime_t mmdc_pmu_timer_period(void) +{ + return ns_to_ktime((u64)mmdc_pmu_poll_period_us * 1000); +} + +static ssize_t mmdc_pmu_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mmdc_pmu *pmu_mmdc = dev_get_drvdata(dev); + + return cpumap_print_to_pagebuf(true, buf, &pmu_mmdc->cpu); +} + +static struct device_attribute mmdc_pmu_cpumask_attr = + __ATTR(cpumask, S_IRUGO, mmdc_pmu_cpumask_show, NULL); + +static struct attribute *mmdc_pmu_cpumask_attrs[] = { + &mmdc_pmu_cpumask_attr.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_cpumask_attr_group = { + .attrs = mmdc_pmu_cpumask_attrs, +}; + +static struct attribute *mmdc_pmu_events_attrs[] = { + &mmdc_pmu_total_cycles.attr.attr, + &mmdc_pmu_busy_cycles.attr.attr, + &mmdc_pmu_read_accesses.attr.attr, + &mmdc_pmu_write_accesses.attr.attr, + &mmdc_pmu_read_bytes.attr.attr, + &mmdc_pmu_read_bytes_unit.attr.attr, + &mmdc_pmu_read_bytes_scale.attr.attr, + &mmdc_pmu_write_bytes.attr.attr, + &mmdc_pmu_write_bytes_unit.attr.attr, + &mmdc_pmu_write_bytes_scale.attr.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_events_attr_group = { + .name = "events", + .attrs = mmdc_pmu_events_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-63"); +PMU_FORMAT_ATTR(axi_id, "config1:0-63"); + +static struct attribute *mmdc_pmu_format_attrs[] = { + &format_attr_event.attr, + &format_attr_axi_id.attr, + NULL, +}; + +static struct attribute_group mmdc_pmu_format_attr_group = { + .name = "format", + .attrs = mmdc_pmu_format_attrs, +}; + +static const struct attribute_group *attr_groups[] = { + &mmdc_pmu_events_attr_group, + &mmdc_pmu_format_attr_group, + &mmdc_pmu_cpumask_attr_group, + NULL, +}; + +static u32 mmdc_pmu_read_counter(struct mmdc_pmu *pmu_mmdc, int cfg) +{ + void __iomem *mmdc_base, *reg; + + mmdc_base = pmu_mmdc->mmdc_base; + + switch (cfg) { + case TOTAL_CYCLES: + reg = mmdc_base + MMDC_MADPSR0; + break; + case BUSY_CYCLES: + reg = mmdc_base + MMDC_MADPSR1; + break; + case READ_ACCESSES: + reg = mmdc_base + MMDC_MADPSR2; + break; + case WRITE_ACCESSES: + reg = mmdc_base + MMDC_MADPSR3; + break; + case READ_BYTES: + reg = mmdc_base + MMDC_MADPSR4; + break; + case WRITE_BYTES: + reg = mmdc_base + MMDC_MADPSR5; + break; + default: + return WARN_ONCE(1, + "invalid configuration %d for mmdc counter", cfg); + } + return readl(reg); +} + +static int mmdc_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct mmdc_pmu *pmu_mmdc = hlist_entry_safe(node, struct mmdc_pmu, node); + int target; + + if (!cpumask_test_and_clear_cpu(cpu, &pmu_mmdc->cpu)) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&pmu_mmdc->pmu, cpu, target); + cpumask_set_cpu(target, &pmu_mmdc->cpu); + + return 0; +} + +static bool mmdc_pmu_group_event_is_valid(struct perf_event *event, + struct pmu *pmu, + unsigned long *used_counters) +{ + int cfg = event->attr.config; + + if (is_software_event(event)) + return true; + + if (event->pmu != pmu) + return false; + + return !test_and_set_bit(cfg, used_counters); +} + +/* + * Each event has a single fixed-purpose counter, so we can only have a + * single active event for each at any point in time. Here we just check + * for duplicates, and rely on mmdc_pmu_event_init to verify that the HW + * event numbers are valid. + */ +static bool mmdc_pmu_group_is_valid(struct perf_event *event) +{ + struct pmu *pmu = event->pmu; + struct perf_event *leader = event->group_leader; + struct perf_event *sibling; + unsigned long counter_mask = 0; + + set_bit(leader->attr.config, &counter_mask); + + if (event != leader) { + if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask)) + return false; + } + + for_each_sibling_event(sibling, leader) { + if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) + return false; + } + + return true; +} + +static int mmdc_pmu_event_init(struct perf_event *event) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + int cfg = event->attr.config; + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EOPNOTSUPP; + + if (event->cpu < 0) { + dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n"); + return -EOPNOTSUPP; + } + + if (event->attr.sample_period) + return -EINVAL; + + if (cfg < 0 || cfg >= MMDC_NUM_COUNTERS) + return -EINVAL; + + if (!mmdc_pmu_group_is_valid(event)) + return -EINVAL; + + event->cpu = cpumask_first(&pmu_mmdc->cpu); + return 0; +} + +static void mmdc_pmu_event_update(struct perf_event *event) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 delta, prev_raw_count, new_raw_count; + + do { + prev_raw_count = local64_read(&hwc->prev_count); + new_raw_count = mmdc_pmu_read_counter(pmu_mmdc, + event->attr.config); + } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, + new_raw_count) != prev_raw_count); + + delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF; + + local64_add(delta, &event->count); +} + +static void mmdc_pmu_event_start(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + void __iomem *mmdc_base, *reg; + u32 val; + + mmdc_base = pmu_mmdc->mmdc_base; + reg = mmdc_base + MMDC_MADPCR0; + + /* + * hrtimer is required because mmdc does not provide an interrupt so + * polling is necessary + */ + hrtimer_start(&pmu_mmdc->hrtimer, mmdc_pmu_timer_period(), + HRTIMER_MODE_REL_PINNED); + + local64_set(&hwc->prev_count, 0); + + writel(DBG_RST, reg); + + /* + * Write the AXI id parameter to MADPCR1. + */ + val = event->attr.config1; + reg = mmdc_base + MMDC_MADPCR1; + writel(val, reg); + + reg = mmdc_base + MMDC_MADPCR0; + val = DBG_EN; + if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL) + val |= PROFILE_SEL; + + writel(val, reg); +} + +static int mmdc_pmu_event_add(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + struct hw_perf_event *hwc = &event->hw; + + int cfg = event->attr.config; + + if (flags & PERF_EF_START) + mmdc_pmu_event_start(event, flags); + + if (pmu_mmdc->mmdc_events[cfg] != NULL) + return -EAGAIN; + + pmu_mmdc->mmdc_events[cfg] = event; + pmu_mmdc->active_events++; + + local64_set(&hwc->prev_count, mmdc_pmu_read_counter(pmu_mmdc, cfg)); + + return 0; +} + +static void mmdc_pmu_event_stop(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + void __iomem *mmdc_base, *reg; + + mmdc_base = pmu_mmdc->mmdc_base; + reg = mmdc_base + MMDC_MADPCR0; + + writel(PRF_FRZ, reg); + + reg = mmdc_base + MMDC_MADPCR1; + writel(MMDC_PRF_AXI_ID_CLEAR, reg); + + mmdc_pmu_event_update(event); +} + +static void mmdc_pmu_event_del(struct perf_event *event, int flags) +{ + struct mmdc_pmu *pmu_mmdc = to_mmdc_pmu(event->pmu); + int cfg = event->attr.config; + + pmu_mmdc->mmdc_events[cfg] = NULL; + pmu_mmdc->active_events--; + + if (pmu_mmdc->active_events == 0) + hrtimer_cancel(&pmu_mmdc->hrtimer); + + mmdc_pmu_event_stop(event, PERF_EF_UPDATE); +} + +static void mmdc_pmu_overflow_handler(struct mmdc_pmu *pmu_mmdc) +{ + int i; + + for (i = 0; i < MMDC_NUM_COUNTERS; i++) { + struct perf_event *event = pmu_mmdc->mmdc_events[i]; + + if (event) + mmdc_pmu_event_update(event); + } +} + +static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) +{ + struct mmdc_pmu *pmu_mmdc = container_of(hrtimer, struct mmdc_pmu, + hrtimer); + + mmdc_pmu_overflow_handler(pmu_mmdc); + hrtimer_forward_now(hrtimer, mmdc_pmu_timer_period()); + + return HRTIMER_RESTART; +} + +static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, + void __iomem *mmdc_base, struct device *dev) +{ + *pmu_mmdc = (struct mmdc_pmu) { + .pmu = (struct pmu) { + .parent = dev, + .task_ctx_nr = perf_invalid_context, + .attr_groups = attr_groups, + .event_init = mmdc_pmu_event_init, + .add = mmdc_pmu_event_add, + .del = mmdc_pmu_event_del, + .start = mmdc_pmu_event_start, + .stop = mmdc_pmu_event_stop, + .read = mmdc_pmu_event_update, + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, + }, + .mmdc_base = mmdc_base, + .dev = dev, + .active_events = 0, + }; + + pmu_mmdc->id = ida_alloc(&mmdc_ida, GFP_KERNEL); + + return pmu_mmdc->id; +} + +static void imx_mmdc_remove(struct platform_device *pdev) +{ + struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); + + ida_free(&mmdc_ida, pmu_mmdc->id); + cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + perf_pmu_unregister(&pmu_mmdc->pmu); + iounmap(pmu_mmdc->mmdc_base); + clk_disable_unprepare(pmu_mmdc->mmdc_ipg_clk); + kfree(pmu_mmdc); +} + +static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_base, + struct clk *mmdc_ipg_clk) +{ + struct mmdc_pmu *pmu_mmdc; + char *name; + int ret; + + pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL); + if (!pmu_mmdc) { + pr_err("failed to allocate PMU device!\n"); + return -ENOMEM; + } + + /* The first instance registers the hotplug state */ + if (!cpuhp_mmdc_state) { + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/arm/mmdc:online", NULL, + mmdc_pmu_offline_cpu); + if (ret < 0) { + pr_err("cpuhp_setup_state_multi failed\n"); + goto pmu_free; + } + cpuhp_mmdc_state = ret; + } + + ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); + if (ret < 0) + goto pmu_free; + + name = devm_kasprintf(&pdev->dev, + GFP_KERNEL, "mmdc%d", ret); + if (!name) { + ret = -ENOMEM; + goto pmu_release_id; + } + + pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; + pmu_mmdc->devtype_data = device_get_match_data(&pdev->dev); + + hrtimer_setup(&pmu_mmdc->hrtimer, mmdc_pmu_timer_handler, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + + cpumask_set_cpu(raw_smp_processor_id(), &pmu_mmdc->cpu); + + /* Register the pmu instance for cpu hotplug */ + cpuhp_state_add_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + + ret = perf_pmu_register(&(pmu_mmdc->pmu), name, -1); + if (ret) + goto pmu_register_err; + + platform_set_drvdata(pdev, pmu_mmdc); + return 0; + +pmu_register_err: + pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); + cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); + hrtimer_cancel(&pmu_mmdc->hrtimer); +pmu_release_id: + ida_free(&mmdc_ida, pmu_mmdc->id); +pmu_free: + kfree(pmu_mmdc); + return ret; +} + +#else +#define imx_mmdc_remove NULL +#define imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk) 0 +#endif + static int imx_mmdc_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; void __iomem *mmdc_base, *reg; + struct clk *mmdc_ipg_clk; u32 val; - int timeout = 0x400; + int err; + + /* the ipg clock is optional */ + mmdc_ipg_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(mmdc_ipg_clk)) + mmdc_ipg_clk = NULL; + + err = clk_prepare_enable(mmdc_ipg_clk); + if (err) { + dev_err(&pdev->dev, "Unable to enable mmdc ipg clock.\n"); + return err; + } mmdc_base = of_iomap(np, 0); WARN_ON(!mmdc_base); + reg = mmdc_base + MMDC_MDMISC; + /* Get ddr type */ + val = readl_relaxed(reg); + ddr_type = (val & BM_MMDC_MDMISC_DDR_TYPE) >> + BP_MMDC_MDMISC_DDR_TYPE; + reg = mmdc_base + MMDC_MAPSR; /* Enable automatic power saving */ @@ -38,31 +575,27 @@ static int imx_mmdc_probe(struct platform_device *pdev) val &= ~(1 << BP_MMDC_MAPSR_PSD); writel_relaxed(val, reg); - /* Ensure it's successfully enabled */ - while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout) - cpu_relax(); - - if (unlikely(!timeout)) { - pr_warn("%s: failed to enable automatic power saving\n", - __func__); - return -EBUSY; + err = imx_mmdc_perf_init(pdev, mmdc_base, mmdc_ipg_clk); + if (err) { + iounmap(mmdc_base); + clk_disable_unprepare(mmdc_ipg_clk); } - return 0; + return err; } -static struct of_device_id imx_mmdc_dt_ids[] = { - { .compatible = "fsl,imx6q-mmdc", }, - { /* sentinel */ } -}; +int imx_mmdc_get_ddr_type(void) +{ + return ddr_type; +} static struct platform_driver imx_mmdc_driver = { .driver = { .name = "imx-mmdc", - .owner = THIS_MODULE, .of_match_table = imx_mmdc_dt_ids, }, .probe = imx_mmdc_probe, + .remove = imx_mmdc_remove, }; static int __init imx_mmdc_init(void) diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c deleted file mode 100644 index fb38436ca67f..000000000000 --- a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Exported ksyms of ARCH_MX1 - * - * Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/module.h> - -#include <linux/platform_data/camera-mx1.h> - -/* IMX camera FIQ handler */ -EXPORT_SYMBOL(mx1_camera_sof_fiq_start); -EXPORT_SYMBOL(mx1_camera_sof_fiq_end); diff --git a/arch/arm/mach-imx/mx1-camera-fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S deleted file mode 100644 index 9c69aa65bf17..000000000000 --- a/arch/arm/mach-imx/mx1-camera-fiq.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * Based on linux/arch/arm/lib/floppydma.S - * Copyright (C) 1995, 1996 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <linux/linkage.h> -#include <asm/assembler.h> - - .text - .global mx1_camera_sof_fiq_end - .global mx1_camera_sof_fiq_start -mx1_camera_sof_fiq_start: - @ enable dma - ldr r12, [r9] - orr r12, r12, #0x00000001 - str r12, [r9] - @ unmask DMA interrupt - ldr r12, [r8] - bic r12, r12, r13 - str r12, [r8] - @ disable SOF interrupt - ldr r12, [r10] - bic r12, r12, #0x00010000 - str r12, [r10] - @ clear SOF flag - mov r12, #0x00010000 - str r12, [r11] - @ return from FIQ - subs pc, lr, #4 -mx1_camera_sof_fiq_end: diff --git a/arch/arm/mach-imx/mx1.h b/arch/arm/mach-imx/mx1.h deleted file mode 100644 index 45bd31cc34d6..000000000000 --- a/arch/arm/mach-imx/mx1.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (C) 1997,1998 Russell King - * Copyright (C) 1999 ARM Limited - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MACH_MX1_H__ -#define __MACH_MX1_H__ - -/* - * Memory map - */ -#define MX1_IO_BASE_ADDR 0x00200000 -#define MX1_IO_SIZE SZ_1M - -#define MX1_CS0_PHYS 0x10000000 -#define MX1_CS0_SIZE 0x02000000 - -#define MX1_CS1_PHYS 0x12000000 -#define MX1_CS1_SIZE 0x01000000 - -#define MX1_CS2_PHYS 0x13000000 -#define MX1_CS2_SIZE 0x01000000 - -#define MX1_CS3_PHYS 0x14000000 -#define MX1_CS3_SIZE 0x01000000 - -#define MX1_CS4_PHYS 0x15000000 -#define MX1_CS4_SIZE 0x01000000 - -#define MX1_CS5_PHYS 0x16000000 -#define MX1_CS5_SIZE 0x01000000 - -/* - * Register BASEs, based on OFFSETs - */ -#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) -#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) -#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) -#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) -#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) -#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) -#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) -#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) -#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) -#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) -#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) -#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) -#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) -#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) -#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) -#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) -#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) -#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) -#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) -#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) -#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) -#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) -#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) -#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) -#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) -#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR) -#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR) -#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR) -#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) -#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) -#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) -#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) -#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) - -/* macro to get at IO space when running virtually */ -#define MX1_IO_P2V(x) IMX_IO_P2V(x) -#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x)) - -/* fixed interrput numbers */ -#include <asm/irq.h> -#define MX1_INT_SOFTINT (NR_IRQS_LEGACY + 0) -#define MX1_INT_CSI (NR_IRQS_LEGACY + 6) -#define MX1_DSPA_MAC_INT (NR_IRQS_LEGACY + 7) -#define MX1_DSPA_INT (NR_IRQS_LEGACY + 8) -#define MX1_COMP_INT (NR_IRQS_LEGACY + 9) -#define MX1_MSHC_XINT (NR_IRQS_LEGACY + 10) -#define MX1_GPIO_INT_PORTA (NR_IRQS_LEGACY + 11) -#define MX1_GPIO_INT_PORTB (NR_IRQS_LEGACY + 12) -#define MX1_GPIO_INT_PORTC (NR_IRQS_LEGACY + 13) -#define MX1_INT_LCDC (NR_IRQS_LEGACY + 14) -#define MX1_SIM_INT (NR_IRQS_LEGACY + 15) -#define MX1_SIM_DATA_INT (NR_IRQS_LEGACY + 16) -#define MX1_RTC_INT (NR_IRQS_LEGACY + 17) -#define MX1_RTC_SAMINT (NR_IRQS_LEGACY + 18) -#define MX1_INT_UART2PFERR (NR_IRQS_LEGACY + 19) -#define MX1_INT_UART2RTS (NR_IRQS_LEGACY + 20) -#define MX1_INT_UART2DTR (NR_IRQS_LEGACY + 21) -#define MX1_INT_UART2UARTC (NR_IRQS_LEGACY + 22) -#define MX1_INT_UART2TX (NR_IRQS_LEGACY + 23) -#define MX1_INT_UART2RX (NR_IRQS_LEGACY + 24) -#define MX1_INT_UART1PFERR (NR_IRQS_LEGACY + 25) -#define MX1_INT_UART1RTS (NR_IRQS_LEGACY + 26) -#define MX1_INT_UART1DTR (NR_IRQS_LEGACY + 27) -#define MX1_INT_UART1UARTC (NR_IRQS_LEGACY + 28) -#define MX1_INT_UART1TX (NR_IRQS_LEGACY + 29) -#define MX1_INT_UART1RX (NR_IRQS_LEGACY + 30) -#define MX1_VOICE_DAC_INT (NR_IRQS_LEGACY + 31) -#define MX1_VOICE_ADC_INT (NR_IRQS_LEGACY + 32) -#define MX1_PEN_DATA_INT (NR_IRQS_LEGACY + 33) -#define MX1_PWM_INT (NR_IRQS_LEGACY + 34) -#define MX1_SDHC_INT (NR_IRQS_LEGACY + 35) -#define MX1_INT_I2C (NR_IRQS_LEGACY + 39) -#define MX1_INT_CSPI2 (NR_IRQS_LEGACY + 40) -#define MX1_INT_CSPI1 (NR_IRQS_LEGACY + 41) -#define MX1_SSI_TX_INT (NR_IRQS_LEGACY + 42) -#define MX1_SSI_TX_ERR_INT (NR_IRQS_LEGACY + 43) -#define MX1_SSI_RX_INT (NR_IRQS_LEGACY + 44) -#define MX1_SSI_RX_ERR_INT (NR_IRQS_LEGACY + 45) -#define MX1_TOUCH_INT (NR_IRQS_LEGACY + 46) -#define MX1_INT_USBD0 (NR_IRQS_LEGACY + 47) -#define MX1_INT_USBD1 (NR_IRQS_LEGACY + 48) -#define MX1_INT_USBD2 (NR_IRQS_LEGACY + 49) -#define MX1_INT_USBD3 (NR_IRQS_LEGACY + 50) -#define MX1_INT_USBD4 (NR_IRQS_LEGACY + 51) -#define MX1_INT_USBD5 (NR_IRQS_LEGACY + 52) -#define MX1_INT_USBD6 (NR_IRQS_LEGACY + 53) -#define MX1_BTSYS_INT (NR_IRQS_LEGACY + 55) -#define MX1_BTTIM_INT (NR_IRQS_LEGACY + 56) -#define MX1_BTWUI_INT (NR_IRQS_LEGACY + 57) -#define MX1_TIM2_INT (NR_IRQS_LEGACY + 58) -#define MX1_TIM1_INT (NR_IRQS_LEGACY + 59) -#define MX1_DMA_ERR (NR_IRQS_LEGACY + 60) -#define MX1_DMA_INT (NR_IRQS_LEGACY + 61) -#define MX1_GPIO_INT_PORTD (NR_IRQS_LEGACY + 62) -#define MX1_WDT_INT (NR_IRQS_LEGACY + 63) - -/* DMA */ -#define MX1_DMA_REQ_UART3_T 2 -#define MX1_DMA_REQ_UART3_R 3 -#define MX1_DMA_REQ_SSI2_T 4 -#define MX1_DMA_REQ_SSI2_R 5 -#define MX1_DMA_REQ_CSI_STAT 6 -#define MX1_DMA_REQ_CSI_R 7 -#define MX1_DMA_REQ_MSHC 8 -#define MX1_DMA_REQ_DSPA_DCT_DOUT 9 -#define MX1_DMA_REQ_DSPA_DCT_DIN 10 -#define MX1_DMA_REQ_DSPA_MAC 11 -#define MX1_DMA_REQ_EXT 12 -#define MX1_DMA_REQ_SDHC 13 -#define MX1_DMA_REQ_SPI1_R 14 -#define MX1_DMA_REQ_SPI1_T 15 -#define MX1_DMA_REQ_SSI_T 16 -#define MX1_DMA_REQ_SSI_R 17 -#define MX1_DMA_REQ_ASP_DAC 18 -#define MX1_DMA_REQ_ASP_ADC 19 -#define MX1_DMA_REQ_USP_EP(x) (20 + (x)) -#define MX1_DMA_REQ_SPI2_R 26 -#define MX1_DMA_REQ_SPI2_T 27 -#define MX1_DMA_REQ_UART2_T 28 -#define MX1_DMA_REQ_UART2_R 29 -#define MX1_DMA_REQ_UART1_T 30 -#define MX1_DMA_REQ_UART1_R 31 - -/* - * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS - * to not break drivers/usb/gadget/imx_udc. Should go - * away after this driver uses the new name. - */ -#define USBD_INT0 MX1_INT_USBD0 - -#endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/mach-imx/mx21.h b/arch/arm/mach-imx/mx21.h deleted file mode 100644 index 468738aa997f..000000000000 --- a/arch/arm/mach-imx/mx21.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de - * - * This contains i.MX21-specific hardware definitions. For those - * hardware pieces that are common between i.MX21 and i.MX27, have a - * look at mx2x.h. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_MX21_H__ -#define __MACH_MX21_H__ - -#define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_SIZE SZ_1M -#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) -#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) -#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) -#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) -#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) -#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) -#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) -#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) -#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) -#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) -#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) -#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) -#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) -#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) -#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) -#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) -#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) -#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) -#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) -#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) -#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) -#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) -#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) -#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) -#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) -#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) -#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) -#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) -#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) -#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) -#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) -#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) -#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) -#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) -#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) -#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) -#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) -#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) - -#define MX21_AVIC_BASE_ADDR 0x10040000 - -#define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_SIZE SZ_1M -#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) - -/* Memory regions and CS */ -#define MX21_SDRAM_BASE_ADDR 0xc0000000 -#define MX21_CSD1_BASE_ADDR 0xc4000000 - -#define MX21_CS0_BASE_ADDR 0xc8000000 -#define MX21_CS1_BASE_ADDR 0xcc000000 -#define MX21_CS2_BASE_ADDR 0xd0000000 -#define MX21_CS3_BASE_ADDR 0xd1000000 -#define MX21_CS4_BASE_ADDR 0xd2000000 -#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 -#define MX21_CS5_BASE_ADDR 0xdd000000 - -/* NAND, SDRAM, WEIM etc controllers */ -#define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_SIZE SZ_256K - -#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) -#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) -#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) -#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) - -#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ - -#define MX21_IO_P2V(x) IMX_IO_P2V(x) -#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) -#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX21_INT_I2C (NR_IRQS_LEGACY + 12) -#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX21_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX21_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX21_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX21_INT_NFC (NR_IRQS_LEGACY + 29) -#define MX21_INT_BMI (NR_IRQS_LEGACY + 30) -#define MX21_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) -#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) -#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) -#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) -#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) -#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) -#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) -#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) -#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) - -/* fixed DMA request numbers */ -#define MX21_DMA_REQ_CSPI3_RX 1 -#define MX21_DMA_REQ_CSPI3_TX 2 -#define MX21_DMA_REQ_EXT 3 -#define MX21_DMA_REQ_FIRI_RX 4 -#define MX21_DMA_REQ_SDHC2 6 -#define MX21_DMA_REQ_SDHC1 7 -#define MX21_DMA_REQ_SSI2_RX0 8 -#define MX21_DMA_REQ_SSI2_TX0 9 -#define MX21_DMA_REQ_SSI2_RX1 10 -#define MX21_DMA_REQ_SSI2_TX1 11 -#define MX21_DMA_REQ_SSI1_RX0 12 -#define MX21_DMA_REQ_SSI1_TX0 13 -#define MX21_DMA_REQ_SSI1_RX1 14 -#define MX21_DMA_REQ_SSI1_TX1 15 -#define MX21_DMA_REQ_CSPI2_RX 16 -#define MX21_DMA_REQ_CSPI2_TX 17 -#define MX21_DMA_REQ_CSPI1_RX 18 -#define MX21_DMA_REQ_CSPI1_TX 19 -#define MX21_DMA_REQ_UART4_RX 20 -#define MX21_DMA_REQ_UART4_TX 21 -#define MX21_DMA_REQ_UART3_RX 22 -#define MX21_DMA_REQ_UART3_TX 23 -#define MX21_DMA_REQ_UART2_RX 24 -#define MX21_DMA_REQ_UART2_TX 25 -#define MX21_DMA_REQ_UART1_RX 26 -#define MX21_DMA_REQ_UART1_TX 27 -#define MX21_DMA_REQ_BMI_TX 28 -#define MX21_DMA_REQ_BMI_RX 29 -#define MX21_DMA_REQ_CSI_STAT 30 -#define MX21_DMA_REQ_CSI_RX 31 - -#endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/mach-imx/mx25.h b/arch/arm/mach-imx/mx25.h deleted file mode 100644 index ec466400a200..000000000000 --- a/arch/arm/mach-imx/mx25.h +++ /dev/null @@ -1,117 +0,0 @@ -#ifndef __MACH_MX25_H__ -#define __MACH_MX25_H__ - -#define MX25_AIPS1_BASE_ADDR 0x43f00000 -#define MX25_AIPS1_SIZE SZ_1M -#define MX25_AIPS2_BASE_ADDR 0x53f00000 -#define MX25_AIPS2_SIZE SZ_1M -#define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_SIZE SZ_1M - -#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) -#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) -#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) -#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) -#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) -#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) -#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) - -#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) -#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) -#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) -#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) -#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) -#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) -#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) -#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) -#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) -#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) -#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) - -#define MX25_UART1_BASE_ADDR 0x43f90000 -#define MX25_UART2_BASE_ADDR 0x43f94000 -#define MX25_AUDMUX_BASE_ADDR 0x43fb0000 -#define MX25_UART3_BASE_ADDR 0x5000c000 -#define MX25_UART4_BASE_ADDR 0x50008000 -#define MX25_UART5_BASE_ADDR 0x5002c000 - -#define MX25_CSPI3_BASE_ADDR 0x50004000 -#define MX25_CSPI2_BASE_ADDR 0x50010000 -#define MX25_FEC_BASE_ADDR 0x50038000 -#define MX25_SSI2_BASE_ADDR 0x50014000 -#define MX25_SSI1_BASE_ADDR 0x50034000 -#define MX25_NFC_BASE_ADDR 0xbb000000 -#define MX25_IIM_BASE_ADDR 0x53ff0000 -#define MX25_DRYICE_BASE_ADDR 0x53ffc000 -#define MX25_ESDHC1_BASE_ADDR 0x53fb4000 -#define MX25_ESDHC2_BASE_ADDR 0x53fb8000 -#define MX25_LCDC_BASE_ADDR 0x53fbc000 -#define MX25_KPP_BASE_ADDR 0x43fa8000 -#define MX25_SDMA_BASE_ADDR 0x53fd4000 -#define MX25_USB_BASE_ADDR 0x53ff4000 -#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) -/* - * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 - * for the host controller. Early documentation drafts specified 0x400 and - * Freescale internal sources confirm only the latter value to work. - */ -#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) -#define MX25_CSI_BASE_ADDR 0x53ff8000 - -#define MX25_IO_P2V(x) IMX_IO_P2V(x) -#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX25_INT_CSPI3 (NR_IRQS_LEGACY + 0) -#define MX25_INT_I2C1 (NR_IRQS_LEGACY + 3) -#define MX25_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX25_INT_UART4 (NR_IRQS_LEGACY + 5) -#define MX25_INT_ESDHC2 (NR_IRQS_LEGACY + 8) -#define MX25_INT_ESDHC1 (NR_IRQS_LEGACY + 9) -#define MX25_INT_I2C3 (NR_IRQS_LEGACY + 10) -#define MX25_INT_SSI2 (NR_IRQS_LEGACY + 11) -#define MX25_INT_SSI1 (NR_IRQS_LEGACY + 12) -#define MX25_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX25_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX25_INT_GPIO3 (NR_IRQS_LEGACY + 16) -#define MX25_INT_CSI (NR_IRQS_LEGACY + 17) -#define MX25_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX25_INT_GPIO4 (NR_IRQS_LEGACY + 23) -#define MX25_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX25_INT_DRYICE (NR_IRQS_LEGACY + 25) -#define MX25_INT_PWM1 (NR_IRQS_LEGACY + 26) -#define MX25_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX25_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX25_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX25_INT_USB_HS (NR_IRQS_LEGACY + 35) -#define MX25_INT_PWM2 (NR_IRQS_LEGACY + 36) -#define MX25_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX25_INT_LCDC (NR_IRQS_LEGACY + 39) -#define MX25_INT_UART5 (NR_IRQS_LEGACY + 40) -#define MX25_INT_PWM3 (NR_IRQS_LEGACY + 41) -#define MX25_INT_PWM4 (NR_IRQS_LEGACY + 42) -#define MX25_INT_CAN1 (NR_IRQS_LEGACY + 43) -#define MX25_INT_CAN2 (NR_IRQS_LEGACY + 44) -#define MX25_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX25_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX25_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX25_INT_GPT1 (NR_IRQS_LEGACY + 54) -#define MX25_INT_FEC (NR_IRQS_LEGACY + 57) - -#define MX25_DMA_REQ_SSI2_RX1 22 -#define MX25_DMA_REQ_SSI2_TX1 23 -#define MX25_DMA_REQ_SSI2_RX0 24 -#define MX25_DMA_REQ_SSI2_TX0 25 -#define MX25_DMA_REQ_SSI1_RX1 26 -#define MX25_DMA_REQ_SSI1_TX1 27 -#define MX25_DMA_REQ_SSI1_RX0 28 -#define MX25_DMA_REQ_SSI1_TX0 29 - -#ifndef __ASSEMBLY__ -extern int mx25_revision(void); -#endif - -#endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h index e074616d54ca..241c04d706fe 100644 --- a/arch/arm/mach-imx/mx27.h +++ b/arch/arm/mach-imx/mx27.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de @@ -5,20 +6,6 @@ * This contains i.MX27-specific hardware definitions. For those * hardware pieces that are common between i.MX21 and i.MX27, have a * look at mx2x.h. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __MACH_MX27_H__ @@ -26,213 +13,13 @@ #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_SIZE SZ_1M -#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) -#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) -#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) -#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) -#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) -#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) -#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) -#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) -#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) -#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) -#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) -#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) -#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) -#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) -#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) -#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) -#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) -#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) -#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) -#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) -#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) -#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) -#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) -#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) -#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) -#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) -#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) -#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) -#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) -#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) -#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) -#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) -#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) -#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) -#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) -#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) -#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) -#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) -#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) -#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) -#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) -#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) -#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) -#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) -#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) -#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) -#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) -#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) -#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) -#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) - -#define MX27_AVIC_BASE_ADDR 0x10040000 - -/* ROM patch */ -#define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 #define MX27_SAHB1_SIZE SZ_1M -#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) -#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) - -/* Memory regions and CS */ -#define MX27_SDRAM_BASE_ADDR 0xa0000000 -#define MX27_CSD1_BASE_ADDR 0xb0000000 - -#define MX27_CS0_BASE_ADDR 0xc0000000 -#define MX27_CS1_BASE_ADDR 0xc8000000 -#define MX27_CS2_BASE_ADDR 0xd0000000 -#define MX27_CS3_BASE_ADDR 0xd2000000 -#define MX27_CS4_BASE_ADDR 0xd4000000 -#define MX27_CS5_BASE_ADDR 0xd6000000 -/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 #define MX27_X_MEMC_SIZE SZ_1M -#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) -#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) -#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) -#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) -#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) - -#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 - -/* IRAM */ -#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ #define MX27_IO_P2V(x) IMX_IO_P2V(x) -#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) -#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) -#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) -#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) -#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) -#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX27_INT_SDHC (NR_IRQS_LEGACY + 7) -#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) -#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) -#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX27_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX27_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX27_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX27_INT_NFC (NR_IRQS_LEGACY + 29) -#define MX27_INT_ATA (NR_IRQS_LEGACY + 30) -#define MX27_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) -#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) -#define MX27_INT_FEC (NR_IRQS_LEGACY + 50) -#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX27_INT_VPU (NR_IRQS_LEGACY + 53) -#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) -#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) -#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) -#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) -#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) -#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) -#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) -#define MX27_INT_IIM (NR_IRQS_LEGACY + 62) -#define MX27_INT_CCM (NR_IRQS_LEGACY + 63) - -/* fixed DMA request numbers */ -#define MX27_DMA_REQ_CSPI3_RX 1 -#define MX27_DMA_REQ_CSPI3_TX 2 -#define MX27_DMA_REQ_EXT 3 -#define MX27_DMA_REQ_MSHC 4 -#define MX27_DMA_REQ_SDHC2 6 -#define MX27_DMA_REQ_SDHC1 7 -#define MX27_DMA_REQ_SSI2_RX0 8 -#define MX27_DMA_REQ_SSI2_TX0 9 -#define MX27_DMA_REQ_SSI2_RX1 10 -#define MX27_DMA_REQ_SSI2_TX1 11 -#define MX27_DMA_REQ_SSI1_RX0 12 -#define MX27_DMA_REQ_SSI1_TX0 13 -#define MX27_DMA_REQ_SSI1_RX1 14 -#define MX27_DMA_REQ_SSI1_TX1 15 -#define MX27_DMA_REQ_CSPI2_RX 16 -#define MX27_DMA_REQ_CSPI2_TX 17 -#define MX27_DMA_REQ_CSPI1_RX 18 -#define MX27_DMA_REQ_CSPI1_TX 19 -#define MX27_DMA_REQ_UART4_RX 20 -#define MX27_DMA_REQ_UART4_TX 21 -#define MX27_DMA_REQ_UART3_RX 22 -#define MX27_DMA_REQ_UART3_TX 23 -#define MX27_DMA_REQ_UART2_RX 24 -#define MX27_DMA_REQ_UART2_TX 25 -#define MX27_DMA_REQ_UART1_RX 26 -#define MX27_DMA_REQ_UART1_TX 27 -#define MX27_DMA_REQ_ATA_TX 28 -#define MX27_DMA_REQ_ATA_RCV 29 -#define MX27_DMA_REQ_CSI_STAT 30 -#define MX27_DMA_REQ_CSI_RX 31 -#define MX27_DMA_REQ_UART5_TX 32 -#define MX27_DMA_REQ_UART5_RX 33 -#define MX27_DMA_REQ_UART6_TX 34 -#define MX27_DMA_REQ_UART6_RX 35 -#define MX27_DMA_REQ_SDHC3 36 -#define MX27_DMA_REQ_NFC 37 - -#ifndef __ASSEMBLY__ -extern int mx27_revision(void); -#endif #endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/mach-imx/mx2x.h b/arch/arm/mach-imx/mx2x.h index 11642f5b224c..841c34e111f1 100644 --- a/arch/arm/mach-imx/mx2x.h +++ b/arch/arm/mach-imx/mx2x.h @@ -1,23 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This contains hardware definitions that are common between i.MX21 and * i.MX27. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __MACH_MX2x_H__ diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h index ee9b1f9215df..08a72e25c289 100644 --- a/arch/arm/mach-imx/mx31.h +++ b/arch/arm/mach-imx/mx31.h @@ -1,196 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_MX31_H__ #define __MACH_MX31_H__ -/* - * IRAM - */ -#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ -#define MX31_IRAM_SIZE SZ_16K - -#define MX31_L2CC_BASE_ADDR 0x30000000 -#define MX31_L2CC_SIZE SZ_1M - #define MX31_AIPS1_BASE_ADDR 0x43f00000 #define MX31_AIPS1_SIZE SZ_1M -#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) -#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) -#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) -#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) -#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) -#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) -#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) -#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) -#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) -#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) -#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) -#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) -#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) -#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) -#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) -#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) -#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) -#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) -#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) -#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) -#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) -#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) -#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) - #define MX31_SPBA0_BASE_ADDR 0x50000000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) -#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) -#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) -#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) -#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) -#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) -#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) -#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) -#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) - #define MX31_AIPS2_BASE_ADDR 0x53f00000 #define MX31_AIPS2_SIZE SZ_1M -#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) -#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) -#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) -#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) -#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) -#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) -#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) -#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) -#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) -#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) -#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) -#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) -#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) -#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) -#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) -#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) -#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) -#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) -#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) -#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) -#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) - -#define MX31_ROMP_BASE_ADDR 0x60000000 -#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000) -#define MX31_ROMP_SIZE SZ_1M - #define MX31_AVIC_BASE_ADDR 0x68000000 #define MX31_AVIC_SIZE SZ_1M - -#define MX31_IPU_MEM_BASE_ADDR 0x70000000 -#define MX31_CSD0_BASE_ADDR 0x80000000 -#define MX31_CSD1_BASE_ADDR 0x90000000 - -#define MX31_CS0_BASE_ADDR 0xa0000000 -#define MX31_CS1_BASE_ADDR 0xa8000000 -#define MX31_CS2_BASE_ADDR 0xb0000000 -#define MX31_CS3_BASE_ADDR 0xb2000000 - -#define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000) -#define MX31_CS4_SIZE SZ_32M - -#define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000) -#define MX31_CS5_SIZE SZ_32M - #define MX31_X_MEMC_BASE_ADDR 0xb8000000 #define MX31_X_MEMC_SIZE SZ_64K -#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) -#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) -#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) -#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) -#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) -#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR - -#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX31_IO_P2V(x) IMX_IO_P2V(x) -#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) -#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) -#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) -#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) -#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) -#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) -#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) -#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX31_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX31_INT_MBX (NR_IRQS_LEGACY + 16) -#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) -#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX31_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) -#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) -#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX31_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX31_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX31_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX31_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) -#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX31_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) -#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) -#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) -#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) -#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) -#define MX31_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX31_INT_CCM (NR_IRQS_LEGACY + 53) -#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) -#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX31_DMA_REQ_SDHC1 20 -#define MX31_DMA_REQ_SDHC2 21 -#define MX31_DMA_REQ_SSI2_RX1 22 -#define MX31_DMA_REQ_SSI2_TX1 23 -#define MX31_DMA_REQ_SSI2_RX0 24 -#define MX31_DMA_REQ_SSI2_TX0 25 -#define MX31_DMA_REQ_SSI1_RX1 26 -#define MX31_DMA_REQ_SSI1_TX1 27 -#define MX31_DMA_REQ_SSI1_RX0 28 -#define MX31_DMA_REQ_SSI1_TX0 29 - -#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c deleted file mode 100644 index d4361b80c5fb..000000000000 --- a/arch/arm/mach-imx/mx31lilly-db.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * LILLY-1131 development board support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "board-mx31lilly.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* - * This file contains board-specific initialization routines for the - * LILLY-1131 development board. If you design an own baseboard for the - * module, use this file as base for support code. - */ - -static unsigned int lilly_db_board_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_CONTRAST__CONTRAST, -}; - -/* UART */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* MMC support */ - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); -} - -static int gpio_det, gpio_wp; - -#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); - - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), - detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data); -} - -static const struct imxmmc_platform_data mmc_pdata __initconst = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* Framebuffer support */ -static const struct fb_videomode fb_modedb = { - /* 640x480 TFT panel (IPS-056T) */ - .name = "CRT-VGA", - .refresh = 64, - .xres = 640, - .yres = 480, - .pixclock = 30000, - .left_margin = 200, - .right_margin = 2, - .upper_margin = 2, - .lower_margin = 2, - .hsync_len = 3, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct mx3fb_platform_data fb_pdata __initdata = { - .name = "CRT-VGA", - .mode = &fb_modedb, - .num_modes = 1, -}; - -#define LCD_VCC_EN_GPIO (7) - -static void __init mx31lilly_init_fb(void) -{ - if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) { - printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n"); - return; - } - - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&fb_pdata); - gpio_direction_output(LCD_VCC_EN_GPIO, 1); -} - -void __init mx31lilly_db_init(void) -{ - mxc_iomux_setup_multiple_pins(lilly_db_board_pins, - ARRAY_SIZE(lilly_db_board_pins), - "development board pins"); - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); - imx31_add_imx_uart2(&uart_pdata); - imx31_add_mxc_mmc(0, &mmc_pdata); - mx31lilly_init_fb(); -} diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c deleted file mode 100644 index 5a160b7e4fce..000000000000 --- a/arch/arm/mach-imx/mx31lite-db.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * LogicPD i.MX31 SOM-LV development board support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "board-mx31lite.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* - * This file contains board-specific initialization routines for the - * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'. - * If you design an own baseboard for the module, use this file as base - * for support code. - */ - -static unsigned int litekit_db_board_pins[] __initdata = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* SPI 0 */ - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* SDHC1 */ - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, -}; - -/* UART */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* MMC */ - -static int gpio_det, gpio_wp; - -#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS) - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6)); -} - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); - - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), - detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data); -} - -static const struct imxmmc_platform_data mmc_pdata __initconst = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* SPI */ - -static int spi_internal_chipselect[] = { - MXC_SPI_CS(0), - MXC_SPI_CS(1), - MXC_SPI_CS(2), -}; - -static const struct spi_imx_master spi0_pdata __initconst = { - .chipselect = spi_internal_chipselect, - .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), -}; - -/* GPIO LEDs */ - -static const struct gpio_led litekit_leds[] __initconst = { - { - .name = "GPIO0", - .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE), - .active_low = 1, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, - { - .name = "GPIO1", - .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE), - .active_low = 1, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - } -}; - -static const struct gpio_led_platform_data - litekit_led_platform_data __initconst = { - .leds = litekit_leds, - .num_leds = ARRAY_SIZE(litekit_leds), -}; - -void __init mx31lite_db_init(void) -{ - mxc_iomux_setup_multiple_pins(litekit_db_board_pins, - ARRAY_SIZE(litekit_db_board_pins), - "development board pins"); - imx31_add_imx_uart0(&uart_pdata); - imx31_add_mxc_mmc(0, &mmc_pdata); - imx31_add_spi_imx0(&spi0_pdata); - gpio_led_register_device(-1, &litekit_led_platform_data); - imx31_add_imx2_wdt(); - imx31_add_mxc_rtc(); -} diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c deleted file mode 100644 index 52d5b1574721..000000000000 --- a/arch/arm/mach-imx/mx31moboard-devboard.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int devboard_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* USB H1 */ - MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, - MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int devboard_sdhc2_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC2_WP); -} - -static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void devboard_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .get_ro = devboard_sdhc2_get_ro, - .init = devboard_sdhc2_init, - .exit = devboard_sdhc2_exit, -}; - -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void devboard_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int devboard_usbh1_hw_init(struct platform_device *pdev) -{ - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) -#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) - -static int devboard_isp1105_init(struct usb_phy *otg) -{ - int ret = gpio_request(USBH1_MODE, "usbh1-mode"); - if (ret) - return ret; - /* single ended */ - gpio_direction_output(USBH1_MODE, 0); - - ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); - if (ret) { - gpio_free(USBH1_MODE); - return ret; - } - gpio_direction_output(USBH1_VBUSEN_B, 1); - - return 0; -} - - -static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on) -{ - if (on) - gpio_set_value(USBH1_VBUSEN_B, 0); - else - gpio_set_value(USBH1_VBUSEN_B, 1); - - return 0; -} - -static struct mxc_usbh_platform_data usbh1_pdata __initdata = { - .init = devboard_usbh1_hw_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static int __init devboard_usbh1_init(void) -{ - struct usb_phy *phy; - struct platform_device *pdev; - - phy = kzalloc(sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); - if (!phy->otg) { - kfree(phy); - return -ENOMEM; - } - - phy->label = "ISP1105"; - phy->init = devboard_isp1105_init; - phy->otg->set_vbus = devboard_isp1105_set_vbus; - - usbh1_pdata.otg = phy; - - pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_devboard_init(void) -{ - printk(KERN_INFO "Initializing mx31devboard peripherals\n"); - - mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), - "devboard"); - - imx31_add_imx_uart1(&uart_pdata); - - imx31_add_mxc_mmc(1, &sdhc2_pdata); - - devboard_init_sel_gpios(); - - imx31_add_fsl_usb2_udc(&usb_pdata); - - devboard_usbh1_init(); -} diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c deleted file mode 100644 index a4f43e90f3c1..000000000000 --- a/arch/arm/mach-imx/mx31moboard-marxbot.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/spi/spi.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> - -#include <media/soc_camera.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int marxbot_pins[] = { - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* CSI */ - MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5, - MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, - MX31_PIN_TXD2__GPIO1_28, - /* dsPIC resets */ - MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, - /*battery detection */ - MX31_PIN_LCS0__GPIO3_23, - /* USB H1 */ - MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, - MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int marxbot_sdhc2_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC2_WP); -} - -static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void marxbot_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .get_ro = marxbot_sdhc2_get_ro, - .init = marxbot_sdhc2_init, - .exit = marxbot_sdhc2_exit, -}; - -#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5) -#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5) - -static void dspics_resets_init(void) -{ - if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 0); - gpio_export(TRSLAT_RST_B, false); - } - - if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { - gpio_direction_output(DSPICS_RST_B, 0); - gpio_export(DSPICS_RST_B, false); - } -} - -static struct spi_board_info marxbot_spi_board_info[] __initdata = { - { - .modalias = "spidev", - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 1, /* according spi1_cs[] ! */ - }, -}; - -#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5) -#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) -#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4) -#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2) - -static int marxbot_basecam_power(struct device *dev, int on) -{ - gpio_set_value(BASECAM_POWER, !on); - return 0; -} - -static int marxbot_basecam_reset(struct device *dev) -{ - gpio_set_value(BASECAM_RST_B, 0); - udelay(100); - gpio_set_value(BASECAM_RST_B, 1); - return 0; -} - -static struct i2c_board_info marxbot_i2c_devices[] = { - { - I2C_BOARD_INFO("mt9t031", 0x5d), - }, -}; - -static struct soc_camera_link base_iclink = { - .bus_id = 0, /* Must match with the camera ID */ - .power = marxbot_basecam_power, - .reset = marxbot_basecam_reset, - .board_info = &marxbot_i2c_devices[0], - .i2c_adapter_id = 0, -}; - -static struct platform_device marxbot_camera[] = { - { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &base_iclink, - }, - }, -}; - -static struct platform_device *marxbot_cameras[] __initdata = { - &marxbot_camera[0], -}; - -static int __init marxbot_cam_init(void) -{ - int ret = gpio_request(CAM_CHOICE, "cam-choice"); - if (ret) - return ret; - gpio_direction_output(CAM_CHOICE, 0); - - ret = gpio_request(BASECAM_RST_B, "basecam-reset"); - if (ret) - return ret; - gpio_direction_output(BASECAM_RST_B, 1); - ret = gpio_request(BASECAM_POWER, "basecam-standby"); - if (ret) - return ret; - gpio_direction_output(BASECAM_POWER, 0); - - ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset"); - if (ret) - return ret; - gpio_direction_output(TURRETCAM_RST_B, 1); - ret = gpio_request(TURRETCAM_POWER, "turretcam-standby"); - if (ret) - return ret; - gpio_direction_output(TURRETCAM_POWER, 0); - - return 0; -} - -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void marxbot_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int marxbot_usbh1_hw_init(struct platform_device *pdev) -{ - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) -#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) - -static int marxbot_isp1105_init(struct usb_phy *otg) -{ - int ret = gpio_request(USBH1_MODE, "usbh1-mode"); - if (ret) - return ret; - /* single ended */ - gpio_direction_output(USBH1_MODE, 0); - - ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); - if (ret) { - gpio_free(USBH1_MODE); - return ret; - } - gpio_direction_output(USBH1_VBUSEN_B, 1); - - return 0; -} - - -static int marxbot_isp1105_set_vbus(struct usb_otg *otg, bool on) -{ - if (on) - gpio_set_value(USBH1_VBUSEN_B, 0); - else - gpio_set_value(USBH1_VBUSEN_B, 1); - - return 0; -} - -static struct mxc_usbh_platform_data usbh1_pdata __initdata = { - .init = marxbot_usbh1_hw_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static int __init marxbot_usbh1_init(void) -{ - struct usb_phy *phy; - struct platform_device *pdev; - - phy = kzalloc(sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); - if (!phy->otg) { - kfree(phy); - return -ENOMEM; - } - - phy->label = "ISP1105"; - phy->init = marxbot_isp1105_init; - phy->otg->set_vbus = marxbot_isp1105_set_vbus; - - usbh1_pdata.otg = phy; - - pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_marxbot_init(void) -{ - printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), - "marxbot"); - - marxbot_init_sel_gpios(); - - dspics_resets_init(); - - imx31_add_mxc_mmc(1, &sdhc2_pdata); - - spi_register_board_info(marxbot_spi_board_info, - ARRAY_SIZE(marxbot_spi_board_info)); - - marxbot_cam_init(); - platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras)); - - /* battery present pin */ - gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); - gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); - - imx31_add_fsl_usb2_udc(&usb_pdata); - - marxbot_usbh1_init(); -} diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c deleted file mode 100644 index 04ae45dbfaa7..000000000000 --- a/arch/arm/mach-imx/mx31moboard-smartbot.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <media/soc_camera.h> - -#include "board-mx31moboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int smartbot_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* CSI */ - MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, - MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, - MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, - MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, - MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, - MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, - MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, - MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, - MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, - /* ENABLES */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) - -static int smartbot_cam_power(struct device *dev, int on) -{ - gpio_set_value(CAM_POWER, !on); - return 0; -} - -static int smartbot_cam_reset(struct device *dev) -{ - gpio_set_value(CAM_RST_B, 0); - udelay(100); - gpio_set_value(CAM_RST_B, 1); - return 0; -} - -static struct i2c_board_info smartbot_i2c_devices[] = { - { - I2C_BOARD_INFO("mt9t031", 0x5d), - }, -}; - -static struct soc_camera_link base_iclink = { - .bus_id = 0, /* Must match with the camera ID */ - .power = smartbot_cam_power, - .reset = smartbot_cam_reset, - .board_info = &smartbot_i2c_devices[0], - .i2c_adapter_id = 0, -}; - -static struct platform_device smartbot_camera[] = { - { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { - .platform_data = &base_iclink, - }, - }, -}; - -static struct platform_device *smartbot_cameras[] __initdata = { - &smartbot_camera[0], -}; - -static int __init smartbot_cam_init(void) -{ - int ret = gpio_request(CAM_RST_B, "cam-reset"); - if (ret) - return ret; - gpio_direction_output(CAM_RST_B, 1); - ret = gpio_request(CAM_POWER, "cam-standby"); - if (ret) - return ret; - gpio_direction_output(CAM_POWER, 0); - - return 0; -} - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -#if defined(CONFIG_USB_ULPI) - -static int smartbot_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data otg_host_pdata __initdata = { - .init = smartbot_otg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static int __init smartbot_otg_host_init(void) -{ - struct platform_device *pdev; - - otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (!otg_host_pdata.otg) - return -ENODEV; - - pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} -#else -static inline int smartbot_otg_host_init(void) { return 0; } -#endif - -#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void smartbot_resets_init(void) -{ - if (!gpio_request(POWER_EN, "power-enable")) { - gpio_direction_output(POWER_EN, 0); - gpio_export(POWER_EN, false); - } - - if (!gpio_request(DSPIC_RST_B, "dspic-rst")) { - gpio_direction_output(DSPIC_RST_B, 0); - gpio_export(DSPIC_RST_B, false); - } - - if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 0); - gpio_export(TRSLAT_RST_B, false); - } - - if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) { - gpio_direction_output(TRSLAT_SRC_CHOICE, 0); - gpio_export(TRSLAT_SRC_CHOICE, false); - } -} -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_smartbot_init(int board) -{ - printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), - "smartbot"); - - imx31_add_imx_uart1(&uart_pdata); - - switch (board) { - case MX31SMARTBOT: - imx31_add_fsl_usb2_udc(&usb_pdata); - break; - case MX31EYEBOT: - smartbot_otg_host_init(); - break; - default: - printk(KERN_WARNING "Unknown board %d, USB OTG not initialized", - board); - } - - smartbot_resets_init(); - - smartbot_cam_init(); - platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras)); -} diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h index 2af5d3a699c7..5a8a87a85c14 100644 --- a/arch/arm/mach-imx/mx35.h +++ b/arch/arm/mach-imx/mx35.h @@ -1,190 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_MX35_H__ #define __MACH_MX35_H__ -/* - * IRAM - */ -#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define MX35_IRAM_SIZE SZ_128K - -#define MX35_L2CC_BASE_ADDR 0x30000000 -#define MX35_L2CC_SIZE SZ_1M - #define MX35_AIPS1_BASE_ADDR 0x43f00000 #define MX35_AIPS1_SIZE SZ_1M -#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) -#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) -#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) -#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) -#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) -#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) -#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) -#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) -#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) -#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) -#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) -#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) -#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) -#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) -#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) -#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) -#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) - #define MX35_SPBA0_BASE_ADDR 0x50000000 #define MX35_SPBA0_SIZE SZ_1M -#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) -#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) -#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) -#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) -#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) -#define MX35_FEC_BASE_ADDR 0x50038000 -#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) - #define MX35_AIPS2_BASE_ADDR 0x53f00000 #define MX35_AIPS2_SIZE SZ_1M -#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) -#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) -#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) -#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) -#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) -#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) -#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) -#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) -#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) -#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) -#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) -#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) -#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) -#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) -#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) -#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) -#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) -#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) -#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) -#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) -#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) -#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) -#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) -/* - * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for - * HS. When host support was implemented only a preliminary document was - * available, which told 0x400. This works fine. - */ -#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) - -#define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_SIZE SZ_1M - #define MX35_AVIC_BASE_ADDR 0x68000000 #define MX35_AVIC_SIZE SZ_1M - -/* - * Memory regions and CS - */ -#define MX35_IPU_MEM_BASE_ADDR 0x70000000 -#define MX35_CSD0_BASE_ADDR 0x80000000 -#define MX35_CSD1_BASE_ADDR 0x90000000 - -#define MX35_CS0_BASE_ADDR 0xa0000000 -#define MX35_CS1_BASE_ADDR 0xa8000000 -#define MX35_CS2_BASE_ADDR 0xb0000000 -#define MX35_CS3_BASE_ADDR 0xb2000000 - -#define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 -#define MX35_CS4_SIZE SZ_32M - -#define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 -#define MX35_CS5_SIZE SZ_32M - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ #define MX35_X_MEMC_BASE_ADDR 0xb8000000 #define MX35_X_MEMC_SIZE SZ_64K -#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) -#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) -#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) -#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) -#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR - -#define MX35_NFC_BASE_ADDR 0xbb000000 -#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX35_IO_P2V(x) IMX_IO_P2V(x) -#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) -#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) -#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) -#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) -#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) -#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) -#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) -#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX35_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) -#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) -#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX35_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX35_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX35_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX35_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX35_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX35_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) -#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) -#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) -#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) -#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX35_INT_MLB (NR_IRQS_LEGACY + 46) -#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) -#define MX35_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX35_INT_FEC (NR_IRQS_LEGACY + 57) -#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX35_DMA_REQ_SSI2_RX1 22 -#define MX35_DMA_REQ_SSI2_TX1 23 -#define MX35_DMA_REQ_SSI2_RX0 24 -#define MX35_DMA_REQ_SSI2_TX0 25 -#define MX35_DMA_REQ_SSI1_RX1 26 -#define MX35_DMA_REQ_SSI1_TX1 27 -#define MX35_DMA_REQ_SSI1_RX0 28 -#define MX35_DMA_REQ_SSI1_TX0 29 - -#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/mach-imx/mx3x.h b/arch/arm/mach-imx/mx3x.h index 96fb4fbc8ad7..74b379488e61 100644 --- a/arch/arm/mach-imx/mx3x.h +++ b/arch/arm/mach-imx/mx3x.h @@ -1,12 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. */ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ #ifndef __MACH_MX3x_H__ #define __MACH_MX3x_H__ @@ -185,11 +181,4 @@ #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ -/* Mandatory defines used globally */ - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx35_revision(void); -extern int mx31_revision(void); -#endif - #endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/mach-imx/mx51.h b/arch/arm/mach-imx/mx51.h deleted file mode 100644 index af844f76261a..000000000000 --- a/arch/arm/mach-imx/mx51.h +++ /dev/null @@ -1,346 +0,0 @@ -#ifndef __MACH_MX51_H__ -#define __MACH_MX51_H__ - -/* - * IROM - */ -#define MX51_IROM_BASE_ADDR 0x0 -#define MX51_IROM_SIZE SZ_64K - -/* - * IRAM - */ -#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ -#define MX51_IRAM_PARTITIONS 16 -#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -#define MX51_GPU_BASE_ADDR 0x20000000 -#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 -#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 - -/* - * SPBA global module enabled #0 - */ -#define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_SPBA0_SIZE SZ_1M - -#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) -#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000) -#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000) -#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000) -#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000) -#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000) -#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000) -#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000) -#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000) -#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000) -#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000) -#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000) - -/* - * AIPS 1 - */ -#define MX51_AIPS1_BASE_ADDR 0x73f00000 -#define MX51_AIPS1_SIZE SZ_1M - -#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) -#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000) -#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200) -#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400) -#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000) -#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000) -#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) -#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) -#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) -#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) -#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) -#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) -#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) -#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000) -#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000) -#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000) -#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000) -#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000) -#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000) -#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000) -#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000) -#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000) -#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000) - -/* - * AIPS 2 - */ -#define MX51_AIPS2_BASE_ADDR 0x83f00000 -#define MX51_AIPS2_SIZE SZ_1M - -#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) -#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000) -#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000) -#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000) -#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000) -#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000) -#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000) -#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000) -#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000) -#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000) -#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000) -#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000) -#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000) -#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000) -#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000) -#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000) -#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000) -#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000) -#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000) -#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000) -#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000) -#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000) -#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000) -#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00) -#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) -#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) -#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) -#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) -#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) -#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) -#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) -#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000) - -#define MX51_CSD0_BASE_ADDR 0x90000000 -#define MX51_CSD1_BASE_ADDR 0xa0000000 -#define MX51_CS0_BASE_ADDR 0xb0000000 -#define MX51_CS1_BASE_ADDR 0xb8000000 -#define MX51_CS2_BASE_ADDR 0xc0000000 -#define MX51_CS3_BASE_ADDR 0xc8000000 -#define MX51_CS4_BASE_ADDR 0xcc000000 -#define MX51_CS5_BASE_ADDR 0xce000000 - -/* - * NFC - */ -#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */ -#define MX51_NFC_AXI_SIZE SZ_64K - -#define MX51_GPU2D_BASE_ADDR 0xd0000000 -#define MX51_TZIC_BASE_ADDR 0xe0000000 -#define MX51_TZIC_SIZE SZ_16K - -#define MX51_IO_P2V(x) IMX_IO_P2V(x) -#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX51_SPBA_SDHC1 0x04 -#define MX51_SPBA_SDHC2 0x08 -#define MX51_SPBA_UART3 0x0c -#define MX51_SPBA_CSPI1 0x10 -#define MX51_SPBA_SSI2 0x14 -#define MX51_SPBA_SDHC3 0x20 -#define MX51_SPBA_SDHC4 0x24 -#define MX51_SPBA_SPDIF 0x28 -#define MX51_SPBA_ATA 0x30 -#define MX51_SPBA_SLIM 0x34 -#define MX51_SPBA_HSI2C 0x38 -#define MX51_SPBA_CTRL 0x3c - -/* - * Defines for modules using static and dynamic DMA channels - */ -#define MX51_MXC_DMA_CHANNEL_IRAM 30 -#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL -#ifdef CONFIG_SDMA_IRAM -#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) -#else /*CONFIG_SDMA_IRAM */ -#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL -#endif /*CONFIG_SDMA_IRAM */ -#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL -#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL - -#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 - -/* - * DMA request assignments - */ -#define MX51_DMA_REQ_VPU 0 -#define MX51_DMA_REQ_GPC 1 -#define MX51_DMA_REQ_ATA_RX 2 -#define MX51_DMA_REQ_ATA_TX 3 -#define MX51_DMA_REQ_ATA_TX_END 4 -#define MX51_DMA_REQ_SLIM_B 5 -#define MX51_DMA_REQ_CSPI1_RX 6 -#define MX51_DMA_REQ_CSPI1_TX 7 -#define MX51_DMA_REQ_CSPI2_RX 8 -#define MX51_DMA_REQ_CSPI2_TX 9 -#define MX51_DMA_REQ_HS_I2C_TX 10 -#define MX51_DMA_REQ_HS_I2C_RX 11 -#define MX51_DMA_REQ_FIRI_RX 12 -#define MX51_DMA_REQ_FIRI_TX 13 -#define MX51_DMA_REQ_EXTREQ1 14 -#define MX51_DMA_REQ_GPU 15 -#define MX51_DMA_REQ_UART2_RX 16 -#define MX51_DMA_REQ_UART2_TX 17 -#define MX51_DMA_REQ_UART1_RX 18 -#define MX51_DMA_REQ_UART1_TX 19 -#define MX51_DMA_REQ_SDHC1 20 -#define MX51_DMA_REQ_SDHC2 21 -#define MX51_DMA_REQ_SSI2_RX1 22 -#define MX51_DMA_REQ_SSI2_TX1 23 -#define MX51_DMA_REQ_SSI2_RX0 24 -#define MX51_DMA_REQ_SSI2_TX0 25 -#define MX51_DMA_REQ_SSI1_RX1 26 -#define MX51_DMA_REQ_SSI1_TX1 27 -#define MX51_DMA_REQ_SSI1_RX0 28 -#define MX51_DMA_REQ_SSI1_TX0 29 -#define MX51_DMA_REQ_EMI_RD 30 -#define MX51_DMA_REQ_CTI2_0 31 -#define MX51_DMA_REQ_EMI_WR 32 -#define MX51_DMA_REQ_CTI2_1 33 -#define MX51_DMA_REQ_EPIT2 34 -#define MX51_DMA_REQ_SSI3_RX1 35 -#define MX51_DMA_REQ_IPU 36 -#define MX51_DMA_REQ_SSI3_TX1 37 -#define MX51_DMA_REQ_CSPI_RX 38 -#define MX51_DMA_REQ_CSPI_TX 39 -#define MX51_DMA_REQ_SDHC3 40 -#define MX51_DMA_REQ_SDHC4 41 -#define MX51_DMA_REQ_SLIM_B_TX 42 -#define MX51_DMA_REQ_UART3_RX 43 -#define MX51_DMA_REQ_UART3_TX 44 -#define MX51_DMA_REQ_SPDIF 45 -#define MX51_DMA_REQ_SSI3_RX0 46 -#define MX51_DMA_REQ_SSI3_TX0 47 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX51_INT_BASE (NR_IRQS_LEGACY + 0) -#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0) -#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1) -#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2) -#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3) -#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4) -#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5) -#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX51_INT_NFC (NR_IRQS_LEGACY + 8) -#define MX51_INT_VPU (NR_IRQS_LEGACY + 9) -#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10) -#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11) -#define MX51_INT_GPU (NR_IRQS_LEGACY + 12) -#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13) -#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14) -#define MX51_INT_EMI (NR_IRQS_LEGACY + 15) -#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16) -#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17) -#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) -#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) -#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21) -#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22) -#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23) -#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26) -#define MX51_INT_CSU (NR_IRQS_LEGACY + 27) -#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28) -#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34) -#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35) -#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36) -#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37) -#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX51_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41) -#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59) -#define MX51_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64) -#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65) -#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66) -#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67) -#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68) -#define MX51_INT_IIM (NR_IRQS_LEGACY + 69) -#define MX51_INT_ATA (NR_IRQS_LEGACY + 70) -#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX51_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX51_INT_NM (NR_IRQS_LEGACY + 76) -#define MX51_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81) -#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82) -#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83) -#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86) -#define MX51_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX51_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91) -#define MX51_INT_TVE (NR_IRQS_LEGACY + 92) -#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93) -#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) -#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96) -#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) -#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99) -#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) -#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101) -#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) - -#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern int mx51_revision(void); -extern void mx51_display_revision(void); -#endif - -#endif /* ifndef __MACH_MX51_H__ */ diff --git a/arch/arm/mach-imx/mx53.h b/arch/arm/mach-imx/mx53.h deleted file mode 100644 index f829d1c22501..000000000000 --- a/arch/arm/mach-imx/mx53.h +++ /dev/null @@ -1,342 +0,0 @@ -#ifndef __MACH_MX53_H__ -#define __MACH_MX53_H__ - -/* - * IROM - */ -#define MX53_IROM_BASE_ADDR 0x0 -#define MX53_IROM_SIZE SZ_64K - -/* TZIC */ -#define MX53_TZIC_BASE_ADDR 0x0FFFC000 -#define MX53_TZIC_SIZE SZ_16K - -/* - * AHCI SATA - */ -#define MX53_SATA_BASE_ADDR 0x10000000 - -/* - * NFC - */ -#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ -#define MX53_NFC_AXI_SIZE SZ_64K - -/* - * IRAM - */ -#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */ -#define MX53_IRAM_PARTITIONS 16 -#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ - -/* - * Graphics Memory of GPU - */ -#define MX53_IPU_CTRL_BASE_ADDR 0x18000000 -#define MX53_GPU2D_BASE_ADDR 0x20000000 -#define MX53_GPU_BASE_ADDR 0x30000000 -#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000 - -#define MX53_DEBUG_BASE_ADDR 0x40000000 -#define MX53_DEBUG_SIZE SZ_1M -#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) -#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) -#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) -#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) -#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) -#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) -#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) -#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) - -/* - * SPBA global module enabled #0 - */ -#define MX53_SPBA0_BASE_ADDR 0x50000000 -#define MX53_SPBA0_SIZE SZ_1M - -#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) -#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) -#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) -#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) -#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) -#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) -#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) -#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) -#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) -#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) -#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) -#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) -#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define MX53_AIPS1_BASE_ADDR 0x53F00000 -#define MX53_AIPS1_SIZE SZ_1M - -#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) -#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) -#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) -#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) -#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) -#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) -#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) -#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) -#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) -#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) -#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) -#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) -#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) -#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) -#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) -#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) -#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) -#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) -#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) -#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) -#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) -#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) -#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) -#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) -#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) -#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) - -/* - * AIPS 2 - */ -#define MX53_AIPS2_BASE_ADDR 0x63F00000 -#define MX53_AIPS2_SIZE SZ_1M - -#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) -#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) -#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) -#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) -#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) -#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) -#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) -#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) -#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) -#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) -#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) -#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) -#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) -#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) -#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) -#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) -#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) -#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) -#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) -#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) -#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) -#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) -#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) -#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) -#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) -#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) -#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) -#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) -#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) -#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) -#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) -#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) -#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) -#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) -#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) - -/* - * Memory regions and CS - */ -#define MX53_CSD0_BASE_ADDR 0x70000000 -#define MX53_CSD1_BASE_ADDR 0xB0000000 -#define MX53_CS0_BASE_ADDR 0xF0000000 -#define MX53_CS1_32MB_BASE_ADDR 0xF2000000 -#define MX53_CS1_64MB_BASE_ADDR 0xF4000000 -#define MX53_CS2_64MB_BASE_ADDR 0xF4000000 -#define MX53_CS2_96MB_BASE_ADDR 0xF6000000 -#define MX53_CS3_BASE_ADDR 0xF6000000 - -#define MX53_IO_P2V(x) IMX_IO_P2V(x) -#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x)) - -/* - * defines for SPBA modules - */ -#define MX53_SPBA_SDHC1 0x04 -#define MX53_SPBA_SDHC2 0x08 -#define MX53_SPBA_UART3 0x0C -#define MX53_SPBA_CSPI1 0x10 -#define MX53_SPBA_SSI2 0x14 -#define MX53_SPBA_SDHC3 0x20 -#define MX53_SPBA_SDHC4 0x24 -#define MX53_SPBA_SPDIF 0x28 -#define MX53_SPBA_ATA 0x30 -#define MX53_SPBA_SLIM 0x34 -#define MX53_SPBA_HSI2C 0x38 -#define MX53_SPBA_CTRL 0x3C - -/* - * DMA request assignments - */ -#define MX53_DMA_REQ_SSI3_TX0 47 -#define MX53_DMA_REQ_SSI3_RX0 46 -#define MX53_DMA_REQ_SSI3_TX1 45 -#define MX53_DMA_REQ_SSI3_RX1 44 -#define MX53_DMA_REQ_UART3_TX 43 -#define MX53_DMA_REQ_UART3_RX 42 -#define MX53_DMA_REQ_ESAI_TX 41 -#define MX53_DMA_REQ_ESAI_RX 40 -#define MX53_DMA_REQ_CSPI_TX 39 -#define MX53_DMA_REQ_CSPI_RX 38 -#define MX53_DMA_REQ_ASRC_DMA6 37 -#define MX53_DMA_REQ_ASRC_DMA5 36 -#define MX53_DMA_REQ_ASRC_DMA4 35 -#define MX53_DMA_REQ_ASRC_DMA3 34 -#define MX53_DMA_REQ_ASRC_DMA2 33 -#define MX53_DMA_REQ_ASRC_DMA1 32 -#define MX53_DMA_REQ_EMI_WR 31 -#define MX53_DMA_REQ_EMI_RD 30 -#define MX53_DMA_REQ_SSI1_TX0 29 -#define MX53_DMA_REQ_SSI1_RX0 28 -#define MX53_DMA_REQ_SSI1_TX1 27 -#define MX53_DMA_REQ_SSI1_RX1 26 -#define MX53_DMA_REQ_SSI2_TX0 25 -#define MX53_DMA_REQ_SSI2_RX0 24 -#define MX53_DMA_REQ_SSI2_TX1 23 -#define MX53_DMA_REQ_SSI2_RX1 22 -#define MX53_DMA_REQ_I2C2_SDHC2 21 -#define MX53_DMA_REQ_I2C1_SDHC1 20 -#define MX53_DMA_REQ_UART1_TX 19 -#define MX53_DMA_REQ_UART1_RX 18 -#define MX53_DMA_REQ_UART5_TX 17 -#define MX53_DMA_REQ_UART5_RX 16 -#define MX53_DMA_REQ_SPDIF_TX 15 -#define MX53_DMA_REQ_SPDIF_RX 14 -#define MX53_DMA_REQ_UART2_FIRI_TX 13 -#define MX53_DMA_REQ_UART2_FIRI_RX 12 -#define MX53_DMA_REQ_SDHC4 11 -#define MX53_DMA_REQ_I2C3_SDHC3 10 -#define MX53_DMA_REQ_CSPI2_TX 9 -#define MX53_DMA_REQ_CSPI2_RX 8 -#define MX53_DMA_REQ_CSPI1_TX 7 -#define MX53_DMA_REQ_CSPI1_RX 6 -#define MX53_DMA_REQ_IPU 5 -#define MX53_DMA_REQ_ATA_TX_END 4 -#define MX53_DMA_REQ_ATA_UART4_TX 3 -#define MX53_DMA_REQ_ATA_UART4_RX 2 -#define MX53_DMA_REQ_GPC 1 -#define MX53_DMA_REQ_VPU 0 - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) -#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) -#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) -#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) -#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) -#define MX53_INT_DAP (NR_IRQS_LEGACY + 5) -#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) -#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) -#define MX53_INT_NFC (NR_IRQS_LEGACY + 8) -#define MX53_INT_VPU (NR_IRQS_LEGACY + 9) -#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) -#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) -#define MX53_INT_GPU (NR_IRQS_LEGACY + 12) -#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) -#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) -#define MX53_INT_EMI (NR_IRQS_LEGACY + 15) -#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) -#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) -#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) -#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) -#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) -#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) -#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) -#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) -#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) -#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) -#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) -#define MX53_INT_CSU (NR_IRQS_LEGACY + 27) -#define MX53_INT_SATA (NR_IRQS_LEGACY + 28) -#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) -#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) -#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) -#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) -#define MX53_INT_RTC (NR_IRQS_LEGACY + 34) -#define MX53_INT_PTP (NR_IRQS_LEGACY + 35) -#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) -#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) -#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) -#define MX53_INT_GPT (NR_IRQS_LEGACY + 39) -#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) -#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) -#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) -#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) -#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) -#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) -#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) -#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) -#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) -#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) -#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) -#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) -#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) -#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) -#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) -#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) -#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) -#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) -#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) -#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) -#define MX53_INT_KPP (NR_IRQS_LEGACY + 60) -#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) -#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) -#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) -#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) -#define MX53_INT_MLB (NR_IRQS_LEGACY + 65) -#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) -#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) -#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) -#define MX53_INT_IIM (NR_IRQS_LEGACY + 69) -#define MX53_INT_ATA (NR_IRQS_LEGACY + 70) -#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) -#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) -#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) -#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) -#define MX53_INT_SRC (NR_IRQS_LEGACY + 75) -#define MX53_INT_NM (NR_IRQS_LEGACY + 76) -#define MX53_INT_PMU (NR_IRQS_LEGACY + 77) -#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) -#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) -#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) -#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) -#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) -#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) -#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) -#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) -#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) -#define MX53_INT_FEC (NR_IRQS_LEGACY + 87) -#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) -#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) -#define MX53_INT_SJC (NR_IRQS_LEGACY + 90) -#define MX53_INT_TVE (NR_IRQS_LEGACY + 92) -#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) -#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) -#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) -#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) -#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) -#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) -#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) -#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) -#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) -#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) -#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) -#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) -#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) -#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) -#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) -#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) - -#endif /* ifndef __MACH_MX53_H__ */ diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 8629e5be7ecd..fe2d0f5abfcc 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -1,160 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc. * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. */ #ifndef __ASM_ARCH_MXC_H__ #define __ASM_ARCH_MXC_H__ #include <linux/types.h> +#include <soc/imx/cpu.h> #ifndef __ASM_ARCH_MXC_HARDWARE_H__ #error "Do not include directly." #endif -#define MXC_CPU_MX1 1 -#define MXC_CPU_MX21 21 -#define MXC_CPU_MX25 25 -#define MXC_CPU_MX27 27 -#define MXC_CPU_MX31 31 -#define MXC_CPU_MX35 35 -#define MXC_CPU_MX51 51 -#define MXC_CPU_MX53 53 -#define MXC_CPU_IMX6DL 0x61 -#define MXC_CPU_IMX6Q 0x63 - -#define IMX_CHIP_REVISION_1_0 0x10 -#define IMX_CHIP_REVISION_1_1 0x11 -#define IMX_CHIP_REVISION_1_2 0x12 -#define IMX_CHIP_REVISION_1_3 0x13 -#define IMX_CHIP_REVISION_2_0 0x20 -#define IMX_CHIP_REVISION_2_1 0x21 -#define IMX_CHIP_REVISION_2_2 0x22 -#define IMX_CHIP_REVISION_2_3 0x23 -#define IMX_CHIP_REVISION_3_0 0x30 -#define IMX_CHIP_REVISION_3_1 0x31 -#define IMX_CHIP_REVISION_3_2 0x32 -#define IMX_CHIP_REVISION_3_3 0x33 -#define IMX_CHIP_REVISION_UNKNOWN 0xff +#define IMX_DDR_TYPE_LPDDR2 1 #ifndef __ASSEMBLY__ -extern unsigned int __mxc_cpu_type; -#endif - -#ifdef CONFIG_SOC_IMX1 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX1 -# endif -# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) -#else -# define cpu_is_mx1() (0) -#endif - -#ifdef CONFIG_SOC_IMX21 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX21 -# endif -# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) -#else -# define cpu_is_mx21() (0) -#endif -#ifdef CONFIG_SOC_IMX25 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX25 -# endif -# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25) +#ifdef CONFIG_SOC_IMX6SL +static inline bool cpu_is_imx6sl(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6SL; +} #else -# define cpu_is_mx25() (0) +static inline bool cpu_is_imx6sl(void) +{ + return false; +} #endif -#ifdef CONFIG_SOC_IMX27 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX27 -# endif -# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) -#else -# define cpu_is_mx27() (0) -#endif +static inline bool cpu_is_imx6dl(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6DL; +} -#ifdef CONFIG_SOC_IMX31 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX31 -# endif -# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) -#else -# define cpu_is_mx31() (0) -#endif +static inline bool cpu_is_imx6sx(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6SX; +} -#ifdef CONFIG_SOC_IMX35 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX35 -# endif -# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) -#else -# define cpu_is_mx35() (0) -#endif +static inline bool cpu_is_imx6ul(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6UL; +} -#ifdef CONFIG_SOC_IMX51 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX51 -# endif -# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) -#else -# define cpu_is_mx51() (0) -#endif +static inline bool cpu_is_imx6ull(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6ULL; +} -#ifdef CONFIG_SOC_IMX53 -# ifdef mxc_cpu_type -# undef mxc_cpu_type -# define mxc_cpu_type __mxc_cpu_type -# else -# define mxc_cpu_type MXC_CPU_MX53 -# endif -# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53) -#else -# define cpu_is_mx53() (0) -#endif +static inline bool cpu_is_imx6ulz(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX6ULZ; +} -#ifndef __ASSEMBLY__ -static inline bool cpu_is_imx6dl(void) +static inline bool cpu_is_imx6sll(void) { - return __mxc_cpu_type == MXC_CPU_IMX6DL; + return __mxc_cpu_type == MXC_CPU_IMX6SLL; } static inline bool cpu_is_imx6q(void) @@ -162,6 +65,11 @@ static inline bool cpu_is_imx6q(void) return __mxc_cpu_type == MXC_CPU_IMX6Q; } +static inline bool cpu_is_imx7d(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX7D; +} + struct cpu_op { u32 cpu_rate; }; @@ -171,7 +79,9 @@ int tzic_enable_wake(void); extern struct cpu_op *(*get_cpu_op)(int *op); #endif -#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) -#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) +#define imx_readl readl_relaxed +#define imx_readw readw_relaxed +#define imx_writel writel_relaxed +#define imx_writew writew_relaxed #endif /* __ASM_ARCH_MXC_H__ */ diff --git a/arch/arm/mach-imx/pcm037.h b/arch/arm/mach-imx/pcm037.h deleted file mode 100644 index 7d167690e17d..000000000000 --- a/arch/arm/mach-imx/pcm037.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef __PCM037_H__ -#define __PCM037_H__ - -enum pcm037_board_variant { - PCM037_PCM970, - PCM037_EET, -}; - -extern enum pcm037_board_variant pcm037_variant(void); - -#ifdef CONFIG_MACH_PCM037_EET -int pcm037_eet_init_devices(void); -#else -static inline int pcm037_eet_init_devices(void) { return 0; } -#endif - -#endif diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c deleted file mode 100644 index 51c608234089..000000000000 --- a/arch/arm/mach-imx/pcm970-baseboard.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/irq.h> -#include <linux/platform_device.h> -#include <linux/can/platform/sja1000.h> - -#include <asm/mach/arch.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -static const int pcm970_pins[] __initconst = { - /* SDHC */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* - * it seems the data line misses a pullup, so we must enable - * the internal pullup as a local workaround - */ - PD17_PF_I2C_DATA | GPIO_PUEN, - PD18_PF_I2C_CLK, - /* Camera */ - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, -}; - -static int pcm970_sdhc2_get_ro(struct device *dev) -{ - return gpio_get_value(GPIO_PORTC + 28); -} - -static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) -{ - int ret; - - ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq, - IRQF_TRIGGER_FALLING, "imx-mmc-detect", data); - if (ret) - return ret; - - ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); - if (ret) { - free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data); - return ret; - } - - gpio_direction_input(GPIO_PORTC + 28); - - return 0; -} - -static void pcm970_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data); - gpio_free(GPIO_PORTC + 28); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .get_ro = pcm970_sdhc2_get_ro, - .init = pcm970_sdhc2_init, - .exit = pcm970_sdhc2_exit, -}; - -static struct imx_fb_videomode pcm970_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 7, - .left_margin = 5, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - }, - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock not inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pcr = 0xF00080C0, - .bpp = 16, - }, { - .mode = { - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - }, - /* - * - HSYNC active low (1 << 22) - * - VSYNC active low (1 << 23) - * - clk notenabled while idle - * - clock not inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19), - .bpp = 32, - }, -}; - -static const struct imx_fb_platform_data pcm038_fb_data __initconst = { - .mode = pcm970_modes, - .num_modes = ARRAY_SIZE(pcm970_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static struct resource pcm970_sja1000_resources[] = { - { - .start = MX27_CS4_BASE_ADDR, - .end = MX27_CS4_BASE_ADDR + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct sja1000_platform_data pcm970_sja1000_platform_data = { - .osc_freq = 16000000, - .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, - .cdr = CDR_CBP, -}; - -static struct platform_device pcm970_sja1000 = { - .name = "sja1000_platform", - .dev = { - .platform_data = &pcm970_sja1000_platform_data, - }, - .resource = pcm970_sja1000_resources, - .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), -}; - -/* - * system init for baseboard usage. Will be called by pcm038 init. - * - * Add platform devices present on this baseboard and init - * them from CPU side as far as required to use them later on - */ -void __init pcm970_baseboard_init(void) -{ - mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), - "PCM970"); - - imx27_add_imx_fb(&pcm038_fb_data); - mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); - imx27_add_mxc_mmc(1, &sdhc_pdata); - pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19)); - pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19)); - platform_device_register(&pcm970_sja1000); -} diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index c6e1ab544882..972639038be5 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -1,17 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/init.h> +#include <linux/of_address.h> +#include <linux/of.h> #include <linux/smp.h> + #include <asm/cacheflush.h> #include <asm/page.h> #include <asm/smp_scu.h> @@ -20,8 +17,6 @@ #include "common.h" #include "hardware.h" -#define SCU_STANDBY_ENABLE (1 << 5) - u32 g_diag_reg; static void __iomem *scu_base; @@ -45,15 +40,7 @@ void __init imx_scu_map_io(void) scu_base = IMX_IO_ADDRESS(base); } -void imx_scu_standby_enable(void) -{ - u32 val = readl_relaxed(scu_base); - - val |= SCU_STANDBY_ENABLE; - writel_relaxed(val, scu_base); -} - -static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) { imx_set_cpu_jump(cpu, v7_secondary_startup); imx_enable_cpu(cpu, true); @@ -92,11 +79,10 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) * secondary cores when booting them. */ asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc"); - __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg)); - outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1)); + sync_cache_w(&g_diag_reg); } -struct smp_operations imx_smp_ops __initdata = { +const struct smp_operations imx_smp_ops __initconst = { .smp_init_cpus = imx_smp_init_cpus, .smp_prepare_cpus = imx_smp_prepare_cpus, .smp_boot_secondary = imx_boot_secondary, @@ -105,3 +91,60 @@ struct smp_operations imx_smp_ops __initdata = { .cpu_kill = imx_cpu_kill, #endif }; + +/* + * Initialise the CPU possible map early - this describes the CPUs + * which may be present or become present in the system. + */ +static void __init imx7_smp_init_cpus(void) +{ + struct device_node *np; + int i, ncores = 0; + + /* The iMX7D SCU does not report core count, get it from DT */ + for_each_of_cpu_node(np) + ncores++; + + for (i = ncores; i < NR_CPUS; i++) + set_cpu_possible(i, false); +} + +const struct smp_operations imx7_smp_ops __initconst = { + .smp_init_cpus = imx7_smp_init_cpus, + .smp_boot_secondary = imx_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = imx_cpu_die, + .cpu_kill = imx_cpu_kill, +#endif +}; + +#define DCFG_CCSR_SCRATCHRW1 0x200 + +static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + return 0; +} + +static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np; + void __iomem *dcfg_base; + unsigned long paddr; + + np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg"); + dcfg_base = of_iomap(np, 0); + of_node_put(np); + BUG_ON(!dcfg_base); + + paddr = __pa_symbol(secondary_startup); + writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1); + + iounmap(dcfg_base); +} + +const struct smp_operations ls1021a_smp_ops __initconst = { + .smp_prepare_cpus = ls1021a_smp_prepare_cpus, + .smp_boot_secondary = ls1021a_boot_secondary, +}; diff --git a/arch/arm/mach-imx/pm-imx25.c b/arch/arm/mach-imx/pm-imx25.c new file mode 100644 index 000000000000..0c574e8607fd --- /dev/null +++ b/arch/arm/mach-imx/pm-imx25.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 NXP Semiconductors + */ + +#include <linux/kernel.h> +#include <linux/suspend.h> +#include <linux/io.h> +#include "common.h" + +static int imx25_suspend_enter(suspend_state_t state) +{ + if (!IS_ENABLED(CONFIG_PM)) + return 0; + + switch (state) { + case PM_SUSPEND_MEM: + cpu_do_idle(); + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct platform_suspend_ops imx25_suspend_ops = { + .enter = imx25_suspend_enter, + .valid = suspend_valid_only_mem, +}; + +void __init imx25_pm_init(void) +{ + suspend_set_ops(&imx25_suspend_ops); +} diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index 56d02d064fbf..237e8aa9fe83 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c @@ -7,21 +7,30 @@ * modify it under the terms of the GNU General Public License. */ +#include <linux/of_address.h> #include <linux/kernel.h> #include <linux/suspend.h> #include <linux/io.h> +#include "common.h" #include "hardware.h" static int mx27_suspend_enter(suspend_state_t state) { + void __iomem *ccm_base; + struct device_node *np; u32 cscr; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); + ccm_base = of_iomap(np, 0); + BUG_ON(!ccm_base); + switch (state) { case PM_SUSPEND_MEM: /* Clear MPEN and SPEN to disable MPLL/SPLL */ - cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + cscr = imx_readl(ccm_base); cscr &= 0xFFFFFFFC; - __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + imx_writel(cscr, ccm_base); /* Executes WFI */ cpu_do_idle(); break; @@ -37,13 +46,7 @@ static const struct platform_suspend_ops mx27_suspend_ops = { .valid = suspend_valid_only_mem, }; -static int __init mx27_pm_init(void) +void __init imx27_pm_init(void) { - if (!cpu_is_mx27()) - return 0; - suspend_set_ops(&mx27_suspend_ops); - return 0; } - -device_initcall(mx27_pm_init); diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c deleted file mode 100644 index 6a07006ff0f4..000000000000 --- a/arch/arm/mach-imx/pm-imx3.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/io.h> - -#include "common.h" -#include "crmregs-imx3.h" -#include "devices/devices-common.h" -#include "hardware.h" - -/* - * Set cpu low power mode before WFI instruction. This function is called - * mx3 because it can be used for mx31 and mx35. - * Currently only WAIT_MODE is supported. - */ -void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode) -{ - int reg = __raw_readl(mx3_ccm_base + MXC_CCM_CCMR); - reg &= ~MXC_CCM_CCMR_LPM_MASK; - - switch (mode) { - case MX3_WAIT: - if (cpu_is_mx35()) - reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; - __raw_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); - break; - default: - pr_err("Unknown cpu power mode: %d\n", mode); - return; - } -} diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c index 82e79c658eb2..6f0de45b71e9 100644 --- a/arch/arm/mach-imx/pm-imx5.c +++ b/arch/arm/mach-imx/pm-imx5.c @@ -1,37 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/suspend.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/err.h> #include <linux/export.h> + +#include <linux/genalloc.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> + #include <asm/cacheflush.h> +#include <asm/fncpy.h> #include <asm/system_misc.h> #include <asm/tlbflush.h> #include "common.h" #include "cpuidle.h" -#include "crm-regs-imx5.h" #include "hardware.h" +#define MXC_CCM_CLPCR 0x54 +#define MXC_CCM_CLPCR_LPM_OFFSET 0 +#define MXC_CCM_CLPCR_LPM_MASK 0x3 +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) + +#define MXC_CORTEXA8_PLAT_LPC 0xc +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +#define MXC_SRPG_NEON_SRPGCR 0x280 +#define MXC_SRPG_ARM_SRPGCR 0x2a0 +#define MXC_SRPG_EMPGC0_SRPGCR 0x2c0 +#define MXC_SRPG_EMPGC1_SRPGCR 0x2d0 + +#define MXC_SRPGCR_PCR 1 + /* * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit. * This is also the lowest power state possible without affecting * non-cpu parts of the system. For these reasons, imx5 should default * to always using this state for cpu idling. The PM_SUSPEND_STANDBY also - * uses this state and needs to take no action when registers remain confgiured + * uses this state and needs to take no action when registers remain configured * for this state. */ #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF +struct imx5_suspend_io_state { + u32 offset; + u32 clear; + u32 set; + u32 saved_value; +}; + +struct imx5_pm_data { + phys_addr_t ccm_addr; + phys_addr_t cortex_addr; + phys_addr_t gpc_addr; + phys_addr_t m4if_addr; + phys_addr_t iomuxc_addr; + void (*suspend_asm)(void __iomem *ocram_vbase); + const u32 *suspend_asm_sz; + const struct imx5_suspend_io_state *suspend_io_config; + int suspend_io_count; +}; + +static const struct imx5_suspend_io_state imx53_suspend_io_config[] = { +#define MX53_DSE_HIGHZ_MASK (0x7 << 19) + {.offset = 0x584, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM0 */ + {.offset = 0x594, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM1 */ + {.offset = 0x560, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM2 */ + {.offset = 0x554, .clear = MX53_DSE_HIGHZ_MASK}, /* DQM3 */ + {.offset = 0x574, .clear = MX53_DSE_HIGHZ_MASK}, /* CAS */ + {.offset = 0x588, .clear = MX53_DSE_HIGHZ_MASK}, /* RAS */ + {.offset = 0x578, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_0 */ + {.offset = 0x570, .clear = MX53_DSE_HIGHZ_MASK}, /* SDCLK_1 */ + + {.offset = 0x580, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT0 */ + {.offset = 0x564, .clear = MX53_DSE_HIGHZ_MASK}, /* SDODT1 */ + {.offset = 0x57c, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS0 */ + {.offset = 0x590, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS1 */ + {.offset = 0x568, .clear = MX53_DSE_HIGHZ_MASK}, /* SDQS2 */ + {.offset = 0x558, .clear = MX53_DSE_HIGHZ_MASK}, /* SDSQ3 */ + {.offset = 0x6f0, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_ADDS */ + {.offset = 0x718, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_BODS */ + {.offset = 0x71c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B1DS */ + {.offset = 0x728, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B2DS */ + {.offset = 0x72c, .clear = MX53_DSE_HIGHZ_MASK}, /* GRP_B3DS */ + + /* Controls the CKE signal which is required to leave self refresh */ + {.offset = 0x720, .clear = MX53_DSE_HIGHZ_MASK, .set = 1 << 19}, /* CTLDS */ +}; + +static const struct imx5_pm_data imx51_pm_data __initconst = { + .ccm_addr = 0x73fd4000, + .cortex_addr = 0x83fa0000, + .gpc_addr = 0x73fd8000, +}; + +static const struct imx5_pm_data imx53_pm_data __initconst = { + .ccm_addr = 0x53fd4000, + .cortex_addr = 0x63fa0000, + .gpc_addr = 0x53fd8000, + .m4if_addr = 0x63fd8000, + .iomuxc_addr = 0x53fa8000, + .suspend_asm = &imx53_suspend, + .suspend_asm_sz = &imx53_suspend_sz, + .suspend_io_config = imx53_suspend_io_config, + .suspend_io_count = ARRAY_SIZE(imx53_suspend_io_config), +}; + +#define MX5_MAX_SUSPEND_IOSTATE ARRAY_SIZE(imx53_suspend_io_config) + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx53.S), if this struct + * definition is changed, the offset definition in that file + * must be also changed accordingly otherwise, the suspend to ocram + * function will be broken! + */ +struct imx5_cpu_suspend_info { + void __iomem *m4if_base; + void __iomem *iomuxc_base; + u32 io_count; + struct imx5_suspend_io_state io_state[MX5_MAX_SUSPEND_IOSTATE]; +} __aligned(8); + +static void __iomem *ccm_base; +static void __iomem *cortex_base; +static void __iomem *gpc_base; +static void __iomem *suspend_ocram_base; +static void (*imx5_suspend_in_ocram_fn)(void __iomem *ocram_vbase); + /* * set cpu low power mode before WFI instruction. This function is called * mx5 because it can be used for mx51, and mx53. @@ -43,12 +148,16 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) int stop_mode = 0; /* always allow platform to issue a deep sleep mode request */ - plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & ~(MXC_CORTEXA8_PLAT_LPC_DSM); - ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); - arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & + ~(MXC_CCM_CLPCR_LPM_MASK); + arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & + ~(MXC_SRPGCR_PCR); + empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & + ~(MXC_SRPGCR_PCR); + empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & + ~(MXC_SRPGCR_PCR); switch (mode) { case WAIT_CLOCKED: @@ -82,17 +191,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) return; } - __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); - __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); - __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); - __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + imx_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); + imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); + imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); + imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); if (stop_mode) { empgc0 |= MXC_SRPGCR_PCR; empgc1 |= MXC_SRPGCR_PCR; - __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); + imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); + imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); } } @@ -114,10 +223,17 @@ static int mx5_suspend_enter(suspend_state_t state) flush_cache_all(); /*clear the EMPGC0/1 bits */ - __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); + imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); + + if (imx5_suspend_in_ocram_fn) + imx5_suspend_in_ocram_fn(suspend_ocram_base); + else + cpu_do_idle(); + + } else { + cpu_do_idle(); } - cpu_do_idle(); /* return registers to default idle state */ mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); @@ -149,7 +265,114 @@ static void imx5_pm_idle(void) imx5_cpu_do_idle(); } -static int __init imx5_pm_common_init(void) +static int __init imx_suspend_alloc_ocram( + size_t size, + void __iomem **virt_out, + phys_addr_t *phys_out) +{ + struct device_node *node; + struct platform_device *pdev; + struct gen_pool *ocram_pool; + unsigned long ocram_base; + void __iomem *virt; + phys_addr_t phys; + int ret = 0; + + /* Copied from imx6: TODO factorize */ + node = of_find_compatible_node(NULL, NULL, "mmio-sram"); + if (!node) { + pr_warn("%s: failed to find ocram node!\n", __func__); + return -ENODEV; + } + + pdev = of_find_device_by_node(node); + if (!pdev) { + pr_warn("%s: failed to find ocram device!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_pool = gen_pool_get(&pdev->dev, NULL); + if (!ocram_pool) { + pr_warn("%s: ocram pool unavailable!\n", __func__); + ret = -ENODEV; + goto put_device; + } + + ocram_base = gen_pool_alloc(ocram_pool, size); + if (!ocram_base) { + pr_warn("%s: unable to alloc ocram!\n", __func__); + ret = -ENOMEM; + goto put_device; + } + + phys = gen_pool_virt_to_phys(ocram_pool, ocram_base); + virt = __arm_ioremap_exec(phys, size, false); + if (phys_out) + *phys_out = phys; + if (virt_out) + *virt_out = virt; + +put_device: + put_device(&pdev->dev); +put_node: + of_node_put(node); + + return ret; +} + +static int __init imx5_suspend_init(const struct imx5_pm_data *soc_data) +{ + struct imx5_cpu_suspend_info *suspend_info; + int ret; + /* Need this to avoid compile error due to const typeof in fncpy.h */ + void (*suspend_asm)(void __iomem *) = soc_data->suspend_asm; + + if (!suspend_asm) + return 0; + + if (!soc_data->suspend_asm_sz || !*soc_data->suspend_asm_sz) + return -EINVAL; + + ret = imx_suspend_alloc_ocram( + *soc_data->suspend_asm_sz + sizeof(*suspend_info), + &suspend_ocram_base, NULL); + if (ret) + return ret; + + suspend_info = suspend_ocram_base; + + suspend_info->io_count = soc_data->suspend_io_count; + memcpy(suspend_info->io_state, soc_data->suspend_io_config, + sizeof(*suspend_info->io_state) * soc_data->suspend_io_count); + + suspend_info->m4if_base = ioremap(soc_data->m4if_addr, SZ_16K); + if (!suspend_info->m4if_base) { + ret = -ENOMEM; + goto failed_map_m4if; + } + + suspend_info->iomuxc_base = ioremap(soc_data->iomuxc_addr, SZ_16K); + if (!suspend_info->iomuxc_base) { + ret = -ENOMEM; + goto failed_map_iomuxc; + } + + imx5_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*suspend_info), + suspend_asm, + *soc_data->suspend_asm_sz); + + return 0; + +failed_map_iomuxc: + iounmap(suspend_info->m4if_base); + +failed_map_m4if: + return ret; +} + +static int __init imx5_pm_common_init(const struct imx5_pm_data *data) { int ret; struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); @@ -163,20 +386,36 @@ static int __init imx5_pm_common_init(void) arm_pm_idle = imx5_pm_idle; + ccm_base = ioremap(data->ccm_addr, SZ_16K); + cortex_base = ioremap(data->cortex_addr, SZ_16K); + gpc_base = ioremap(data->gpc_addr, SZ_16K); + WARN_ON(!ccm_base || !cortex_base || !gpc_base); + /* Set the registers to the default cpu idle state. */ mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE); - return imx5_cpuidle_init(); + ret = imx5_cpuidle_init(); + if (ret) + pr_warn("%s: cpuidle init failed %d\n", __func__, ret); + + ret = imx5_suspend_init(data); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + + suspend_set_ops(&mx5_suspend_ops); + + return 0; } void __init imx51_pm_init(void) { - int ret = imx5_pm_common_init(); - if (!ret) - suspend_set_ops(&mx5_suspend_ops); + if (IS_ENABLED(CONFIG_SOC_IMX51)) + imx5_pm_common_init(&imx51_pm_data); } void __init imx53_pm_init(void) { - imx5_pm_common_init(); + if (IS_ENABLED(CONFIG_SOC_IMX53)) + imx5_pm_common_init(&imx53_pm_data); } diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c new file mode 100644 index 000000000000..a671ca498f88 --- /dev/null +++ b/arch/arm/mach-imx/pm-imx6.c @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2011-2014 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + */ + +#include <linux/clk/imx.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/irq.h> +#include <linux/genalloc.h> +#include <linux/irqchip/arm-gic.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/suspend.h> +#include <asm/cacheflush.h> +#include <asm/fncpy.h> +#include <asm/proc-fns.h> +#include <asm/suspend.h> +#include <asm/tlb.h> + +#include "common.h" +#include "hardware.h" + +#define CCR 0x0 +#define BM_CCR_WB_COUNT (0x7 << 16) +#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21) +#define BM_CCR_RBC_EN (0x1 << 27) + +#define CLPCR 0x54 +#define BP_CLPCR_LPM 0 +#define BM_CLPCR_LPM (0x3 << 0) +#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2) +#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define BM_CLPCR_SBYOS (0x1 << 6) +#define BM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define BM_CLPCR_VSTBY (0x1 << 8) +#define BP_CLPCR_STBY_COUNT 9 +#define BM_CLPCR_STBY_COUNT (0x3 << 9) +#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16) +#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17) +#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19) +#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21) +#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22) +#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23) +#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24) +#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25) +#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26) +#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27) + +#define CGPR 0x64 +#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17) + +#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000 +#define MX6_MAX_MMDC_IO_NUM 33 + +static void __iomem *ccm_base; +static void __iomem *suspend_ocram_base; +static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase); + +/* + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx6_suspend code + * PM_INFO structure(imx6_cpu_pm_info) + * ======================== low address ======================= + */ + +struct imx6_pm_base { + phys_addr_t pbase; + void __iomem *vbase; +}; + +struct imx6_pm_socdata { + u32 ddr_type; + const char *mmdc_compat; + const char *src_compat; + const char *iomuxc_compat; + const char *gpc_compat; + const char *pl310_compat; + const u32 mmdc_io_num; + const u32 *mmdc_io_offset; +}; + +static const u32 imx6q_mmdc_io_offset[] __initconst = { + 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */ + 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */ + 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */ + 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */ + 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */ + 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, /* GPR_ADDS */ +}; + +static const u32 imx6dl_mmdc_io_offset[] __initconst = { + 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */ + 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */ + 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */ + 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */ + 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */ + 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */ + 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */ + 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x74c, /* GPR_ADDS */ +}; + +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ +}; + +static const u32 imx6sll_mmdc_io_offset[] __initconst = { + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ +}; + +static const u32 imx6sx_mmdc_io_offset[] __initconst = { + 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */ + 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */ +}; + +static const u32 imx6ul_mmdc_io_offset[] __initconst = { + 0x244, 0x248, 0x24c, 0x250, /* DQM0, DQM1, RAS, CAS */ + 0x27c, 0x498, 0x4a4, 0x490, /* SDCLK0, GPR_B0DS-B1DS, GPR_ADDS */ + 0x280, 0x284, 0x260, 0x264, /* SDQS0~1, SODT0, SODT1 */ + 0x494, 0x4b0, /* MODE_CTL, MODE, */ +}; + +static const struct imx6_pm_socdata imx6q_pm_data __initconst = { + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6q-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .pl310_compat = "arm,pl310-cache", + .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset), + .mmdc_io_offset = imx6q_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { + .mmdc_compat = "fsl,imx6q-mmdc", + .src_compat = "fsl,imx6q-src", + .iomuxc_compat = "fsl,imx6dl-iomuxc", + .gpc_compat = "fsl,imx6q-gpc", + .pl310_compat = "arm,pl310-cache", + .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset), + .mmdc_io_offset = imx6dl_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sl-mmdc", + .src_compat = "fsl,imx6sl-src", + .iomuxc_compat = "fsl,imx6sl-iomuxc", + .gpc_compat = "fsl,imx6sl-gpc", + .pl310_compat = "arm,pl310-cache", + .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), + .mmdc_io_offset = imx6sl_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6sll_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sll-mmdc", + .src_compat = "fsl,imx6sll-src", + .iomuxc_compat = "fsl,imx6sll-iomuxc", + .gpc_compat = "fsl,imx6sll-gpc", + .pl310_compat = "arm,pl310-cache", + .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset), + .mmdc_io_offset = imx6sll_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { + .mmdc_compat = "fsl,imx6sx-mmdc", + .src_compat = "fsl,imx6sx-src", + .iomuxc_compat = "fsl,imx6sx-iomuxc", + .gpc_compat = "fsl,imx6sx-gpc", + .pl310_compat = "arm,pl310-cache", + .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset), + .mmdc_io_offset = imx6sx_mmdc_io_offset, +}; + +static const struct imx6_pm_socdata imx6ul_pm_data __initconst = { + .mmdc_compat = "fsl,imx6ul-mmdc", + .src_compat = "fsl,imx6ul-src", + .iomuxc_compat = "fsl,imx6ul-iomuxc", + .gpc_compat = "fsl,imx6ul-gpc", + .pl310_compat = NULL, + .mmdc_io_num = ARRAY_SIZE(imx6ul_mmdc_io_offset), + .mmdc_io_offset = imx6ul_mmdc_io_offset, +}; + +/* + * This structure is for passing necessary data for low level ocram + * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct + * definition is changed, the offset definition in + * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly, + * otherwise, the suspend to ocram function will be broken! + */ +struct imx6_cpu_pm_info { + phys_addr_t pbase; /* The physical address of pm_info. */ + phys_addr_t resume_addr; /* The physical resume address for asm code */ + u32 ddr_type; + u32 pm_info_size; /* Size of pm_info. */ + struct imx6_pm_base mmdc_base; + struct imx6_pm_base src_base; + struct imx6_pm_base iomuxc_base; + struct imx6_pm_base ccm_base; + struct imx6_pm_base gpc_base; + struct imx6_pm_base l2_base; + u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ +} __aligned(8); + +void imx6_set_int_mem_clk_lpm(bool enable) +{ + u32 val = readl_relaxed(ccm_base + CGPR); + + val &= ~BM_CGPR_INT_MEM_CLK_LPM; + if (enable) + val |= BM_CGPR_INT_MEM_CLK_LPM; + writel_relaxed(val, ccm_base + CGPR); +} + +void imx6_enable_rbc(bool enable) +{ + u32 val; + + /* + * need to mask all interrupts in GPC before + * operating RBC configurations + */ + imx_gpc_mask_all(); + + /* configure RBC enable bit */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_EN; + val |= enable ? BM_CCR_RBC_EN : 0; + writel_relaxed(val, ccm_base + CCR); + + /* configure RBC count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_RBC_BYPASS_COUNT; + val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0; + writel(val, ccm_base + CCR); + + /* + * need to delay at least 2 cycles of CKIL(32K) + * due to hardware design requirement, which is + * ~61us, here we use 65us for safe + */ + udelay(65); + + /* restore GPC interrupt mask settings */ + imx_gpc_restore_all(); +} + +static void imx6q_enable_wb(bool enable) +{ + u32 val; + + /* configure well bias enable bit */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_WB_PER_AT_LPM; + val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0; + writel_relaxed(val, ccm_base + CLPCR); + + /* configure well bias count */ + val = readl_relaxed(ccm_base + CCR); + val &= ~BM_CCR_WB_COUNT; + val |= enable ? BM_CCR_WB_COUNT : 0; + writel_relaxed(val, ccm_base + CCR); +} + +int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) +{ + u32 val = readl_relaxed(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + switch (mode) { + case WAIT_CLOCKED: + break; + case WAIT_UNCLOCKED: + val |= 0x1 << BP_CLPCR_LPM; + val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM; + break; + case STOP_POWER_ON: + val |= 0x2 << BP_CLPCR_LPM; + val &= ~BM_CLPCR_VSTBY; + val &= ~BM_CLPCR_SBYOS; + if (cpu_is_imx6sl()) + val |= BM_CLPCR_BYPASS_PMIC_READY; + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) + val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + break; + case WAIT_UNCLOCKED_POWER_OFF: + val |= 0x1 << BP_CLPCR_LPM; + val &= ~BM_CLPCR_VSTBY; + val &= ~BM_CLPCR_SBYOS; + break; + case STOP_POWER_OFF: + val |= 0x2 << BP_CLPCR_LPM; + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + if (cpu_is_imx6sl() || cpu_is_imx6sx()) + val |= BM_CLPCR_BYPASS_PMIC_READY; + if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || + cpu_is_imx6ull() || cpu_is_imx6sll() || cpu_is_imx6ulz()) + val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; + else + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + break; + default: + return -EINVAL; + } + + /* + * ERR007265: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #32 (IOMUX) to be always pending + * by setting IOMUX_GPR1_GINT. + * 2) Software should then unmask IRQ #32 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #32 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + * + * Note that IRQ #32 is GIC SPI #0. + */ + if (mode != WAIT_CLOCKED) + imx_gpc_hwirq_unmask(0); + writel_relaxed(val, ccm_base + CLPCR); + if (mode != WAIT_CLOCKED) + imx_gpc_hwirq_mask(0); + + return 0; +} + +static int imx6q_suspend_finish(unsigned long val) +{ + if (!imx6_suspend_in_ocram_fn) { + cpu_do_idle(); + } else { + /* + * call low level suspend function in ocram, + * as we need to float DDR IO. + */ + local_flush_tlb_all(); + /* check if need to flush internal L2 cache */ + if (!((struct imx6_cpu_pm_info *) + suspend_ocram_base)->l2_base.vbase) + flush_cache_all(); + imx6_suspend_in_ocram_fn(suspend_ocram_base); + } + + return 0; +} + +static int imx6q_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + imx6_set_lpm(STOP_POWER_ON); + imx6_set_int_mem_clk_lpm(true); + imx_gpc_pre_suspend(false); + if (cpu_is_imx6sl()) + imx6sl_set_wait_clk(true); + /* Zzz ... */ + cpu_do_idle(); + if (cpu_is_imx6sl()) + imx6sl_set_wait_clk(false); + imx_gpc_post_resume(); + imx6_set_lpm(WAIT_CLOCKED); + break; + case PM_SUSPEND_MEM: + imx6_set_lpm(STOP_POWER_OFF); + imx6_set_int_mem_clk_lpm(false); + imx6q_enable_wb(true); + /* + * For suspend into ocram, asm code already take care of + * RBC setting, so we do NOT need to do that here. + */ + if (!imx6_suspend_in_ocram_fn) + imx6_enable_rbc(true); + imx_gpc_pre_suspend(true); + imx_anatop_pre_suspend(); + /* Zzz ... */ + cpu_suspend(0, imx6q_suspend_finish); + if (cpu_is_imx6q() || cpu_is_imx6dl()) + imx_smp_prepare(); + imx_anatop_post_resume(); + imx_gpc_post_resume(); + imx6_enable_rbc(false); + imx6q_enable_wb(false); + imx6_set_int_mem_clk_lpm(true); + imx6_set_lpm(WAIT_CLOCKED); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int imx6q_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM); +} + +static const struct platform_suspend_ops imx6q_pm_ops = { + .enter = imx6q_pm_enter, + .valid = imx6q_pm_valid, +}; + +static int __init imx6_pm_get_base(struct imx6_pm_base *base, + const char *compat) +{ + struct device_node *node; + struct resource res; + int ret = 0; + + node = of_find_compatible_node(NULL, NULL, compat); + if (!node) + return -ENODEV; + + ret = of_address_to_resource(node, 0, &res); + if (ret) + goto put_node; + + base->pbase = res.start; + base->vbase = ioremap(res.start, resource_size(&res)); + if (!base->vbase) + ret = -ENOMEM; + +put_node: + of_node_put(node); + return ret; +} + +static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) +{ + phys_addr_t ocram_pbase; + struct device_node *node; + struct platform_device *pdev; + struct imx6_cpu_pm_info *pm_info; + struct gen_pool *ocram_pool; + unsigned long ocram_base; + int i, ret = 0; + const u32 *mmdc_offset_array; + + suspend_set_ops(&imx6q_pm_ops); + + if (!socdata) { + pr_warn("%s: invalid argument!\n", __func__); + return -EINVAL; + } + + node = of_find_compatible_node(NULL, NULL, "mmio-sram"); + if (!node) { + pr_warn("%s: failed to find ocram node!\n", __func__); + return -ENODEV; + } + + pdev = of_find_device_by_node(node); + if (!pdev) { + pr_warn("%s: failed to find ocram device!\n", __func__); + ret = -ENODEV; + goto put_node; + } + + ocram_pool = gen_pool_get(&pdev->dev, NULL); + if (!ocram_pool) { + pr_warn("%s: ocram pool unavailable!\n", __func__); + ret = -ENODEV; + goto put_device; + } + + ocram_base = gen_pool_alloc(ocram_pool, MX6Q_SUSPEND_OCRAM_SIZE); + if (!ocram_base) { + pr_warn("%s: unable to alloc ocram!\n", __func__); + ret = -ENOMEM; + goto put_device; + } + + ocram_pbase = gen_pool_virt_to_phys(ocram_pool, ocram_base); + + suspend_ocram_base = __arm_ioremap_exec(ocram_pbase, + MX6Q_SUSPEND_OCRAM_SIZE, false); + + memset(suspend_ocram_base, 0, sizeof(*pm_info)); + pm_info = suspend_ocram_base; + pm_info->pbase = ocram_pbase; + pm_info->resume_addr = __pa_symbol(v7_cpu_resume); + pm_info->pm_info_size = sizeof(*pm_info); + + /* + * ccm physical address is not used by asm code currently, + * so get ccm virtual address directly. + */ + pm_info->ccm_base.vbase = ccm_base; + + ret = imx6_pm_get_base(&pm_info->mmdc_base, socdata->mmdc_compat); + if (ret) { + pr_warn("%s: failed to get mmdc base %d!\n", __func__, ret); + goto put_device; + } + + ret = imx6_pm_get_base(&pm_info->src_base, socdata->src_compat); + if (ret) { + pr_warn("%s: failed to get src base %d!\n", __func__, ret); + goto src_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->iomuxc_base, socdata->iomuxc_compat); + if (ret) { + pr_warn("%s: failed to get iomuxc base %d!\n", __func__, ret); + goto iomuxc_map_failed; + } + + ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat); + if (ret) { + pr_warn("%s: failed to get gpc base %d!\n", __func__, ret); + goto gpc_map_failed; + } + + if (socdata->pl310_compat) { + ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat); + if (ret) { + pr_warn("%s: failed to get pl310-cache base %d!\n", + __func__, ret); + goto pl310_cache_map_failed; + } + } + + pm_info->ddr_type = imx_mmdc_get_ddr_type(); + pm_info->mmdc_io_num = socdata->mmdc_io_num; + mmdc_offset_array = socdata->mmdc_io_offset; + + for (i = 0; i < pm_info->mmdc_io_num; i++) { + pm_info->mmdc_io_val[i][0] = + mmdc_offset_array[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(pm_info->iomuxc_base.vbase + + mmdc_offset_array[i]); + } + + imx6_suspend_in_ocram_fn = fncpy( + suspend_ocram_base + sizeof(*pm_info), + &imx6_suspend, + MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info)); + + __arm_iomem_set_ro(suspend_ocram_base, MX6Q_SUSPEND_OCRAM_SIZE); + + goto put_device; + +pl310_cache_map_failed: + iounmap(pm_info->gpc_base.vbase); +gpc_map_failed: + iounmap(pm_info->iomuxc_base.vbase); +iomuxc_map_failed: + iounmap(pm_info->src_base.vbase); +src_map_failed: + iounmap(pm_info->mmdc_base.vbase); +put_device: + put_device(&pdev->dev); +put_node: + of_node_put(node); + + return ret; +} + +static void __init imx6_pm_common_init(const struct imx6_pm_socdata + *socdata) +{ + struct regmap *gpr; + int ret; + + WARN_ON(!ccm_base); + + if (IS_ENABLED(CONFIG_SUSPEND)) { + ret = imx6q_suspend_init(socdata); + if (ret) + pr_warn("%s: No DDR LPM support with suspend %d!\n", + __func__, ret); + } + + /* + * This is for SW workaround step #1 of ERR007265, see comments + * in imx6_set_lpm for details of this errata. + * Force IOMUXC irq pending, so that the interrupt to GPC can be + * used to deassert dsm_request signal when the signal gets + * asserted unexpectedly. + */ + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT, + IMX6Q_GPR1_GINT); +} + +static void imx6_pm_stby_poweroff(void) +{ + gic_cpu_if_down(0); + imx6_set_lpm(STOP_POWER_OFF); + imx6q_suspend_finish(0); + + mdelay(1000); + + pr_emerg("Unable to poweroff system\n"); +} + +static int imx6_pm_stby_poweroff_probe(void) +{ + if (register_platform_power_off(imx6_pm_stby_poweroff)) { + pr_warn("%s: platform power off already claimed!\n", __func__); + return -EBUSY; + } + + return 0; +} + +void __init imx6_pm_ccm_init(const char *ccm_compat) +{ + struct device_node *np; + u32 val; + + np = of_find_compatible_node(NULL, NULL, ccm_compat); + ccm_base = of_iomap(np, 0); + BUG_ON(!ccm_base); + + /* + * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core + * clock being shut down unexpectedly by WAIT mode. + */ + val = readl_relaxed(ccm_base + CLPCR); + val &= ~BM_CLPCR_LPM; + writel_relaxed(val, ccm_base + CLPCR); + + if (of_property_read_bool(np, "fsl,pmic-stby-poweroff")) + imx6_pm_stby_poweroff_probe(); + + of_node_put(np); +} + +void __init imx6q_pm_init(void) +{ + imx6_pm_common_init(&imx6q_pm_data); +} + +void __init imx6dl_pm_init(void) +{ + imx6_pm_common_init(&imx6dl_pm_data); +} + +void __init imx6sl_pm_init(void) +{ + struct regmap *gpr; + + if (cpu_is_imx6sl()) { + imx6_pm_common_init(&imx6sl_pm_data); + } else { + imx6_pm_common_init(&imx6sll_pm_data); + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) + regmap_update_bits(gpr, IOMUXC_GPR5, + IMX6SLL_GPR5_AFCG_X_BYPASS_MASK, 0); + } +} + +void __init imx6sx_pm_init(void) +{ + imx6_pm_common_init(&imx6sx_pm_data); +} + +void __init imx6ul_pm_init(void) +{ + imx6_pm_common_init(&imx6ul_pm_data); +} diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c deleted file mode 100644 index 204942749e21..000000000000 --- a/arch/arm/mach-imx/pm-imx6q.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include <linux/init.h> -#include <linux/io.h> -#include <linux/of.h> -#include <linux/suspend.h> -#include <asm/cacheflush.h> -#include <asm/proc-fns.h> -#include <asm/suspend.h> -#include <asm/hardware/cache-l2x0.h> - -#include "common.h" -#include "hardware.h" - -static int imx6q_suspend_finish(unsigned long val) -{ - cpu_do_idle(); - return 0; -} - -static int imx6q_pm_enter(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_MEM: - imx6q_set_lpm(STOP_POWER_OFF); - imx_gpc_pre_suspend(); - imx_anatop_pre_suspend(); - imx_set_cpu_jump(0, v7_cpu_resume); - /* Zzz ... */ - cpu_suspend(0, imx6q_suspend_finish); - imx_smp_prepare(); - imx_anatop_post_resume(); - imx_gpc_post_resume(); - imx6q_set_lpm(WAIT_CLOCKED); - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct platform_suspend_ops imx6q_pm_ops = { - .enter = imx6q_pm_enter, - .valid = suspend_valid_only_mem, -}; - -void __init imx6q_pm_init(void) -{ - suspend_set_ops(&imx6q_pm_ops); -} diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c new file mode 100644 index 000000000000..2e756d8191fa --- /dev/null +++ b/arch/arm/mach-imx/pm-imx7ulp.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Author: Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> + +#include "common.h" + +#define SMC_PMCTRL 0x10 +#define BP_PMCTRL_PSTOPO 16 +#define PSTOPO_PSTOP3 0x3 +#define PSTOPO_PSTOP2 0x2 +#define PSTOPO_PSTOP1 0x1 +#define BP_PMCTRL_RUNM 8 +#define RUNM_RUN 0 +#define BP_PMCTRL_STOPM 0 +#define STOPM_STOP 0 + +#define BM_PMCTRL_PSTOPO (3 << BP_PMCTRL_PSTOPO) +#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM) +#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM) + +static void __iomem *smc1_base; + +int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) +{ + u32 val = readl_relaxed(smc1_base + SMC_PMCTRL); + + /* clear all */ + val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO); + + switch (mode) { + case ULP_PM_RUN: + /* system/bus clock enabled */ + val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO; + break; + case ULP_PM_WAIT: + /* system clock disabled, bus clock enabled */ + val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO; + break; + case ULP_PM_STOP: + /* system/bus clock disabled */ + val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO; + break; + default: + return -EINVAL; + } + + writel_relaxed(val, smc1_base + SMC_PMCTRL); + + return 0; +} + +void __init imx7ulp_pm_init(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1"); + smc1_base = of_iomap(np, 0); + of_node_put(np); + WARN_ON(!smc1_base); + + imx7ulp_set_lpm(ULP_PM_RUN); +} diff --git a/arch/arm/mach-imx/resume-imx6.S b/arch/arm/mach-imx/resume-imx6.S new file mode 100644 index 000000000000..2c0c5c771251 --- /dev/null +++ b/arch/arm/mach-imx/resume-imx6.S @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h> +#include "hardware.h" + +.arch armv7-a + +/* + * The following code must assume it is running from physical address + * where absolute virtual addresses to the data section have to be + * turned into relative ones. + */ + +ENTRY(v7_cpu_resume) + bl v7_invalidate_l1 +#ifdef CONFIG_CACHE_L2X0 + bl l2c310_early_resume +#endif + b cpu_resume +ENDPROC(v7_cpu_resume) diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 10a6b1a8c5ac..59a8e8cc4469 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -1,26 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #include <linux/init.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/platform_device.h> #include <linux/reset-controller.h> #include <linux/smp.h> #include <asm/smp_plat.h> #include "common.h" +#include "hardware.h" #define SRC_SCR 0x000 -#define SRC_GPR1 0x020 +#define SRC_GPR1_V1 0x020 +#define SRC_GPR1_V2 0x074 +#define SRC_GPR1(gpr_v2) ((gpr_v2) ? SRC_GPR1_V2 : SRC_GPR1_V1) #define BP_SRC_SCR_WARM_RESET_ENABLE 0 #define BP_SRC_SCR_SW_GPU_RST 1 #define BP_SRC_SCR_SW_VPU_RST 2 @@ -29,9 +28,18 @@ #define BP_SRC_SCR_SW_IPU2_RST 12 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 +/* below is for i.MX7D */ +#define SRC_A7RCR1 0x008 +#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1 +#define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_CPU_PGC_SW_PDN_REQ 0xfc +#define GPC_PGC_C1 0x840 +#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 static void __iomem *src_base; static DEFINE_SPINLOCK(scr_lock); +static bool gpr_v2; +static void __iomem *gpc_base; static const int sw_reset_bits[5] = { BP_SRC_SCR_SW_GPU_RST, @@ -49,9 +57,6 @@ static int imx_src_reset_module(struct reset_controller_dev *rcdev, int bit; u32 val; - if (!src_base) - return -ENODEV; - if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits)) return -EINVAL; @@ -73,60 +78,88 @@ static int imx_src_reset_module(struct reset_controller_dev *rcdev, return 0; } -static struct reset_control_ops imx_src_ops = { +static const struct reset_control_ops imx_src_ops = { .reset = imx_src_reset_module, }; -static struct reset_controller_dev imx_reset_controller = { - .ops = &imx_src_ops, - .nr_resets = ARRAY_SIZE(sw_reset_bits), -}; +static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) +{ + writel_relaxed(enable, gpc_base + offset); +} + +/* + * The motivation for bringing up the second i.MX7D core inside the kernel + * is that legacy vendor bootloaders usually do not implement PSCI support. + * This is a significant blocker for systems in the field that are running old + * bootloader versions to upgrade to a modern mainline kernel version, as only + * one CPU of the i.MX7D would be brought up. + * Bring up the second i.MX7D core inside the kernel to make the migration + * path to mainline kernel easier for the existing iMX7D users. + */ +void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn) +{ + u32 reg = pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ; + u32 val, pup; + int ret; + + imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + val = readl_relaxed(gpc_base + reg); + val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + reg); + + ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup, + !(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7), + 5, 1000000); + if (ret < 0) { + pr_err("i.MX7D: CORE1_A7 power up timeout\n"); + val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + writel_relaxed(val, gpc_base + reg); + } + + imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); +} void imx_enable_cpu(int cpu, bool enable) { u32 mask, val; cpu = cpu_logical_map(cpu); - mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); - val = enable ? val | mask : val & ~mask; - writel_relaxed(val, src_base + SRC_SCR); + if (gpr_v2) { + if (enable) + imx_gpcv2_set_core1_pdn_pup_by_software(false); + + mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_A7RCR1); + val = enable ? val | mask : val & ~mask; + writel_relaxed(val, src_base + SRC_A7RCR1); + } else { + mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1); + val = readl_relaxed(src_base + SRC_SCR); + val = enable ? val | mask : val & ~mask; + val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1); + writel_relaxed(val, src_base + SRC_SCR); + } spin_unlock(&scr_lock); } void imx_set_cpu_jump(int cpu, void *jump_addr) { cpu = cpu_logical_map(cpu); - writel_relaxed(virt_to_phys(jump_addr), - src_base + SRC_GPR1 + cpu * 8); + writel_relaxed(__pa_symbol(jump_addr), + src_base + SRC_GPR1(gpr_v2) + cpu * 8); } u32 imx_get_cpu_arg(int cpu) { cpu = cpu_logical_map(cpu); - return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); + return readl_relaxed(src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); } void imx_set_cpu_arg(int cpu, u32 arg) { cpu = cpu_logical_map(cpu); - writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); -} - -void imx_src_prepare_restart(void) -{ - u32 val; - - /* clear enable bits of secondary cores */ - spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); - val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); - writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); - - /* clear persistent entry register of primary core */ - writel_relaxed(0, src_base + SRC_GPR1); + writel_relaxed(arg, src_base + SRC_GPR1(gpr_v2) + cpu * 8 + 4); } void __init imx_src_init(void) @@ -140,10 +173,6 @@ void __init imx_src_init(void) src_base = of_iomap(np, 0); WARN_ON(!src_base); - imx_reset_controller.of_node = np; - if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) - reset_controller_register(&imx_reset_controller); - /* * force warm reset sources to generate cold reset * for a more reliable restart @@ -154,3 +183,56 @@ void __init imx_src_init(void) writel_relaxed(val, src_base + SRC_SCR); spin_unlock(&scr_lock); } + +void __init imx7_src_init(void) +{ + struct device_node *np; + + gpr_v2 = true; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-src"); + if (!np) + return; + + src_base = of_iomap(np, 0); + if (!src_base) + return; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc"); + if (!np) + return; + + gpc_base = of_iomap(np, 0); + if (!gpc_base) + return; +} + +static const struct of_device_id imx_src_dt_ids[] = { + { .compatible = "fsl,imx51-src" }, + { /* sentinel */ } +}; + +static int imx_src_probe(struct platform_device *pdev) +{ + struct reset_controller_dev *rcdev; + + rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL); + if (!rcdev) + return -ENOMEM; + + rcdev->ops = &imx_src_ops; + rcdev->dev = &pdev->dev; + rcdev->of_node = pdev->dev.of_node; + rcdev->nr_resets = ARRAY_SIZE(sw_reset_bits); + + return devm_reset_controller_register(&pdev->dev, rcdev); +} + +static struct platform_driver imx_src_driver = { + .driver = { + .name = "imx-src", + .of_match_table = imx_src_dt_ids, + }, + .probe = imx_src_probe, +}; +builtin_platform_driver(imx_src_driver); diff --git a/arch/arm/mach-imx/ssi-fiq-ksym.c b/arch/arm/mach-imx/ssi-fiq-ksym.c index 792090f9a032..c1e7c3ac0ba5 100644 --- a/arch/arm/mach-imx/ssi-fiq-ksym.c +++ b/arch/arm/mach-imx/ssi-fiq-ksym.c @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Exported ksyms for the SSI FIQ handler * * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/module.h> diff --git a/arch/arm/mach-imx/ssi-fiq.S b/arch/arm/mach-imx/ssi-fiq.S index a8b93c5f29b5..68d7fdea92ad 100644 --- a/arch/arm/mach-imx/ssi-fiq.S +++ b/arch/arm/mach-imx/ssi-fiq.S @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #include <linux/linkage.h> diff --git a/arch/arm/mach-imx/suspend-imx53.S b/arch/arm/mach-imx/suspend-imx53.S new file mode 100644 index 000000000000..46570ec2fbcf --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx53.S @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. + */ +/* + */ + +#include <linux/linkage.h> + +#define M4IF_MCR0_OFFSET (0x008C) +#define M4IF_MCR0_FDVFS (0x1 << 11) +#define M4IF_MCR0_FDVACK (0x1 << 27) + + .align 3 + +/* + * ==================== low level suspend ==================== + * + * On entry + * r0: pm_info structure address; + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx53_suspend code + * PM_INFO structure(imx5_cpu_suspend_info) + * ======================== low address ======================= + */ + +/* Offsets of members of struct imx5_cpu_suspend_info */ +#define SUSPEND_INFO_MX53_M4IF_V_OFFSET 0x0 +#define SUSPEND_INFO_MX53_IOMUXC_V_OFFSET 0x4 +#define SUSPEND_INFO_MX53_IO_COUNT_OFFSET 0x8 +#define SUSPEND_INFO_MX53_IO_STATE_OFFSET 0xc + +ENTRY(imx53_suspend) + stmfd sp!, {r4,r5,r6,r7} + + /* Save pad config */ + ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET] + cmp r1, #0 + beq skip_pad_conf_1 + + add r2, r0, #SUSPEND_INFO_MX53_IO_STATE_OFFSET + ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET] + +1: + ldr r5, [r2], #12 /* IOMUXC register offset */ + ldr r6, [r3, r5] /* current value */ + str r6, [r2], #4 /* save area */ + subs r1, r1, #1 + bne 1b + +skip_pad_conf_1: + /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */ + ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET] + ldr r2,[r1, #M4IF_MCR0_OFFSET] + orr r2, r2, #M4IF_MCR0_FDVFS + str r2,[r1, #M4IF_MCR0_OFFSET] + + /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */ +wait_sr_ack: + ldr r2,[r1, #M4IF_MCR0_OFFSET] + ands r2, r2, #M4IF_MCR0_FDVACK + beq wait_sr_ack + + /* Set pad config */ + ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET] + cmp r1, #0 + beq skip_pad_conf_2 + + add r2, r0, #SUSPEND_INFO_MX53_IO_STATE_OFFSET + ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET] + +2: + ldr r5, [r2], #4 /* IOMUXC register offset */ + ldr r6, [r2], #4 /* clear */ + ldr r7, [r3, r5] + bic r7, r7, r6 + ldr r6, [r2], #8 /* set */ + orr r7, r7, r6 + str r7, [r3, r5] + subs r1, r1, #1 + bne 2b + +skip_pad_conf_2: + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* Restore pad config */ + ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET] + cmp r1, #0 + beq skip_pad_conf_3 + + add r2, r0, #SUSPEND_INFO_MX53_IO_STATE_OFFSET + ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET] + +3: + ldr r5, [r2], #12 /* IOMUXC register offset */ + ldr r6, [r2], #4 /* saved value */ + str r6, [r3, r5] + subs r1, r1, #1 + bne 3b + +skip_pad_conf_3: + /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */ + ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET] + ldr r2,[r1, #M4IF_MCR0_OFFSET] + bic r2, r2, #M4IF_MCR0_FDVFS + str r2,[r1, #M4IF_MCR0_OFFSET] + + /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */ +wait_ar_ack: + ldr r2,[r1, #M4IF_MCR0_OFFSET] + ands r2, r2, #M4IF_MCR0_FDVACK + bne wait_ar_ack + + /* Restore registers */ + ldmfd sp!, {r4,r5,r6,r7} + mov pc, lr + +ENDPROC(imx53_suspend) + +ENTRY(imx53_suspend_sz) + .word . - imx53_suspend diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S new file mode 100644 index 000000000000..63ccc2d0e920 --- /dev/null +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/asm-offsets.h> +#include <asm/hardware/cache-l2x0.h> +#include "hardware.h" + +.arch armv7-a + +/* + * ==================== low level suspend ==================== + * + * Better to follow below rules to use ARM registers: + * r0: pm_info structure address; + * r1 ~ r4: for saving pm_info members; + * r5 ~ r10: free registers; + * r11: io base address. + * + * suspend ocram space layout: + * ======================== high address ====================== + * . + * . + * . + * ^ + * ^ + * ^ + * imx6_suspend code + * PM_INFO structure(imx6_cpu_pm_info) + * ======================== low address ======================= + */ + +/* + * Below offsets are based on struct imx6_cpu_pm_info + * which defined in arch/arm/mach-imx/pm-imx6q.c, this + * structure contains necessary pm info for low level + * suspend related code. + */ +#define PM_INFO_PBASE_OFFSET 0x0 +#define PM_INFO_RESUME_ADDR_OFFSET 0x4 +#define PM_INFO_DDR_TYPE_OFFSET 0x8 +#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC +#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10 +#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14 +#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18 +#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C +#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20 +#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24 +#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28 +#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C +#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30 +#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34 +#define PM_INFO_MX6Q_L2_P_OFFSET 0x38 +#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C +#define PM_INFO_MMDC_IO_NUM_OFFSET 0x40 +#define PM_INFO_MMDC_IO_VAL_OFFSET 0x44 + +#define MX6Q_SRC_GPR1 0x20 +#define MX6Q_SRC_GPR2 0x24 +#define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c +#define MX6Q_GPC_IMR1 0x08 +#define MX6Q_GPC_IMR2 0x0c +#define MX6Q_GPC_IMR3 0x10 +#define MX6Q_GPC_IMR4 0x14 +#define MX6Q_CCM_CCR 0x0 + + .align 3 + .arm + + .macro sync_l2_cache + + /* sync L2 cache to drain L2's buffers to DRAM. */ +#ifdef CONFIG_CACHE_L2X0 + ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET] + teq r11, #0 + beq 6f + mov r6, #0x0 + str r6, [r11, #L2X0_CACHE_SYNC] +1: + ldr r6, [r11, #L2X0_CACHE_SYNC] + ands r6, r6, #0x1 + bne 1b +6: +#endif + + .endm + + .macro resume_mmdc + + /* restore MMDC IO */ + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET] + + ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET + add r7, r7, r0 +1: + ldr r8, [r7], #0x4 + ldr r9, [r7], #0x4 + str r9, [r11, r8] + subs r6, r6, #0x1 + bne 1b + + cmp r5, #0x0 + ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + + cmp r3, #IMX_DDR_TYPE_LPDDR2 + bne 4f + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +2: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 2b + + /* reset FIFO a second time */ + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +3: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 3b +4: + /* let DDR out of self-refresh */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] +5: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + bne 5b + + /* enable DDR auto power saving */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + bic r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] + + .endm + +ENTRY(imx6_suspend) + ldr r1, [r0, #PM_INFO_PBASE_OFFSET] + ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET] + + /* + * counting the resume address in iram + * to set it in SRC register. + */ + ldr r6, =imx6_suspend + ldr r7, =resume + sub r7, r7, r6 + add r8, r1, r4 + add r9, r8, r7 + + /* + * make sure TLB contain the addr we want, + * as we will access them after MMDC IO floated. + */ + + ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r6, [r11, #0x0] + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r6, [r11, #0x0] + ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, [r11, #0x0] + + /* use r11 to store the IO address */ + ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET] + /* store physical resume addr and pm_info address. */ + str r9, [r11, #MX6Q_SRC_GPR1] + str r1, [r11, #MX6Q_SRC_GPR2] + + /* need to sync L2 cache before DSM. */ + sync_l2_cache + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + /* + * put DDR explicitly into self-refresh and + * disable automatic power savings. + */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #0x1 + str r7, [r11, #MX6Q_MMDC_MAPSR] + + /* make the DDR explicitly enter self-refresh. */ + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + orr r7, r7, #(1 << 21) + str r7, [r11, #MX6Q_MMDC_MAPSR] + +poll_dvfs_set: + ldr r7, [r11, #MX6Q_MMDC_MAPSR] + ands r7, r7, #(1 << 25) + beq poll_dvfs_set + + ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] + ldr r6, =0x0 + ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] + ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + add r8, r8, r0 + /* LPDDR2's last 3 IOs need special setting */ + cmp r3, #IMX_DDR_TYPE_LPDDR2 + subeq r7, r7, #0x3 +set_mmdc_io_lpm: + ldr r9, [r8], #0x8 + str r6, [r11, r9] + subs r7, r7, #0x1 + bne set_mmdc_io_lpm + + cmp r3, #IMX_DDR_TYPE_LPDDR2 + bne set_mmdc_io_lpm_done + ldr r6, =0x1000 + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r6, =0x80000 + ldr r9, [r8] + str r6, [r11, r9] +set_mmdc_io_lpm_done: + + /* + * mask all GPC interrupts before + * enabling the RBC counters to + * avoid the counter starting too + * early if an interupt is already + * pending. + */ + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + ldr r6, [r11, #MX6Q_GPC_IMR1] + ldr r7, [r11, #MX6Q_GPC_IMR2] + ldr r8, [r11, #MX6Q_GPC_IMR3] + ldr r9, [r11, #MX6Q_GPC_IMR4] + + ldr r10, =0xffffffff + str r10, [r11, #MX6Q_GPC_IMR1] + str r10, [r11, #MX6Q_GPC_IMR2] + str r10, [r11, #MX6Q_GPC_IMR3] + str r10, [r11, #MX6Q_GPC_IMR4] + + /* + * enable the RBC bypass counter here + * to hold off the interrupts. RBC counter + * = 32 (1ms), Minimum RBC delay should be + * 400us for the analog LDOs to power down. + */ + ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET] + ldr r10, [r11, #MX6Q_CCM_CCR] + bic r10, r10, #(0x3f << 21) + orr r10, r10, #(0x20 << 21) + str r10, [r11, #MX6Q_CCM_CCR] + + /* enable the counter. */ + ldr r10, [r11, #MX6Q_CCM_CCR] + orr r10, r10, #(0x1 << 27) + str r10, [r11, #MX6Q_CCM_CCR] + + /* unmask all the GPC interrupts. */ + ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET] + str r6, [r11, #MX6Q_GPC_IMR1] + str r7, [r11, #MX6Q_GPC_IMR2] + str r8, [r11, #MX6Q_GPC_IMR3] + str r9, [r11, #MX6Q_GPC_IMR4] + + /* + * now delay for a short while (3usec) + * ARM is at 1GHz at this point + * so a short loop should be enough. + * this delay is required to ensure that + * the RBC counter can start counting in + * case an interrupt is already pending + * or in case an interrupt arrives just + * as ARM is about to assert DSM_request. + */ + ldr r6, =2000 +rbc_loop: + subs r6, r6, #0x1 + bne rbc_loop + + /* Zzz, enter stop mode */ + wfi + nop + nop + nop + nop + + /* + * run to here means there is pending + * wakeup source, system should auto + * resume, we need to restore MMDC IO first + */ + mov r5, #0x0 + resume_mmdc + + /* return to suspend finish */ + ret lr + +resume: + /* invalidate L1 I-cache first */ + mov r6, #0x0 + mcr p15, 0, r6, c7, c5, 0 + mcr p15, 0, r6, c7, c5, 6 + /* enable the Icache and branch prediction */ + mov r6, #0x1800 + mcr p15, 0, r6, c1, c0, 0 + isb + + /* get physical resume address from pm_info. */ + ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET] + /* clear core0's entry and parameter */ + ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET] + mov r7, #0x0 + str r7, [r11, #MX6Q_SRC_GPR1] + str r7, [r11, #MX6Q_SRC_GPR2] + + ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET] + mov r5, #0x1 + resume_mmdc + + ret lr +ENDPROC(imx6_suspend) diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 6fe81bb4d3c9..e88ca027129d 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -1,19 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include <linux/kernel.h> @@ -27,30 +18,37 @@ #include <asm/system_misc.h> #include <asm/proc-fns.h> #include <asm/mach-types.h> +#include <asm/hardware/cache-l2x0.h> #include "common.h" #include "hardware.h" static void __iomem *wdog_base; static struct clk *wdog_clk; +static int wcr_enable = (1 << 2); /* * Reset the system. It is called by machine_restart(). */ void mxc_restart(enum reboot_mode mode, const char *cmd) { - unsigned int wcr_enable; + if (!wdog_base) + goto reset_fallback; - if (wdog_clk) + if (!IS_ERR(wdog_clk)) clk_enable(wdog_clk); - if (cpu_is_mx1()) - wcr_enable = (1 << 0); - else - wcr_enable = (1 << 2); - /* Assert SRS signal */ - __raw_writew(wcr_enable, wdog_base); + imx_writew(wcr_enable, wdog_base); + /* + * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be + * written twice), we add another two writes to ensure there must be at + * least two writes happen in the same one 32kHz clock period. We save + * the target check here, since the writes shouldn't be a huge burden + * for other platforms. + */ + imx_writew(wcr_enable, wdog_base); + imx_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); @@ -60,6 +58,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd) /* delay to allow the serial port to show the message */ mdelay(50); +reset_fallback: /* we'll take a jump through zero as a poor second */ soft_restart(0); } @@ -69,29 +68,51 @@ void __init mxc_arch_reset_init(void __iomem *base) wdog_base = base; wdog_clk = clk_get_sys("imx2-wdt.0", NULL); - if (IS_ERR(wdog_clk)) { + if (IS_ERR(wdog_clk)) pr_warn("%s: failed to get wdog clock\n", __func__); - wdog_clk = NULL; - return; - } + else + clk_prepare(wdog_clk); +} - clk_prepare(wdog_clk); +#ifdef CONFIG_SOC_IMX1 +void __init imx1_reset_init(void __iomem *base) +{ + wcr_enable = (1 << 0); + mxc_arch_reset_init(base); } +#endif -void __init mxc_arch_reset_init_dt(void) +#ifdef CONFIG_CACHE_L2X0 +void __init imx_init_l2cache(void) { + void __iomem *l2x0_base; struct device_node *np; + unsigned int val; - np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt"); - wdog_base = of_iomap(np, 0); - WARN_ON(!wdog_base); - - wdog_clk = of_clk_get(np, 0); - if (IS_ERR(wdog_clk)) { - pr_warn("%s: failed to get wdog clock\n", __func__); - wdog_clk = NULL; + np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); + if (!np) return; + + l2x0_base = of_iomap(np, 0); + if (!l2x0_base) + goto put_node; + + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); + val |= L310_PREFETCH_CTRL_DBL_LINEFILL | + L310_PREFETCH_CTRL_INSTR_PREFETCH | + L310_PREFETCH_CTRL_DATA_PREFETCH; + + /* Set perfetch offset to improve performance */ + val &= ~L310_PREFETCH_CTRL_OFFSET_MASK; + val |= 15; + + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); } - clk_prepare(wdog_clk); + iounmap(l2x0_base); +put_node: + of_node_put(np); } +#endif diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c deleted file mode 100644 index cd46529e9eaa..000000000000 --- a/arch/arm/mach-imx/time.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * linux/arch/arm/plat-mxc/time.c - * - * Copyright (C) 2000-2001 Deep Blue Solutions - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com) - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/clockchips.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/sched_clock.h> - -#include <asm/mach/time.h> - -#include "common.h" -#include "hardware.h" - -/* - * There are 2 versions of the timer hardware on Freescale MXC hardware. - * Version 1: MX1/MXL, MX21, MX27. - * Version 2: MX25, MX31, MX35, MX37, MX51 - */ - -/* defines common for all i.MX */ -#define MXC_TCTL 0x00 -#define MXC_TCTL_TEN (1 << 0) /* Enable module */ -#define MXC_TPRER 0x04 - -/* MX1, MX21, MX27 */ -#define MX1_2_TCTL_CLK_PCLK1 (1 << 1) -#define MX1_2_TCTL_IRQEN (1 << 4) -#define MX1_2_TCTL_FRR (1 << 8) -#define MX1_2_TCMP 0x08 -#define MX1_2_TCN 0x10 -#define MX1_2_TSTAT 0x14 - -/* MX21, MX27 */ -#define MX2_TSTAT_CAPT (1 << 1) -#define MX2_TSTAT_COMP (1 << 0) - -/* MX31, MX35, MX25, MX5 */ -#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ -#define V2_TCTL_CLK_IPG (1 << 6) -#define V2_TCTL_CLK_PER (2 << 6) -#define V2_TCTL_FRR (1 << 9) -#define V2_IR 0x0c -#define V2_TSTAT 0x08 -#define V2_TSTAT_OF1 (1 << 0) -#define V2_TCN 0x24 -#define V2_TCMP 0x10 - -#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) -#define timer_is_v2() (!timer_is_v1()) - -static struct clock_event_device clockevent_mxc; -static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -static void __iomem *timer_base; - -static inline void gpt_irq_disable(void) -{ - unsigned int tmp; - - if (timer_is_v2()) - __raw_writel(0, timer_base + V2_IR); - else { - tmp = __raw_readl(timer_base + MXC_TCTL); - __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); - } -} - -static inline void gpt_irq_enable(void) -{ - if (timer_is_v2()) - __raw_writel(1<<0, timer_base + V2_IR); - else { - __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, - timer_base + MXC_TCTL); - } -} - -static void gpt_irq_acknowledge(void) -{ - if (timer_is_v1()) { - if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); - else - __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, - timer_base + MX1_2_TSTAT); - } else if (timer_is_v2()) - __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); -} - -static void __iomem *sched_clock_reg; - -static u32 notrace mxc_read_sched_clock(void) -{ - return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; -} - -static int __init mxc_clocksource_init(struct clk *timer_clk) -{ - unsigned int c = clk_get_rate(timer_clk); - void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); - - sched_clock_reg = reg; - - setup_sched_clock(mxc_read_sched_clock, 32, c); - return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, - clocksource_mmio_readl_up); -} - -/* clock event */ - -static int mx1_2_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; - - __raw_writel(tcmp, timer_base + MX1_2_TCMP); - - return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? - -ETIME : 0; -} - -static int v2_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long tcmp; - - tcmp = __raw_readl(timer_base + V2_TCN) + evt; - - __raw_writel(tcmp, timer_base + V2_TCMP); - - return evt < 0x7fffffff && - (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? - -ETIME : 0; -} - -#ifdef DEBUG -static const char *clock_event_mode_label[] = { - [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC", - [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT", - [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN", - [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED", - [CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME", -}; -#endif /* DEBUG */ - -static void mxc_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - unsigned long flags; - - /* - * The timer interrupt generation is disabled at least - * for enough time to call mxc_set_next_event() - */ - local_irq_save(flags); - - /* Disable interrupt in GPT module */ - gpt_irq_disable(); - - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - if (timer_is_v2()) - __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, - timer_base + V2_TCMP); - else - __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, - timer_base + MX1_2_TCMP); - - /* Clear pending interrupt */ - gpt_irq_acknowledge(); - } - -#ifdef DEBUG - printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n", - clock_event_mode_label[clockevent_mode], - clock_event_mode_label[mode]); -#endif /* DEBUG */ - - /* Remember timer mode */ - clockevent_mode = mode; - local_irq_restore(flags); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - printk(KERN_ERR"mxc_set_mode: Periodic mode is not " - "supported for i.MX\n"); - break; - case CLOCK_EVT_MODE_ONESHOT: - /* - * Do not put overhead of interrupt enable/disable into - * mxc_set_next_event(), the core has about 4 minutes - * to call mxc_set_next_event() or shutdown clock after - * mode switching - */ - local_irq_save(flags); - gpt_irq_enable(); - local_irq_restore(flags); - break; - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_RESUME: - /* Left event sources disabled, no more interrupts appear */ - break; - } -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &clockevent_mxc; - uint32_t tstat; - - if (timer_is_v2()) - tstat = __raw_readl(timer_base + V2_TSTAT); - else - tstat = __raw_readl(timer_base + MX1_2_TSTAT); - - gpt_irq_acknowledge(); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -static struct irqaction mxc_timer_irq = { - .name = "i.MX Timer Tick", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = mxc_timer_interrupt, -}; - -static struct clock_event_device clockevent_mxc = { - .name = "mxc_timer1", - .features = CLOCK_EVT_FEAT_ONESHOT, - .set_mode = mxc_set_mode, - .set_next_event = mx1_2_set_next_event, - .rating = 200, -}; - -static int __init mxc_clockevent_init(struct clk *timer_clk) -{ - if (timer_is_v2()) - clockevent_mxc.set_next_event = v2_set_next_event; - - clockevent_mxc.cpumask = cpumask_of(0); - clockevents_config_and_register(&clockevent_mxc, - clk_get_rate(timer_clk), - 0xff, 0xfffffffe); - - return 0; -} - -void __init mxc_timer_init(void __iomem *base, int irq) -{ - uint32_t tctl_val; - struct clk *timer_clk; - struct clk *timer_ipg_clk; - - timer_clk = clk_get_sys("imx-gpt.0", "per"); - if (IS_ERR(timer_clk)) { - pr_err("i.MX timer: unable to get clk\n"); - return; - } - - timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg"); - if (!IS_ERR(timer_ipg_clk)) - clk_prepare_enable(timer_ipg_clk); - - clk_prepare_enable(timer_clk); - - timer_base = base; - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - - __raw_writel(0, timer_base + MXC_TCTL); - __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - - if (timer_is_v2()) - tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - else - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - - __raw_writel(tctl_val, timer_base + MXC_TCTL); - - /* init and register the timer to the framework */ - mxc_clocksource_init(timer_clk); - mxc_clockevent_init(timer_clk); - - /* Make irqs happen */ - setup_irq(irq, &mxc_timer_irq); -} diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c index 8183178d5aa3..50a5668e65d2 100644 --- a/arch/arm/mach-imx/tzic.c +++ b/arch/arm/mach-imx/tzic.c @@ -1,22 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ -#include <linux/module.h> -#include <linux/moduleparam.h> #include <linux/init.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/io.h> +#include <linux/irqchip.h> #include <linux/irqdomain.h> #include <linux/of.h> +#include <linux/of_address.h> #include <asm/mach/irq.h> #include <asm/exception.h> @@ -55,19 +49,19 @@ static struct irq_domain *domain; #define TZIC_NUM_IRQS 128 #ifdef CONFIG_FIQ -static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) +static int tzic_set_irq_fiq(unsigned int hwirq, unsigned int type) { unsigned int index, mask, value; - index = irq >> 5; + index = hwirq >> 5; if (unlikely(index >= 4)) return -EINVAL; - mask = 1U << (irq & 0x1F); + mask = 1U << (hwirq & 0x1F); - value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; + value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; if (type) value &= ~mask; - __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); + imx_writel(value, tzic_base + TZIC_INTSEC0(index)); return 0; } @@ -81,15 +75,15 @@ static void tzic_irq_suspend(struct irq_data *d) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); int idx = d->hwirq >> 5; - __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); + imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); } static void tzic_irq_resume(struct irq_data *d) { int idx = d->hwirq >> 5; - __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), - tzic_base + TZIC_WAKEUP0(idx)); + imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)), + tzic_base + TZIC_WAKEUP0(idx)); } #else @@ -125,7 +119,7 @@ static __init void tzic_init_gc(int idx, unsigned int irq_start) irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); } -asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) +static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) { u32 stat; int i, irqofs, handled; @@ -134,14 +128,13 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) handled = 0; for (i = 0; i < 4; i++) { - stat = __raw_readl(tzic_base + TZIC_HIPND(i)) & - __raw_readl(tzic_base + TZIC_INTSEC0(i)); + stat = imx_readl(tzic_base + TZIC_HIPND(i)) & + imx_readl(tzic_base + TZIC_INTSEC0(i)); while (stat) { handled = 1; irqofs = fls(stat) - 1; - handle_IRQ(irq_find_mapping(domain, - irqofs + i * 32), regs); + generic_handle_domain_irq(domain, irqofs + i * 32); stat &= ~(1 << irqofs); } } @@ -153,49 +146,54 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ -void __init tzic_init_irq(void __iomem *irqbase) +static int __init tzic_init_dt(struct device_node *np, struct device_node *p) { - struct device_node *np; int irq_base; int i; - tzic_base = irqbase; + tzic_base = of_iomap(np, 0); + WARN_ON(!tzic_base); + /* put the TZIC into the reset value with * all interrupts disabled */ - i = __raw_readl(tzic_base + TZIC_INTCNTL); + i = imx_readl(tzic_base + TZIC_INTCNTL); - __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); - __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); - __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); + imx_writel(0x80010001, tzic_base + TZIC_INTCNTL); + imx_writel(0x1f, tzic_base + TZIC_PRIOMASK); + imx_writel(0x02, tzic_base + TZIC_SYNCCTRL); for (i = 0; i < 4; i++) - __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); + imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); /* disable all interrupts */ for (i = 0; i < 4; i++) - __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); + imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); /* all IRQ no FIQ Warning :: No selection */ irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id()); WARN_ON(irq_base < 0); - np = of_find_compatible_node(NULL, NULL, "fsl,tzic"); - domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0, - &irq_domain_simple_ops, NULL); + domain = irq_domain_create_legacy(of_fwnode_handle(np), TZIC_NUM_IRQS, irq_base, 0, + &irq_domain_simple_ops, NULL); WARN_ON(!domain); for (i = 0; i < 4; i++, irq_base += 32) tzic_init_gc(i, irq_base); + set_handle_irq(tzic_handle_irq); + #ifdef CONFIG_FIQ /* Initialize FIQ */ init_FIQ(FIQ_START); #endif pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); + + return 0; } +IRQCHIP_DECLARE(tzic, "fsl,tzic", tzic_init_dt); /** * tzic_enable_wake() - enable wakeup interrupt @@ -210,13 +208,13 @@ int tzic_enable_wake(void) { unsigned int i; - __raw_writel(1, tzic_base + TZIC_DSMINT); - if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) + imx_writel(1, tzic_base + TZIC_DSMINT); + if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0)) return -EAGAIN; for (i = 0; i < 4; i++) - __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), - tzic_base + TZIC_WAKEUP0(i)); + imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)), + tzic_base + TZIC_WAKEUP0(i)); return 0; } diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h deleted file mode 100644 index 23f5c0349e80..000000000000 --- a/arch/arm/mach-imx/ulpi.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef __MACH_ULPI_H -#define __MACH_ULPI_H - -#include <linux/usb/ulpi.h> - -#ifdef CONFIG_USB_ULPI_VIEWPORT -static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return otg_ulpi_create(&ulpi_viewport_access_ops, flags); -} -#else -static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return NULL; -} -#endif - -#endif /* __MACH_ULPI_H */ - |