diff options
Diffstat (limited to 'arch/arm/mach-mmp/time.c')
| -rw-r--r-- | arch/arm/mach-mmp/time.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 41b2e8abc9e6..fcb190826dd1 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -29,32 +29,30 @@ #include <linux/sched_clock.h> #include <asm/mach/time.h> -#include "addr-map.h" #include "regs-timers.h" -#include "regs-apbc.h" -#include "irqs.h" #include <linux/soc/mmp/cputype.h> -#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE - #define MAX_DELTA (0xfffffffe) #define MIN_DELTA (16) -static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; +static void __iomem *mmp_timer_base; /* - * FIXME: the timer needs some delay to stablize the counter capture + * Read the timer through the CVWR register. Delay is required after requesting + * a read. The CR register cannot be directly read due to metastability issues + * documented in the PXA168 software manual. */ static inline uint32_t timer_read(void) { - int delay = 100; + uint32_t val; + int delay = 3; __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); while (delay--) - cpu_relax(); + val = __raw_readl(mmp_timer_base + TMR_CVWR(1)); - return __raw_readl(mmp_timer_base + TMR_CVWR(1)); + return val; } static u64 notrace mmp_read_sched_clock(void) @@ -174,7 +172,7 @@ static void __init timer_config(void) __raw_writel(0x2, mmp_timer_base + TMR_CER); } -void __init mmp_timer_init(int irq, unsigned long rate) +static void __init mmp_timer_init(int irq, unsigned long rate) { timer_config(); |