diff options
Diffstat (limited to 'arch/arm/mach-mv78xx0/common.c')
| -rw-r--r-- | arch/arm/mach-mv78xx0/common.c | 54 |
1 files changed, 34 insertions, 20 deletions
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index 75062eff2494..679753fcc0ef 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -1,30 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78xx0/common.c * * Core functions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/io.h> #include <linux/platform_device.h> #include <linux/serial_8250.h> #include <linux/ata_platform.h> #include <linux/clk-provider.h> #include <linux/ethtool.h> +#include <asm/hardware/cache-feroceon-l2.h> #include <asm/mach/map.h> #include <asm/mach/time.h> -#include <mach/mv78xx0.h> -#include <mach/bridge-regs.h> -#include <plat/cache-feroceon-l2.h> #include <linux/platform_data/usb-ehci-orion.h> #include <linux/platform_data/mtd-orion_nand.h> #include <plat/time.h> #include <plat/common.h> #include <plat/addr-map.h> +#include "mv78xx0.h" +#include "bridge-regs.h" #include "common.h" static int get_tclk(void); @@ -168,8 +166,7 @@ static struct clk *tclk; static void __init clk_init(void) { - tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, - get_tclk()); + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk()); orion_clkdev_init(tclk); } @@ -220,7 +217,6 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, - NO_IRQ, MV643XX_TX_CSUM_DEFAULT_LIMIT); } @@ -243,9 +239,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge10_init(eth_data, - GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM, - NO_IRQ); + orion_ge10_init(eth_data, GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM); } @@ -267,9 +261,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) eth_data->duplex = DUPLEX_FULL; } - orion_ge11_init(eth_data, - GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM, - NO_IRQ); + orion_ge11_init(eth_data, GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM); } /***************************************************************************** @@ -344,12 +336,35 @@ void __init mv78xx0_init_early(void) DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ); } -void __init_refok mv78xx0_timer_init(void) +void __ref mv78xx0_timer_init(void) { orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } +/**************************************************************************** +* XOR engine +****************************************************************************/ +void __init mv78xx0_xor_init(void) +{ + orion_xor0_init(XOR_PHYS_BASE, + XOR_PHYS_BASE + 0x200, + IRQ_MV78XX0_XOR_0, IRQ_MV78XX0_XOR_1); +} + +/**************************************************************************** + * Cryptographic Engines and Security Accelerator (CESA) +****************************************************************************/ +void __init mv78xx0_crypto_init(void) +{ + mvebu_mbus_add_window_by_id(MV78XX0_MBUS_SRAM_TARGET, + MV78XX0_MBUS_SRAM_ATTR, + MV78XX0_SRAM_PHYS_BASE, + MV78XX0_SRAM_SIZE); + orion_crypto_init(CRYPTO_PHYS_BASE, MV78XX0_SRAM_PHYS_BASE, + SZ_8K, IRQ_MV78XX0_CRYPTO); +} + /***************************************************************************** * General @@ -405,9 +420,8 @@ void __init mv78xx0_init(void) printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); -#ifdef CONFIG_CACHE_FEROCEON_L2 - feroceon_l2_init(is_l2_writethrough()); -#endif + if (IS_ENABLED(CONFIG_CACHE_FEROCEON_L2)) + feroceon_l2_init(is_l2_writethrough()); /* Setup root of clk tree */ clk_init(); |