diff options
Diffstat (limited to 'arch/arm/mach-mv78xx0/mv78xx0.h')
| -rw-r--r-- | arch/arm/mach-mv78xx0/mv78xx0.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h index 2db1265ec121..88efb1e44142 100644 --- a/arch/arm/mach-mv78xx0/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/mv78xx0.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Generic definitions for Marvell MV78xx0 SoC flavors: * MV781x0 and MV782x0. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #ifndef __ASM_ARCH_MV78XX0_H @@ -37,7 +34,7 @@ * fee50000 f0d00000 64K PCIe #5 I/O space * fee60000 f0e00000 64K PCIe #6 I/O space * fee70000 f0f00000 64K PCIe #7 I/O space - * fd000000 f1000000 1M on-chip peripheral registers + * fec00000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -49,12 +46,18 @@ #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) #define MV78XX0_REGS_SIZE SZ_1M +#define MV78XX0_SRAM_PHYS_BASE (0xf2200000) +#define MV78XX0_SRAM_SIZE SZ_8K + #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 #define MV78XX0_PCIE_MEM_SIZE 0x30000000 +#define MV78XX0_MBUS_SRAM_TARGET 0x09 +#define MV78XX0_MBUS_SRAM_ATTR 0x00 + /* * Core-specific peripheral registers. */ @@ -101,6 +104,8 @@ #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) +#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900) + #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) @@ -109,6 +114,8 @@ #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) +#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000) + #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) /* |