summaryrefslogtreecommitdiff
path: root/arch/arm/mach-omap2/id.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-omap2/id.c')
-rw-r--r--arch/arm/mach-omap2/id.c231
1 files changed, 178 insertions, 53 deletions
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2dc62a25f2c3..7f387706368a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-omap2/id.c
*
@@ -8,16 +9,13 @@
*
* Copyright (C) 2009-11 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/random.h>
#include <linux/slab.h>
#ifdef CONFIG_SOC_BUS
@@ -51,17 +49,22 @@ EXPORT_SYMBOL(omap_rev);
int omap_type(void)
{
- u32 val = 0;
+ static u32 val = OMAP2_DEVICETYPE_MASK;
+
+ if (val < OMAP2_DEVICETYPE_MASK)
+ return val;
- if (cpu_is_omap24xx()) {
+ if (soc_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
+ } else if (soc_is_ti81xx()) {
+ val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
} else if (soc_is_am33xx() || soc_is_am43xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
- } else if (cpu_is_omap34xx()) {
+ } else if (soc_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
- } else if (soc_is_omap54xx()) {
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
val &= OMAP5_DEVICETYPE_MASK;
val >>= 6;
@@ -93,7 +96,7 @@ EXPORT_SYMBOL(omap_type);
#define OMAP_TAP_DIE_ID_44XX_2 0x020c
#define OMAP_TAP_DIE_ID_44XX_3 0x0210
-#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
+#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
struct omap_id {
u16 hawkeye; /* Silicon type (Hawkeye id) */
@@ -114,9 +117,9 @@ static struct omap_id omap_ids[] __initdata = {
static void __iomem *tap_base;
static u16 tap_prod_id;
-void omap_get_die_id(struct omap_die_id *odi)
+static void omap_get_die_id(struct omap_die_id *odi)
{
- if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@@ -130,6 +133,17 @@ void omap_get_die_id(struct omap_die_id *odi)
odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
}
+static int __init omap_feed_randpool(void)
+{
+ struct omap_die_id odi;
+
+ /* Throw the die ID into the entropy pool at boot */
+ omap_get_die_id(&odi);
+ add_device_randomness(&odi, sizeof(odi));
+ return 0;
+}
+omap_device_initcall(omap_feed_randpool);
+
void __init omap2xxx_check_revision(void)
{
int i, j;
@@ -182,17 +196,21 @@ void __init omap2xxx_check_revision(void)
pr_info("%s", soc_name);
if ((omap_rev() >> 8) & 0x0f)
- pr_info("%s", soc_rev);
- pr_info("\n");
+ pr_cont("%s", soc_rev);
+ pr_cont("\n");
}
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
- printk(#feat" ");
+ n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
static void __init omap3_cpuinfo(void)
{
const char *cpu_name;
+ char buf[64];
+ int n = 0;
+
+ memset(buf, 0, sizeof(buf));
/*
* OMAP3430 and OMAP3530 are assumed to be same.
@@ -201,17 +219,25 @@ static void __init omap3_cpuinfo(void)
* on available features. Upon detection, update the CPU id
* and CPU class bits.
*/
- if (cpu_is_omap3630()) {
- cpu_name = "OMAP3630";
+ if (soc_is_omap3630()) {
+ if (omap3_has_iva() && omap3_has_sgx()) {
+ cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
+ } else if (omap3_has_iva()) {
+ cpu_name = "DM3725";
+ } else if (omap3_has_sgx()) {
+ cpu_name = "OMAP3615/AM3715";
+ } else {
+ cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
+ }
} else if (soc_is_am35xx()) {
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
- } else if (cpu_is_ti816x()) {
+ } else if (soc_is_ti816x()) {
cpu_name = "TI816X";
} else if (soc_is_am335x()) {
cpu_name = "AM335X";
} else if (soc_is_am437x()) {
cpu_name = "AM437x";
- } else if (cpu_is_ti814x()) {
+ } else if (soc_is_ti814x()) {
cpu_name = "TI814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
@@ -224,10 +250,10 @@ static void __init omap3_cpuinfo(void)
cpu_name = "OMAP3503";
}
- sprintf(soc_name, "%s", cpu_name);
+ scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
/* Print verbose information */
- pr_info("%s %s (", soc_name, soc_rev);
+ n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
OMAP3_SHOW_FEATURE(l2cache);
OMAP3_SHOW_FEATURE(iva);
@@ -235,8 +261,10 @@ static void __init omap3_cpuinfo(void)
OMAP3_SHOW_FEATURE(neon);
OMAP3_SHOW_FEATURE(isp);
OMAP3_SHOW_FEATURE(192mhz_clk);
-
- printk(")\n");
+ if (*(buf + n - 1) == ' ')
+ n--;
+ n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
+ pr_info("%s", buf);
}
#define OMAP3_CHECK_FEATURE(status,feat) \
@@ -258,11 +286,11 @@ void __init omap3xxx_check_features(void)
OMAP3_CHECK_FEATURE(status, SGX);
OMAP3_CHECK_FEATURE(status, NEON);
OMAP3_CHECK_FEATURE(status, ISP);
- if (cpu_is_omap3630())
+ if (soc_is_omap3630())
omap_features |= OMAP3_HAS_192MHZ_CLK;
- if (cpu_is_omap3430() || cpu_is_omap3630())
+ if (soc_is_omap3430() || soc_is_omap3630())
omap_features |= OMAP3_HAS_IO_WAKEUP;
- if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
+ if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
omap_rev() == OMAP3430_REV_ES3_1_2)
omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
@@ -368,7 +396,6 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "3.1";
break;
case 7:
- /* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1_2;
@@ -388,7 +415,6 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "1.0";
break;
case 1:
- /* FALLTHROUGH */
default:
omap_revision = AM35XX_REV_ES1_1;
cpu_rev = "1.1";
@@ -407,7 +433,6 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "1.1";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2";
@@ -428,7 +453,6 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "2.0";
break;
case 3:
- /* FALLTHROUGH */
default:
omap_revision = TI8168_REV_ES2_1;
cpu_rev = "2.1";
@@ -445,7 +469,6 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "2.0";
break;
case 2:
- /* FALLTHROUGH */
default:
omap_revision = AM335X_REV_ES2_1;
cpu_rev = "2.1";
@@ -453,13 +476,26 @@ void __init omap3xxx_check_revision(void)
}
break;
case 0xb98c:
- omap_revision = AM437X_REV_ES1_0;
- cpu_rev = "1.0";
+ switch (rev) {
+ case 0:
+ omap_revision = AM437X_REV_ES1_0;
+ cpu_rev = "1.0";
+ break;
+ case 1:
+ omap_revision = AM437X_REV_ES1_1;
+ cpu_rev = "1.1";
+ break;
+ case 2:
+ default:
+ omap_revision = AM437X_REV_ES1_2;
+ cpu_rev = "1.2";
+ break;
+ }
break;
case 0xb8f2:
+ case 0xb968:
switch (rev) {
case 0:
- /* FALLTHROUGH */
case 1:
omap_revision = TI8148_REV_ES1_0;
cpu_rev = "1.0";
@@ -469,7 +505,6 @@ void __init omap3xxx_check_revision(void)
cpu_rev = "2.0";
break;
case 3:
- /* FALLTHROUGH */
default:
omap_revision = TI8148_REV_ES2_1;
cpu_rev = "2.1";
@@ -480,7 +515,8 @@ void __init omap3xxx_check_revision(void)
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
cpu_rev = "1.2";
- pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
+ pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
+ hawkeye);
}
sprintf(soc_rev, "ES%s", cpu_rev);
}
@@ -576,8 +612,8 @@ void __init omap5xxx_check_revision(void)
case 0xb942:
switch (rev) {
case 0:
- omap_revision = OMAP5430_REV_ES1_0;
- break;
+ /* No support for ES1.0 Test chip */
+ BUG();
case 1:
default:
omap_revision = OMAP5430_REV_ES2_0;
@@ -587,8 +623,8 @@ void __init omap5xxx_check_revision(void)
case 0xb998:
switch (rev) {
case 0:
- omap_revision = OMAP5432_REV_ES1_0;
- break;
+ /* No support for ES1.0 Test chip */
+ BUG();
case 1:
default:
omap_revision = OMAP5432_REV_ES2_0;
@@ -606,6 +642,82 @@ void __init omap5xxx_check_revision(void)
pr_info("%s %s\n", soc_name, soc_rev);
}
+void __init dra7xxx_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev, package;
+ struct omap_die_id odi;
+
+ omap_get_die_id(&odi);
+ package = (odi.id_2 >> 16) & 0x3;
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+ switch (hawkeye) {
+ case 0xbb50:
+ switch (rev) {
+ case 0:
+ default:
+ switch (package) {
+ case 0x2:
+ omap_revision = DRA762_ABZ_REV_ES1_0;
+ break;
+ case 0x3:
+ omap_revision = DRA762_ACD_REV_ES1_0;
+ break;
+ default:
+ omap_revision = DRA762_REV_ES1_0;
+ break;
+ }
+ break;
+ }
+ break;
+
+ case 0xb990:
+ switch (rev) {
+ case 0:
+ omap_revision = DRA752_REV_ES1_0;
+ break;
+ case 1:
+ omap_revision = DRA752_REV_ES1_1;
+ break;
+ case 2:
+ default:
+ omap_revision = DRA752_REV_ES2_0;
+ break;
+ }
+ break;
+
+ case 0xb9bc:
+ switch (rev) {
+ case 0:
+ omap_revision = DRA722_REV_ES1_0;
+ break;
+ case 1:
+ omap_revision = DRA722_REV_ES2_0;
+ break;
+ case 2:
+ default:
+ omap_revision = DRA722_REV_ES2_1;
+ break;
+ }
+ break;
+
+ default:
+ /* Unknown default to latest silicon rev as default*/
+ pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
+ __func__, idcode, hawkeye, rev);
+ omap_revision = DRA752_REV_ES2_0;
+ }
+
+ sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
+ sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+ (omap_rev() >> 8) & 0xf);
+
+ pr_info("%s %s\n", soc_name, soc_rev);
+}
+
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
@@ -619,7 +731,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
tap_base = tap;
/* XXX What is this intended to do? */
- if (cpu_is_omap34xx())
+ if (soc_is_omap34xx())
tap_prod_id = 0x0210;
else
tap_prod_id = 0x0208;
@@ -637,31 +749,41 @@ static const char * const omap_types[] = {
static const char * __init omap_get_family(void)
{
- if (cpu_is_omap24xx())
+ if (soc_is_omap24xx())
return kasprintf(GFP_KERNEL, "OMAP2");
- else if (cpu_is_omap34xx())
+ else if (soc_is_omap34xx())
return kasprintf(GFP_KERNEL, "OMAP3");
- else if (cpu_is_omap44xx())
+ else if (soc_is_omap44xx())
return kasprintf(GFP_KERNEL, "OMAP4");
else if (soc_is_omap54xx())
return kasprintf(GFP_KERNEL, "OMAP5");
+ else if (soc_is_am33xx() || soc_is_am335x())
+ return kasprintf(GFP_KERNEL, "AM33xx");
+ else if (soc_is_am43xx())
+ return kasprintf(GFP_KERNEL, "AM43xx");
+ else if (soc_is_dra7xx())
+ return kasprintf(GFP_KERNEL, "DRA7");
else
return kasprintf(GFP_KERNEL, "Unknown");
}
-static ssize_t omap_get_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static ssize_t
+type_show(struct device *dev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%s\n", omap_types[omap_type()]);
}
-static struct device_attribute omap_soc_attr =
- __ATTR(type, S_IRUGO, omap_get_type, NULL);
+static DEVICE_ATTR_RO(type);
+
+static struct attribute *omap_soc_attrs[] = {
+ &dev_attr_type.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(omap_soc);
void __init omap_soc_device_init(void)
{
- struct device *parent;
struct soc_device *soc_dev;
struct soc_device_attribute *soc_dev_attr;
@@ -671,15 +793,18 @@ void __init omap_soc_device_init(void)
soc_dev_attr->machine = soc_name;
soc_dev_attr->family = omap_get_family();
+ if (!soc_dev_attr->family) {
+ kfree(soc_dev_attr);
+ return;
+ }
soc_dev_attr->revision = soc_rev;
+ soc_dev_attr->custom_attr_group = omap_soc_groups[0];
soc_dev = soc_device_register(soc_dev_attr);
if (IS_ERR(soc_dev)) {
+ kfree(soc_dev_attr->family);
kfree(soc_dev_attr);
return;
}
-
- parent = soc_device_to_device(soc_dev);
- device_create_file(parent, &omap_soc_attr);
}
#endif /* CONFIG_SOC_BUS */
generated by cgit (git 2.34.1) at 2025-12-25 05:59:01 +0000