diff options
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 45 |
1 files changed, 38 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 12ef6e81c8bd..f69923da07fe 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -105,7 +105,7 @@ mux { groups = "uart_tx_ao_a", "uart_rx_ao_a"; function = "uart_ao"; - bias-disable; + bias-pull-up; }; }; @@ -122,7 +122,7 @@ mux { groups = "uart_tx_ao_b", "uart_rx_ao_b"; function = "uart_ao_b"; - bias-disable; + bias-pull-up; }; }; @@ -311,10 +311,16 @@ <&reset RESET_HDMI_SYSTEM_RESET>, <&reset RESET_HDMI_TX>; reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; - clocks = <&clkc CLKID_HDMI_PCLK>, - <&clkc CLKID_CLK81>, + clocks = <&clkc CLKID_HDMI>, + <&clkc CLKID_HDMI_PCLK>, <&clkc CLKID_GCLK_VENCI_INT0>; clock-names = "isfr", "iahb", "venci"; + power-domains = <&pwrc PWRC_GXBB_VPU_ID>; + + assigned-clocks = <&clkc CLKID_HDMI_SEL>, + <&clkc CLKID_HDMI>; + assigned-clock-parents = <&xtal>, <0>; + assigned-clock-rates = <0>, <24000000>; }; &sysctrl { @@ -514,7 +520,7 @@ groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; - bias-disable; + bias-pull-up; }; }; @@ -532,7 +538,7 @@ groups = "uart_tx_b", "uart_rx_b"; function = "uart_b"; - bias-disable; + bias-pull-up; }; }; @@ -550,7 +556,7 @@ groups = "uart_tx_c", "uart_rx_c"; function = "uart_c"; - bias-disable; + bias-pull-up; }; }; @@ -733,6 +739,31 @@ }; }; +&pwm_ab { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_AO_ab { + clocks = <&xtal>, <&clkc CLKID_CLK81>; +}; + +&pwm_cd { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_ef { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + &pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, |