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Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-gxl.dtsi')
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxl.dtsi47
1 files changed, 36 insertions, 11 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index f58d1790de1c..ba535010a3c9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -163,7 +163,7 @@
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
- bias-disable;
+ bias-pull-up;
};
};
@@ -180,7 +180,7 @@
mux {
groups = "uart_tx_ao_b", "uart_rx_ao_b";
function = "uart_ao_b";
- bias-disable;
+ bias-pull-up;
};
};
@@ -188,7 +188,7 @@
mux {
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
function = "uart_ao_b";
- bias-disable;
+ bias-pull-up;
};
};
@@ -214,7 +214,7 @@
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
- bias-disable;
+ bias-pull-up;
};
};
@@ -522,7 +522,7 @@
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
- bias-disable;
+ bias-pull-up;
};
};
@@ -540,7 +540,7 @@
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
- bias-disable;
+ bias-pull-up;
};
};
@@ -558,7 +558,7 @@
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
- bias-disable;
+ bias-pull-up;
};
};
@@ -576,7 +576,7 @@
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
- bias-disable;
+ bias-pull-up;
};
};
@@ -585,7 +585,7 @@
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
- bias-disable;
+ bias-pull-up;
};
};
@@ -594,7 +594,7 @@
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
- bias-disable;
+ bias-pull-up;
};
};
@@ -603,7 +603,7 @@
groups = "i2c_sck_c_dv19",
"i2c_sda_c_dv18";
function = "i2c_c";
- bias-disable;
+ bias-pull-up;
};
};
@@ -809,6 +809,31 @@
};
};
+&pwm_ab {
+ clocks = <&xtal>,
+ <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_FCLK_DIV3>;
+};
+
+&pwm_AO_ab {
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
+};
+
+&pwm_cd {
+ clocks = <&xtal>,
+ <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_FCLK_DIV3>;
+};
+
+&pwm_ef {
+ clocks = <&xtal>,
+ <0>, /* unknown/untested, the datasheet calls it "vid_pll" */
+ <&clkc CLKID_FCLK_DIV4>,
+ <&clkc CLKID_FCLK_DIV3>;
+};
+
&pwrc {
resets = <&reset RESET_VIU>,
<&reset RESET_VENC>,