diff options
Diffstat (limited to 'arch/arm64/boot/dts/apple/s8000.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/apple/s8000.dtsi | 162 |
1 files changed, 43 insertions, 119 deletions
diff --git a/arch/arm64/boot/dts/apple/s8000.dtsi b/arch/arm64/boot/dts/apple/s8000.dtsi index 6e9046ea106c..72322f5677ab 100644 --- a/arch/arm64/boot/dts/apple/s8000.dtsi +++ b/arch/arm64/boot/dts/apple/s8000.dtsi @@ -4,141 +4,65 @@ * * Other names: H8P, "Maui" * - * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> + * Copyright (c) 2024, Nick Chan <towinchenmi@gmail.com> */ -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/apple-aic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/apple.h> +#include "s800-0-3.dtsi" / { - interrupt-parent = <&aic>; - #address-cells = <2>; - #size-cells = <2>; + twister_opp: opp-table { + compatible = "operating-points-v2"; - clkref: clock-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "clkref"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "apple,twister"; - reg = <0x0 0x0>; - cpu-release-addr = <0 0>; /* To be filled in by loader */ - enable-method = "spin-table"; - device_type = "cpu"; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <650>; }; - - cpu1: cpu@1 { - compatible = "apple,twister"; - reg = <0x0 0x1>; - cpu-release-addr = <0 0>; /* To be filled in by loader */ - enable-method = "spin-table"; - device_type = "cpu"; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <75000>; }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - nonposted-mmio; - ranges; - - serial0: serial@20a0c0000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x0a0c0000 0x0 0x4000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>; - /* Use the bootloader-enabled clocks for now. */ - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <27000>; }; - - aic: interrupt-controller@20e100000 { - compatible = "apple,s8000-aic", "apple,aic"; - reg = <0x2 0x0e100000 0x0 0x100000>; - #interrupt-cells = <3>; - interrupt-controller; + opp04 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <4>; + clock-latency-ns = <32000>; }; - - pinctrl_ap: pinctrl@20f100000 { - compatible = "apple,s8000-pinctrl", "apple,pinctrl"; - reg = <0x2 0x0f100000 0x0 0x100000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_ap 0 0 208>; - apple,npins = <208>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-level = <5>; + clock-latency-ns = <35000>; }; - - pinctrl_aop: pinctrl@2100f0000 { - compatible = "apple,s8000-pinctrl", "apple,pinctrl"; - reg = <0x2 0x100f0000 0x0 0x100000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>, - <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <6>; + clock-latency-ns = <45000>; }; - - wdt: watchdog@2102b0000 { - compatible = "apple,s8000-wdt", "apple,wdt"; - reg = <0x2 0x102b0000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <7>; + clock-latency-ns = <58000>; }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&aic>; - interrupt-names = "phys", "virt"; - /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ - interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, - <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <1844000000>; + opp-level = <8>; + clock-latency-ns = <58000>; + turbo-mode; + }; +#endif }; }; /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ |