diff options
Diffstat (limited to 'arch/arm64/boot/dts/apple/s8001.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/apple/s8001.dtsi | 227 |
1 files changed, 227 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi new file mode 100644 index 000000000000..fee350765894 --- /dev/null +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple S8001 "A9X" SoC + * + * Other names: H8G, "Elba" + * + * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "apple,twister"; + reg = <0x0 0x0>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + cpu1: cpu@1 { + compatible = "apple,twister"; + reg = <0x0 0x1>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x300000>; + }; + }; + + twister_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <800>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <53000>; + }; + opp03 { + opp-hz = /bits/ 64 <792000000>; + opp-level = <3>; + clock-latency-ns = <18000>; + }; + opp04 { + opp-hz = /bits/ 64 <1080000000>; + opp-level = <4>; + clock-latency-ns = <21000>; + }; + opp05 { + opp-hz = /bits/ 64 <1440000000>; + opp-level = <5>; + clock-latency-ns = <25000>; + }; + opp06 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <6>; + clock-latency-ns = <33000>; + }; + opp07 { + opp-hz = /bits/ 64 <2160000000>; + opp-level = <7>; + clock-latency-ns = <45000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <2160000000>; + opp-level = <8>; + clock-latency-ns = <45000>; + turbo-mode; + }; +#endif + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + cpufreq: performance-controller@202220000 { + compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + serial0: serial@20a0c0000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x0a0c0000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + pmgr: power-management@20e000000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + + aic: interrupt-controller@20e100000 { + compatible = "apple,s8000-aic", "apple,aic"; + reg = <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + power-domains = <&ps_aic>; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible = "apple,s8000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 219>; + apple,npins = <219>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible = "apple,s8000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 28>; + apple,npins = <28>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; + }; + + pmgr_mini: power-management@210200000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + + wdt: watchdog@2102b0000 { + compatible = "apple,s8000-wdt", "apple,wdt"; + reg = <0x2 0x102b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that A9X doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +#include "s8001-pmgr.dtsi" |