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Diffstat (limited to 'arch/arm64/boot/dts/apple/t8011.dtsi')
-rw-r--r--arch/arm64/boot/dts/apple/t8011.dtsi193
1 files changed, 193 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi
index 6c4ed9dc4a50..039aa4d1e887 100644
--- a/arch/arm64/boot/dts/apple/t8011.dtsi
+++ b/arch/arm64/boot/dts/apple/t8011.dtsi
@@ -32,27 +32,116 @@
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x0>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&fusion_opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@1 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x1>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&fusion_opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
};
cpu2: cpu@2 {
compatible = "apple,hurricane-zephyr";
reg = <0x0 0x2>;
cpu-release-addr = <0 0>; /* To be filled by loader */
+ operating-points-v2 = <&fusion_opp>;
+ performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x800000>; /* P-cluster */
};
};
+ fusion_opp: opp-table {
+ compatible = "operating-points-v2";
+
+ /*
+ * Apple Fusion Architecture: Hardwired big.LITTLE switcher
+ * that use p-state transitions to switch between cores.
+ *
+ * The E-core frequencies are adjusted so performance scales
+ * linearly with reported clock speed.
+ */
+
+ opp01 {
+ opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
+ opp-level = <1>;
+ clock-latency-ns = <12000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
+ opp-level = <2>;
+ clock-latency-ns = <135000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */
+ opp-level = <3>;
+ clock-latency-ns = <105000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */
+ opp-level = <4>;
+ clock-latency-ns = <115000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <804000000>;
+ opp-level = <5>;
+ clock-latency-ns = <122000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1140000000>;
+ opp-level = <6>;
+ clock-latency-ns = <120000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1548000000>;
+ opp-level = <7>;
+ clock-latency-ns = <125000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1956000000>;
+ opp-level = <8>;
+ clock-latency-ns = <135000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2316000000>;
+ opp-level = <9>;
+ clock-latency-ns = <140000>;
+ };
+#if 0
+ /* Not available until CPU deep sleep is implemented */
+ opp10 {
+ opp-hz = /bits/ 64 <2400000000>;
+ opp-level = <10>;
+ clock-latency-ns = <140000>;
+ turbo-mode;
+ };
+#endif
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -60,6 +149,12 @@
nonposted-mmio;
ranges;
+ cpufreq: performance-controller@202f20000 {
+ compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
+ reg = <0x2 0x02f20000 0 0x1000>;
+ #performance-domain-cells = <0>;
+ };
+
serial0: serial@20a0c0000 {
compatible = "apple,s5l-uart";
reg = <0x2 0x0a0c0000 0x0 0x4000>;
@@ -69,19 +164,86 @@
/* Use the bootloader-enabled clocks for now. */
clocks = <&clkref>, <&clkref>;
clock-names = "uart", "clk_uart_baud0";
+ power-domains = <&ps_uart0>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@20a110000 {
+ compatible = "apple,t8010-i2c", "apple,i2c";
+ reg = <0x2 0x0a110000 0x0 0x1000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 230 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
+ i2c1: i2c@20a111000 {
+ compatible = "apple,t8010-i2c", "apple,i2c";
+ reg = <0x2 0x0a111000 0x0 0x1000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 231 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@20a112000 {
+ compatible = "apple,t8010-i2c", "apple,i2c";
+ reg = <0x2 0x0a112000 0x0 0x1000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@20a113000 {
+ compatible = "apple,t8010-i2c", "apple,i2c";
+ reg = <0x2 0x0a113000 0x0 0x1000>;
+ clocks = <&clkref>;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ power-domains = <&ps_i2c3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pmgr: power-management@20e000000 {
+ compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reg = <0x2 0xe000000 0 0x8c000>;
+ };
+
aic: interrupt-controller@20e100000 {
compatible = "apple,t8010-aic", "apple,aic";
reg = <0x2 0x0e100000 0x0 0x100000>;
#interrupt-cells = <3>;
interrupt-controller;
+ power-domains = <&ps_aic>;
};
pinctrl_ap: pinctrl@20f100000 {
compatible = "apple,t8010-pinctrl", "apple,pinctrl";
reg = <0x2 0x0f100000 0x0 0x100000>;
+ power-domains = <&ps_gpio>;
gpio-controller;
#gpio-cells = <2>;
@@ -98,11 +260,32 @@
<AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>;
+
+ i2c0_pins: i2c0-pins {
+ pinmux = <APPLE_PINMUX(211, 1)>,
+ <APPLE_PINMUX(210, 1)>;
+ };
+
+ i2c1_pins: i2c1-pins {
+ pinmux = <APPLE_PINMUX(156, 1)>,
+ <APPLE_PINMUX(155, 1)>;
+ };
+
+ i2c2_pins: i2c2-pins {
+ pinmux = <APPLE_PINMUX(58, 1)>,
+ <APPLE_PINMUX(57, 1)>;
+ };
+
+ i2c3_pins: i2c3-pins {
+ pinmux = <APPLE_PINMUX(158, 1)>,
+ <APPLE_PINMUX(157, 1)>;
+ };
};
pinctrl_aop: pinctrl@2100f0000 {
compatible = "apple,t8010-pinctrl", "apple,pinctrl";
reg = <0x2 0x100f0000 0x0 0x100000>;
+ power-domains = <&ps_aop_gpio>;
gpio-controller;
#gpio-cells = <2>;
@@ -121,6 +304,14 @@
<AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>;
};
+ pmgr_mini: power-management@210200000 {
+ compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reg = <0x2 0x10200000 0 0x84000>;
+ };
+
wdt: watchdog@2102b0000 {
compatible = "apple,t8010-wdt", "apple,wdt";
reg = <0x2 0x102b0000 0x0 0x4000>;
@@ -139,3 +330,5 @@
<AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
};
};
+
+#include "t8011-pmgr.dtsi"
generated by cgit (git 2.34.1) at 2025-12-31 17:40:00 +0000