diff options
Diffstat (limited to 'arch/arm64/boot/dts/arm/corstone1000-fvp.dts')
| -rw-r--r-- | arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index 26b0f1b3cea6..66ba6b027193 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (c) 2022, Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro Limited. All rights reserved. @@ -21,7 +21,7 @@ reg-io-width = <2>; }; - vmmc_v3_3d: fixed_v3_3d { + vmmc_v3_3d: regulator-vmmc { compatible = "regulator-fixed"; regulator-name = "vmmc_supply"; regulator-min-microvolt = <3300000>; @@ -49,3 +49,29 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; |