diff options
Diffstat (limited to 'arch/arm64/boot/dts/arm/corstone1000.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/arm/corstone1000.dtsi | 32 |
1 files changed, 14 insertions, 18 deletions
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index 21f1f952e985..f35a5c96f3da 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (c) 2022, Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro Limited. All rights reserved. @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; @@ -29,6 +29,7 @@ device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; }; @@ -43,10 +44,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x1c010000 0x1000>, - <0x1c02f000 0x2000>, - <0x1c04f000 0x1000>, - <0x1c06f000 0x2000>; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; @@ -60,14 +61,14 @@ cache-sets = <1024>; }; - refclk100mhz: refclk100mhz { + refclk100mhz: clock-100000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "apb_pclk"; }; - smbclk: refclk24mhzx2 { + smbclk: clock-48000000 { /* Reference 24MHz clock x 2 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -77,17 +78,13 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; - uartclk: uartclk { + uartclk: clock-50000000 { /* UART clock - 50MHz */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -112,7 +109,6 @@ reg = <0x1a220000 0x1000>; #address-cells = <1>; #size-cells = <1>; - clock-frequency = <50000000>; ranges; frame@1a230000 { |