diff options
Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos850.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos850.dtsi | 48 |
1 files changed, 41 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 2ba67c3d0681..cb55015c8dce 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -93,6 +93,8 @@ compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; + clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; + clock-names = "cluster0_clk"; }; cpu1: cpu@1 { device_type = "cpu"; @@ -117,6 +119,8 @@ compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; + clock-names = "cluster1_clk"; }; cpu5: cpu@101 { device_type = "cpu"; @@ -254,6 +258,28 @@ "dout_peri_uart", "dout_peri_ip"; }; + cmu_cpucl1: clock-controller@10800000 { + compatible = "samsung,exynos850-cmu-cpucl1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL1_DBG>; + clock-names = "oscclk", "dout_cpucl1_switch", + "dout_cpucl1_dbg"; + }; + + cmu_cpucl0: clock-controller@10900000 { + compatible = "samsung,exynos850-cmu-cpucl0"; + reg = <0x10900000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL0_DBG>; + clock-names = "oscclk", "dout_cpucl0_switch", + "dout_cpucl0_dbg"; + }; + cmu_g3d: clock-controller@11400000 { compatible = "samsung,exynos850-cmu-g3d"; reg = <0x11400000 0x8000>; @@ -390,6 +416,14 @@ interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; }; + trng: rng@12081400 { + compatible = "samsung,exynos850-trng"; + reg = <0x12081400 0x100>; + clocks = <&cmu_core CLK_GOUT_SSS_ACLK>, + <&cmu_core CLK_GOUT_SSS_PCLK>; + clock-names = "secss", "pclk"; + }; + pinctrl_hsi: pinctrl@13430000 { compatible = "samsung,exynos850-pinctrl"; reg = <0x13430000 0x1000>; @@ -617,7 +651,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x138200c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1010>; - samsung,mode = <USI_V2_UART>; + samsung,mode = <USI_MODE_UART>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -643,7 +677,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x138a00c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1020>; - samsung,mode = <USI_V2_I2C>; + samsung,mode = <USI_MODE_I2C>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -672,7 +706,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x138b00c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1030>; - samsung,mode = <USI_V2_I2C>; + samsung,mode = <USI_MODE_I2C>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -701,7 +735,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x138c00c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1040>; - samsung,mode = <USI_V2_I2C>; + samsung,mode = <USI_MODE_I2C>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -730,7 +764,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x139400c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1050>; - samsung,mode = <USI_V2_SPI>; + samsung,mode = <USI_MODE_SPI>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -762,7 +796,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x11d000c0 0x20>; samsung,sysreg = <&sysreg_cmgp 0x2000>; - samsung,mode = <USI_V2_I2C>; + samsung,mode = <USI_MODE_I2C>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -821,7 +855,7 @@ compatible = "samsung,exynos850-usi"; reg = <0x11d200c0 0x20>; samsung,sysreg = <&sysreg_cmgp 0x2010>; - samsung,mode = <USI_V2_I2C>; + samsung,mode = <USI_MODE_I2C>; #address-cells = <1>; #size-cells = <1>; ranges; |