diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi | 87 |
1 files changed, 84 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 5d012c95222f..7a191195dbd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -3,6 +3,63 @@ * Copyright 2019~2020, 2022 NXP */ +/delete-node/ &asrc1; +/delete-node/ &asrc1_lpcg; +/delete-node/ &adc1; +/delete-node/ &adc1_lpcg; +/delete-node/ &amix; +/delete-node/ &amix_lpcg; +/delete-node/ &edma1; +/delete-node/ &esai0; +/delete-node/ &esai0_lpcg; +/delete-node/ &sai4; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5; +/delete-node/ &sai5_lpcg; + +&acm { + compatible = "fsl,imx8dxl-acm"; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "spdif0_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk"; +}; + &audio_ipg_clk { clock-frequency = <160000000>; }; @@ -44,7 +101,8 @@ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ - <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, /* gpt3 */ + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd IMX_SC_R_DMA_0_CH0>, <&pd IMX_SC_R_DMA_0_CH1>, <&pd IMX_SC_R_DMA_0_CH2>, @@ -88,7 +146,8 @@ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; }; &edma3 { @@ -99,7 +158,8 @@ <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; }; &flexcan1 { @@ -177,3 +237,24 @@ &lpspi3 { interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; }; + +&sai0 { + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai1 { + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai2 { + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai3 { + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; +}; + +&spdif0 { + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */ + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */ +}; |