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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi110
1 files changed, 61 insertions, 49 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 6f0811587142..d29710772569 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mm.dtsi"
+#include "imx8mm-overdrive.dtsi"
/ {
chosen {
@@ -17,20 +18,6 @@
rtc1 = &snvs_rtc;
};
- backlight: backlight {
- compatible = "pwm-backlight";
- brightness-levels = <0 45 63 88 119 158 203 255>;
- default-brightness-level = <4>;
- /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
- enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
- power-supply = <&reg_3p3v>;
- /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
- pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
- status = "disabled";
- };
-
/* Fixed clock dedicated to SPI CAN controller */
clk40m: oscillator {
compatible = "fixed-clock";
@@ -65,13 +52,6 @@
status = "disabled";
};
- panel_lvds: panel-lvds {
- compatible = "panel-lvds";
- backlight = <&backlight>;
- data-mapping = "vesa-24";
- status = "disabled";
- };
-
/* Carrier Board Supplies */
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
@@ -110,6 +90,22 @@
startup-delay-us = <200000>;
};
+ /*
+ * By default we enable CTRL_SLEEP_MOCI#, this is required to have
+ * peripherals on the carrier board powered.
+ * If more granularity or power saving is required this can be disabled
+ * in the carrier board device tree files.
+ */
+ reg_force_sleep_moci: regulator-force-sleep-moci {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "CTRL_SLEEP_MOCI#";
+ };
+
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
enable-active-high;
@@ -145,7 +141,20 @@
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SD";
- startup-delay-us = <2000>;
+ startup-delay-us = <20000>;
+ };
+
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vsel>;
+ gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ regulator-name = "PMIC_USDHC_VSELECT";
+ vin-supply = <&reg_nvcc_sd>;
};
reserved-memory {
@@ -211,15 +220,16 @@
pinctrl-0 = <&pinctrl_ecspi2>;
};
-/* Verdin CAN_1 (On-module) */
+/* On-module SPI */
&ecspi3 {
#address-cells = <1>;
#size-cells = <0>;
- cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi3>;
+ pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>;
status = "okay";
+ /* Verdin CAN_1 */
can1: can@0 {
compatible = "microchip,mcp251xfd";
clocks = <&clk40m>;
@@ -229,6 +239,12 @@
reg = <0>;
spi-max-frequency = <8500000>;
};
+
+ verdin_som_tpm: tpm@1 {
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
/* Verdin ETH_1 (On-module PHY) */
@@ -266,7 +282,7 @@
"SODIMM_19",
"",
"",
- "",
+ "PMIC_USDHC_VSELECT",
"",
"",
"",
@@ -333,16 +349,6 @@
"SODIMM_212",
"SODIMM_151",
"SODIMM_153";
-
- ctrl-sleep-moci-hog {
- gpio-hog;
- /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
- gpios = <1 GPIO_ACTIVE_HIGH>;
- line-name = "CTRL_SLEEP_MOCI#";
- output-high;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
- };
};
/* On-module I2C */
@@ -353,6 +359,7 @@
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
status = "okay";
pca9450: pmic@25 {
@@ -469,11 +476,12 @@
reg = <0x32>;
};
- adc@49 {
+ verdin_som_adc: adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
+ #io-channel-cells = <1>;
/* Verdin I2C_1 (ADC_4 - ADC_3) */
channel@0 {
@@ -533,7 +541,7 @@
};
eeprom@50 {
- compatible = "st,24c02";
+ compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
};
@@ -541,12 +549,13 @@
/* Verdin I2C_2_DSI */
&i2c2 {
- clock-frequency = <10000>;
+ clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
status = "disabled";
};
@@ -560,6 +569,7 @@
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
};
/* Verdin I2C_1 */
@@ -570,6 +580,7 @@
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
gpio_expander_21: gpio-expander@21 {
compatible = "nxp,pcal6416";
@@ -635,7 +646,7 @@
/* EEPROM on display adapter (MIPI DSI Display Adapter) */
eeprom_display_adapter: eeprom@50 {
- compatible = "st,24c02";
+ compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x50>;
status = "disabled";
@@ -643,7 +654,7 @@
/* EEPROM on carrier board */
eeprom_carrier_board: eeprom@57 {
- compatible = "st,24c02";
+ compatible = "st,24c02", "atmel,24c02";
pagesize = <16>;
reg = <0x57>;
status = "disabled";
@@ -787,6 +798,7 @@
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
vmmc-supply = <&reg_usdhc2_vmmc>;
+ vqmmc-supply = <&reg_usdhc2_vqmmc>;
};
&wdog1 {
@@ -801,8 +813,7 @@
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>,
- <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>,
- <&pinctrl_pmic_tpm_ena>;
+ <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
pinctrl_can1_int: can1intgrp {
fsl,pins =
@@ -929,7 +940,7 @@
/* Verdin GPIO_9_DSI (pulled-up as active-low) */
pinctrl_gpio_9_dsi: gpio9dsigrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
+ <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */
};
/* Verdin GPIO_10_DSI (pulled-up as active-low) */
@@ -1104,7 +1115,7 @@
};
/* control signal for optional ATTPM20P or SE050 */
- pinctrl_pmic_tpm_ena: pmictpmenagrp {
+ pinctrl_tpm_spi_cs: tpmspicsgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
};
@@ -1209,13 +1220,17 @@
<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
};
+ pinctrl_usdhc2_vsel: usdhc2vselgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */
+ };
+
/*
* Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
* on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
*/
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
@@ -1226,7 +1241,6 @@
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
@@ -1237,7 +1251,6 @@
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
@@ -1249,7 +1262,6 @@
/* Avoid backfeeding with removed card power */
pinctrl_usdhc2_sleep: usdhc2slpgrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
generated by cgit (git 2.34.1) at 2025-07-23 13:28:15 +0000