diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index cae586cd45bd..6daa2313f879 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -9,6 +9,7 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/net/ti-dp83867.h> #include "imx8mp.dtsi" @@ -24,6 +25,8 @@ ethernet4 = &lan3; ethernet5 = &lan4; ethernet6 = &lan5; + rtc0 = &gsc_rtc; + rtc1 = &snvs_rtc; }; chosen { @@ -225,6 +228,29 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; }; }; @@ -275,7 +301,7 @@ &gpio3 { gpio-line-names = "", "", "", "", "", "", "m2_rst", "", - "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "m2_gpio10", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -404,6 +430,12 @@ label = "vdd_dram"; }; + channel@9e { + gw,mode = <2>; + reg = <0x9e>; + label = "vdd_1p0"; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; @@ -451,7 +483,7 @@ pagesize = <16>; }; - rtc@68 { + gsc_rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; @@ -786,6 +818,7 @@ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ |