diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8qxp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 104 |
1 files changed, 95 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 1e6b4995091e..7c4a50e0ec9e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,6 +46,12 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + spi0 = &lpspi0; + spi1 = &lpspi1; + spi2 = &lpspi2; + spi3 = &lpspi3; + vpu-core0 = &vpu_core0; + vpu-core1 = &vpu_core1; }; cpus { @@ -58,6 +64,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -69,6 +81,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -80,6 +98,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x2>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -91,6 +115,12 @@ compatible = "arm,cortex-a35"; reg = <0x0 0x3>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&A35_L2>; clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; @@ -99,6 +129,11 @@ A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; @@ -124,6 +159,7 @@ compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -134,14 +170,35 @@ #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; + status = "disabled"; + }; + + encoder_rpc: encoder-rpc@94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; }; }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; @@ -150,7 +207,7 @@ method = "smc"; }; - scu { + system-controller { compatible = "fsl,imx-scu"; mbox-names = "tx0", "rx0", @@ -159,34 +216,46 @@ &lsio_mu1 1 0 &lsio_mu1 3 3>; - pd: imx8qx-pd { + pd: power-controller { compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; }; clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; #clock-cells = <2>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; }; iomuxc: pinctrl { compatible = "fsl,imx8qxp-iomuxc"; }; - ocotp: imx8qx-ocotp { + ocotp: ocotp { compatible = "fsl,imx8qxp-scu-ocotp"; #address-cells = <1>; #size-cells = <1>; + + fec_mac0: mac@2c4 { + reg = <0x2c4 6>; + }; + + fec_mac1: mac@2c6 { + reg = <0x2c6 6>; + }; }; - scu_key: scu-key { + scu_key: keys { compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; linux,keycodes = <KEY_POWER>; + wakeup-source; status = "disabled"; }; + scu_reset: reset-controller { + compatible = "fsl,imx-scu-reset"; + #reset-cells = <1>; + }; + rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; @@ -210,6 +279,13 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + xtal32k: clock-xtal32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -225,7 +301,7 @@ }; thermal_zones: thermal-zones { - cpu-thermal0 { + cpu0-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; @@ -258,12 +334,22 @@ }; /* sorted in register address */ + #include "imx8-ss-img.dtsi" + #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-security.dtsi" + #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" + #include "imx8-ss-hsio.dtsi" }; +#include "imx8qxp-ss-img.dtsi" +#include "imx8qxp-ss-vpu.dtsi" +#include "imx8qxp-ss-security.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi" +#include "imx8qxp-ss-hsio.dtsi" |