diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32g2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32g2.dtsi | 674 |
1 files changed, 673 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index d8c82da88ca0..51d00dac12de 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2017-2021 NXP + * Copyright 2017-2021, 2024-2025 NXP */ #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -14,6 +14,18 @@ #address-cells = <2>; #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_buf: shm@d0000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd0000000 0x0 0x80>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -53,11 +65,13 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -75,6 +89,19 @@ }; firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_buf>; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -87,6 +114,335 @@ #size-cells = <1>; ranges = <0 0 0 0x80000000>; + rtc0: rtc@40060000 { + compatible = "nxp,s32g2-rtc"; + reg = <0x40060000 0x1000>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 54>, <&clks 55>; + clock-names = "ipg", "source0"; + }; + + pinctrl: pinctrl@4009c240 { + compatible = "nxp,s32g2-siul2-pinctrl"; + /* MSCR0-MSCR101 registers on siul2_0 */ + reg = <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + + jtag_pins: jtag-pins { + jtag-grp0 { + pinmux = <0x0>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + + jtag-grp1 { + pinmux = <0x11>; + slew-rate = <166>; + }; + + jtag-grp2 { + pinmux = <0x40>; + input-enable; + bias-pull-down; + slew-rate = <166>; + }; + + jtag-grp3 { + pinmux = <0x23c0>, + <0x23d0>, + <0x2320>; + }; + + jtag-grp4 { + pinmux = <0x51>; + input-enable; + bias-pull-up; + slew-rate = <166>; + }; + }; + + pinctrl_usdhc0: usdhc0grp-pins { + usdhc0-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <150>; + }; + + usdhc0-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <150>; + }; + + usdhc0-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <150>; + }; + + usdhc0-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <150>; + }; + + usdhc0-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + + pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins { + usdhc0-100mhz-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <150>; + }; + + usdhc0-100mhz-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + + pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins { + usdhc0-200mhz-grp0 { + pinmux = <0x2e1>, + <0x381>; + output-enable; + bias-pull-down; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp1 { + pinmux = <0x2f1>, + <0x301>, + <0x311>, + <0x321>, + <0x331>, + <0x341>, + <0x351>, + <0x361>, + <0x371>; + output-enable; + input-enable; + bias-pull-up; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp2 { + pinmux = <0x391>; + output-enable; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp3 { + pinmux = <0x3a0>; + input-enable; + slew-rate = <208>; + }; + + usdhc0-200mhz-grp4 { + pinmux = <0x2032>, + <0x2042>, + <0x2052>, + <0x2062>, + <0x2072>, + <0x2082>, + <0x2092>, + <0x20a2>, + <0x20b2>, + <0x20c2>; + }; + }; + }; + + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + + swt0: watchdog@40100000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt1: watchdog@40104000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40104000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt2: watchdog@40108000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40108000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible = "nxp,s32g2-swt"; + reg = <0x4010c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm0: timer@4011c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm1: timer@40120000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40120000 0x3000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm2: timer@40124000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40124000 0x3000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm3: timer@40128000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40128000 0x3000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + edma0: dma-controller@40144000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can0: can@401b4000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -103,6 +459,195 @@ status = "disabled"; }; + usbmisc: usbmisc@44064200 { + #index-cells = <1>; + compatible = "nxp,s32g2-usbmisc"; + reg = <0x44064200 0x200>; + }; + + usbotg: usb@44064000 { + compatible = "nxp,s32g2-usb"; + reg = <0x44064000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ + clocks = <&clks 94>, <&clks 95>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x3>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + phy_type = "ulpi"; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "disabled"; + }; + + spi0: spi@401d4000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401d4000 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <8>; + bus-num = <0>; + dmas = <&edma0 0 7>, <&edma0 0 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@401d8000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401d8000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <1>; + dmas = <&edma0 0 10>, <&edma0 0 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@401dc000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401dc000 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <2>; + dmas = <&edma0 0 13>, <&edma0 0 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + swt4: watchdog@40200000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40200000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt5: watchdog@40204000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40204000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt6: watchdog@40208000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40208000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm4: timer@4021c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4021c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm5: timer@40220000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40220000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + stm6: timer@40224000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40224000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + edma1: dma-controller@40244000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can2: can@402a8000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -111,6 +656,133 @@ status = "disabled"; }; + spi3: spi@402c8000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402c8000 0x1000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <3>; + dmas = <&edma0 1 7>, <&edma0 1 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@402cc000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402cc000 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <4>; + dmas = <&edma0 1 10>, <&edma0 1 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@402d0000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402d0000 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <5>; + dmas = <&edma0 1 13>, <&edma0 1 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + usdhc0: mmc@402f0000 { + compatible = "nxp,s32g2-usdhc"; + reg = <0x402f0000 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 32>, <&clks 31>, <&clks 33>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + + gmac0: ethernet@4033c000 { + compatible = "nxp,s32g2-dwmac"; + reg = <0x4033c000 0x2000>, /* gmac IP */ + <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + }; + + queue1 { + }; + + queue2 { + }; + + queue3 { + }; + + queue4 { + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + }; + + queue1 { + }; + + queue2 { + }; + + queue3 { + }; + + queue4 { + }; + }; + + gmac0mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; reg = <0x50800000 0x10000>, |