summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/s32g3.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32g3.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/s32g3.dtsi586
1 files changed, 586 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
new file mode 100644
index 000000000000..991dbfbfa203
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -0,0 +1,586 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2021-2024 NXP
+ *
+ * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
+ * Ciprian Costea <ciprianmarian.costea@nxp.com>
+ * Andra-Teodora Ilie <andra.ilie@nxp.com>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "nxp,s32g3";
+ interrupt-parent = <&gic>;
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ clocks = <&dfs 0>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&scmi_shmem>;
+ arm,smc-id = <0xc20000fe>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ clks: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scmi_shmem: shm@d0000000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0xd0000000 0x0 0x80>;
+ no-map;
+ };
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x80000000>;
+
+ pinctrl: pinctrl@4009c240 {
+ compatible = "nxp,s32g2-siul2-pinctrl";
+ /* MSCR0-MSCR101 registers on siul2_0 */
+ reg = <0x4009c240 0x198>,
+ /* MSCR112-MSCR122 registers on siul2_1 */
+ <0x44010400 0x2c>,
+ /* MSCR144-MSCR190 registers on siul2_1 */
+ <0x44010480 0xbc>,
+ /* IMCR0-IMCR83 registers on siul2_0 */
+ <0x4009ca40 0x150>,
+ /* IMCR119-IMCR397 registers on siul2_1 */
+ <0x44010c1c 0x45c>,
+ /* IMCR430-IMCR495 registers on siul2_1 */
+ <0x440110f8 0x108>;
+
+ jtag_pins: jtag-pins {
+ jtag-grp0 {
+ pinmux = <0x0>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+
+ jtag-grp1 {
+ pinmux = <0x11>;
+ slew-rate = <166>;
+ };
+
+ jtag-grp2 {
+ pinmux = <0x40>;
+ input-enable;
+ bias-pull-down;
+ slew-rate = <166>;
+ };
+
+ jtag-grp3 {
+ pinmux = <0x23c0>,
+ <0x23d0>,
+ <0x2320>;
+ };
+
+ jtag-grp4 {
+ pinmux = <0x51>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+ };
+
+ pinctrl_usdhc0: usdhc0grp-pins {
+ usdhc0-grp0 {
+ pinmux = <0x2e1>,
+ <0x381>;
+ output-enable;
+ bias-pull-down;
+ slew-rate = <150>;
+ };
+
+ usdhc0-grp1 {
+ pinmux = <0x2f1>,
+ <0x301>,
+ <0x311>,
+ <0x321>,
+ <0x331>,
+ <0x341>,
+ <0x351>,
+ <0x361>,
+ <0x371>;
+ output-enable;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <150>;
+ };
+
+ usdhc0-grp2 {
+ pinmux = <0x391>;
+ output-enable;
+ slew-rate = <150>;
+ };
+
+ usdhc0-grp3 {
+ pinmux = <0x3a0>;
+ input-enable;
+ slew-rate = <150>;
+ };
+
+ usdhc0-grp4 {
+ pinmux = <0x2032>,
+ <0x2042>,
+ <0x2052>,
+ <0x2062>,
+ <0x2072>,
+ <0x2082>,
+ <0x2092>,
+ <0x20a2>,
+ <0x20b2>,
+ <0x20c2>;
+ };
+ };
+
+ pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
+ usdhc0-100mhz-grp0 {
+ pinmux = <0x2e1>,
+ <0x381>;
+ output-enable;
+ bias-pull-down;
+ slew-rate = <150>;
+ };
+
+ usdhc0-100mhz-grp1 {
+ pinmux = <0x2f1>,
+ <0x301>,
+ <0x311>,
+ <0x321>,
+ <0x331>,
+ <0x341>,
+ <0x351>,
+ <0x361>,
+ <0x371>;
+ output-enable;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <150>;
+ };
+
+ usdhc0-100mhz-grp2 {
+ pinmux = <0x391>;
+ output-enable;
+ slew-rate = <150>;
+ };
+
+ usdhc0-100mhz-grp3 {
+ pinmux = <0x3a0>;
+ input-enable;
+ slew-rate = <150>;
+ };
+
+ usdhc0-100mhz-grp4 {
+ pinmux = <0x2032>,
+ <0x2042>,
+ <0x2052>,
+ <0x2062>,
+ <0x2072>,
+ <0x2082>,
+ <0x2092>,
+ <0x20a2>,
+ <0x20b2>,
+ <0x20c2>;
+ };
+ };
+
+ pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
+ usdhc0-200mhz-grp0 {
+ pinmux = <0x2e1>,
+ <0x381>;
+ output-enable;
+ bias-pull-down;
+ slew-rate = <208>;
+ };
+
+ usdhc0-200mhz-grp1 {
+ pinmux = <0x2f1>,
+ <0x301>,
+ <0x311>,
+ <0x321>,
+ <0x331>,
+ <0x341>,
+ <0x351>,
+ <0x361>,
+ <0x371>;
+ output-enable;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <208>;
+ };
+
+ usdhc0-200mhz-grp2 {
+ pinmux = <0x391>;
+ output-enable;
+ slew-rate = <208>;
+ };
+
+ usdhc0-200mhz-grp3 {
+ pinmux = <0x3a0>;
+ input-enable;
+ slew-rate = <208>;
+ };
+
+ usdhc0-200mhz-grp4 {
+ pinmux = <0x2032>,
+ <0x2042>,
+ <0x2052>,
+ <0x2062>,
+ <0x2072>,
+ <0x2082>,
+ <0x2092>,
+ <0x20a2>,
+ <0x20b2>,
+ <0x20c2>;
+ };
+ };
+ };
+
+ edma0: dma-controller@40144000 {
+ compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
+ reg = <0x40144000 0x24000>,
+ <0x4012c000 0x3000>,
+ <0x40130000 0x3000>;
+ #dma-cells = <2>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-0-15",
+ "tx-16-31",
+ "err";
+ clocks = <&clks 63>, <&clks 64>;
+ clock-names = "dmamux0", "dmamux1";
+ };
+
+ can0: can@401b4000 {
+ compatible = "nxp,s32g3-flexcan",
+ "nxp,s32g2-flexcan";
+ reg = <0x401b4000 0xa000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mb-0", "state", "berr", "mb-1";
+ clocks = <&clks 9>, <&clks 11>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can1: can@401be000 {
+ compatible = "nxp,s32g3-flexcan",
+ "nxp,s32g2-flexcan";
+ reg = <0x401be000 0xa000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mb-0", "state", "berr", "mb-1";
+ clocks = <&clks 9>, <&clks 11>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart0: serial@401c8000 {
+ compatible = "nxp,s32g3-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0x401c8000 0x3000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart1: serial@401cc000 {
+ compatible = "nxp,s32g3-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0x401cc000 0x3000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@401e4000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401e4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c1: i2c@401e8000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401e8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c2: i2c@401ec000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401ec000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ edma1: dma-controller@40244000 {
+ compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
+ reg = <0x40244000 0x24000>,
+ <0x4022c000 0x3000>,
+ <0x40230000 0x3000>;
+ #dma-cells = <2>;
+ dma-channels = <32>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx-0-15",
+ "tx-16-31",
+ "err";
+ clocks = <&clks 63>, <&clks 64>;
+ clock-names = "dmamux0", "dmamux1";
+ };
+
+ can2: can@402a8000 {
+ compatible = "nxp,s32g3-flexcan",
+ "nxp,s32g2-flexcan";
+ reg = <0x402a8000 0xa000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mb-0", "state", "berr", "mb-1";
+ clocks = <&clks 9>, <&clks 11>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ can3: can@402b2000 {
+ compatible = "nxp,s32g3-flexcan",
+ "nxp,s32g2-flexcan";
+ reg = <0x402b2000 0xa000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mb-0", "state", "berr", "mb-1";
+ clocks = <&clks 9>, <&clks 11>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+
+ uart2: serial@402bc000 {
+ compatible = "nxp,s32g3-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0x402bc000 0x3000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@402d8000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x402d8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c4: i2c@402dc000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x402dc000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ usdhc0: mmc@402f0000 {
+ compatible = "nxp,s32g3-usdhc",
+ "nxp,s32g2-usdhc";
+ reg = <0x402f0000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 32>,
+ <&clks 31>,
+ <&clks 33>;
+ clock-names = "ipg", "ahb", "per";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@50800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x50800000 0x10000>,
+ <0x50900000 0x200000>,
+ <0x50400000 0x2000>,
+ <0x50410000 0x2000>,
+ <0x50420000 0x2000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
+ arm,no-tick-in-suspend;
+ };
+};
generated by cgit (git 2.34.1) at 2025-07-23 13:26:30 +0000