diff options
Diffstat (limited to 'arch/arm64/boot/dts/hisilicon/hi6220.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index dde9371dc545..f8b56d443850 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -186,14 +186,18 @@ CLUSTER0_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -405,7 +409,7 @@ compatible = "pinctrl-single"; reg = <0x0 0xf7010000 0x0 0x27c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; #gpio-range-cells = <3>; pinctrl-single,register-width = <32>; @@ -444,7 +448,7 @@ compatible = "pinconf-single"; reg = <0x0 0xf7010800 0x0 0x28c>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; @@ -453,7 +457,7 @@ compatible = "pinconf-single"; reg = <0x0 0xf8001800 0x0 0x78>; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; }; @@ -723,8 +727,6 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x0 0xf7106000 0x0 0x1000>; interrupts = <0 50 4>; - bus-id = <0>; - enable-dma = <0>; clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>; clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; @@ -840,7 +842,7 @@ }; watchdog0: watchdog@f8005000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xf8005000 0x0 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ao_ctrl HI6220_WDT0_PCLK>, @@ -848,7 +850,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - tsensor: tsensor@0,f7030700 { + tsensor: tsensor@f7030700 { compatible = "hisilicon,tsensor"; reg = <0x0 0xf7030700 0x0 0x1000>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -857,7 +859,7 @@ #thermal-sensor-cells = <1>; }; - i2s0: i2s@f7118000{ + i2s0: i2s@f7118000 { compatible = "hisilicon,hi6210-i2s"; reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ @@ -1028,17 +1030,17 @@ compatible = "hisilicon,hi6220-mali", "arm,mali-450"; reg = <0x0 0xf4080000 0x0 0x00040000>; interrupt-parent = <&gic>; - interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", |