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Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8173.dtsi')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi112
1 files changed, 58 insertions, 54 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 22f271b1f5b0..122a57c3780b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1,14 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: Eddie Huang <eddie.huang@mediatek.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <dt-bindings/clock/mt8173-clk.h>
@@ -57,7 +50,7 @@
serial3 = &uart3;
};
- cluster0_opp: opp_table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
@@ -94,7 +87,7 @@
};
};
- cluster1_opp: opp_table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
opp-507000000 {
@@ -229,14 +222,14 @@
};
};
- pmu_a53 {
+ pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- pmu_a72 {
+ pmu-a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
@@ -246,9 +239,9 @@
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
};
clk26m: oscillator0 {
@@ -273,7 +266,7 @@
};
thermal-zones {
- cpu_thermal: cpu_thermal {
+ cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
@@ -293,7 +286,7 @@
type = "passive";
};
- cpu_crit: cpu_crit0 {
+ cpu_crit: cpu-crit0 {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
@@ -325,7 +318,15 @@
#address-cells = <2>;
#size-cells = <2>;
ranges;
- vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
+
+ afe_dma_mem: audio-dma-pool {
+ compatible = "shared-dma-pool";
+ size = <0 0x100000>;
+ alignment = <0 0x10>;
+ no-map;
+ };
+
+ vpu_dma_reserved: vpu-dma-mem@b7000000 {
compatible = "shared-dma-pool";
reg = <0 0xb7000000 0 0x500000>;
alignment = <0x1000>;
@@ -359,21 +360,21 @@
#clock-cells = <1>;
};
- infracfg: power-controller@10001000 {
+ infracfg: clock-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- pericfg: power-controller@10003000 {
+ pericfg: clock-controller@10003000 {
compatible = "mediatek,mt8173-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- syscfg_pctl_a: syscfg_pctl_a@10005000 {
+ syscfg_pctl_a: syscon@10005000 {
compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
@@ -382,7 +383,6 @@
compatible = "mediatek,mt8173-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -451,9 +451,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
@@ -504,7 +503,7 @@
reg = <MT8173_POWER_DOMAIN_USB>;
#power-domain-cells = <0>;
};
- power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
+ mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&clk26m>;
clock-names = "mfg";
@@ -573,7 +572,7 @@
memory-region = <&vpu_dma_reserved>;
};
- sysirq: intpol-controller@10200620 {
+ sysirq: interrupt-controller@10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
@@ -588,8 +587,9 @@
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb4 &larb5>;
+ mediatek,infracfg = <&infracfg>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>;
};
@@ -598,6 +598,15 @@
reg = <0 0x10206000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ socinfo-data1@40 {
+ reg = <0x040 0x4>;
+ };
+
+ socinfo-data2@44 {
+ reg = <0x044 0x4>;
+ };
+
thermal_calibration: calib@528 {
reg = <0x528 0xc>;
};
@@ -790,9 +799,12 @@
nor_flash: spi@1100d000 {
compatible = "mediatek,mt8173-nor";
reg = <0 0x1100d000 0 0xe0>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
+ assigned-clock-parents = <&clk26m>;
clocks = <&pericfg CLK_PERI_SPI>,
- <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
- clock-names = "spi", "sf";
+ <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
+ <&pericfg CLK_PERI_NFI>;
+ clock-names = "spi", "sf", "axi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -883,6 +895,7 @@
<&topckgen CLK_TOP_AUD_2_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
<&topckgen CLK_TOP_APLL2>;
+ memory-region = <&afe_dma_mem>;
};
mmc0: mmc@11230000 {
@@ -996,6 +1009,7 @@
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
@@ -1009,7 +1023,6 @@
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,vpu = <&vpu>;
};
@@ -1020,7 +1033,6 @@
<&mmsys CLK_MM_MUTEX_32K>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- mediatek,larb = <&larb4>;
};
mdp_rsz0: rsz@14003000 {
@@ -1050,7 +1062,6 @@
clocks = <&mmsys CLK_MM_MDP_WDMA>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WDMA>;
- mediatek,larb = <&larb0>;
};
mdp_wrot0: wrot@14007000 {
@@ -1059,7 +1070,6 @@
clocks = <&mmsys CLK_MM_MDP_WROT0>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
- mediatek,larb = <&larb0>;
};
mdp_wrot1: wrot@14008000 {
@@ -1068,7 +1078,6 @@
clocks = <&mmsys CLK_MM_MDP_WROT1>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
iommus = <&iommu M4U_PORT_MDP_WROT1>;
- mediatek,larb = <&larb4>;
};
ovl0: ovl@1400c000 {
@@ -1078,7 +1087,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL0>;
iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
};
@@ -1089,7 +1097,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_OVL1>;
iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
};
@@ -1100,7 +1107,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
};
@@ -1111,7 +1117,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
@@ -1122,7 +1127,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
@@ -1133,7 +1137,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
@@ -1144,7 +1147,6 @@
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
@@ -1211,6 +1213,7 @@
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
};
dsi0: dsi@1401b000 {
@@ -1222,6 +1225,7 @@
<&mmsys CLK_MM_DSI0_DIGITAL>,
<&mipi_tx0>;
clock-names = "engine", "digital", "hs";
+ resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
@@ -1260,8 +1264,7 @@
};
pwm0: pwm@1401e000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
+ compatible = "mediatek,mt8173-disp-pwm";
reg = <0 0x1401e000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&mmsys CLK_MM_DISP_PWM026M>,
@@ -1271,8 +1274,7 @@
};
pwm1: pwm@1401f000 {
- compatible = "mediatek,mt8173-disp-pwm",
- "mediatek,mt6595-disp-pwm";
+ compatible = "mediatek,mt8173-disp-pwm";
reg = <0 0x1401f000 0 0x1000>;
#pwm-cells = <2>;
clocks = <&mmsys CLK_MM_DISP_PWM126M>,
@@ -1287,6 +1289,7 @@
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
};
@@ -1314,6 +1317,7 @@
compatible = "mediatek,mt8173-disp-od";
reg = <0 0x14023000 0 0x1000>;
clocks = <&mmsys CLK_MM_DISP_OD>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
};
hdmi0: hdmi@14025000 {
@@ -1380,10 +1384,9 @@
#clock-cells = <1>;
};
- vcodec_dec: vcodec@16000000 {
+ vcodec_dec: vcodec@16020000 {
compatible = "mediatek,mt8173-vcodec-dec";
- reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
- <0 0x16020000 0 0x1000>, /* VDEC_MISC */
+ reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */
<0 0x16021000 0 0x800>, /* VDEC_LD */
<0 0x16021800 0 0x800>, /* VDEC_TOP */
<0 0x16022000 0 0x1000>, /* VDEC_CM */
@@ -1394,8 +1397,9 @@
<0 0x16027000 0 0x800>, /* VDEC_HWQ */
<0 0x16027800 0 0x800>, /* VDEC_HWB */
<0 0x16028400 0 0x400>; /* VDEC_HWG */
+ reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
+ "hwd", "hwq", "hwb", "hwg";
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb1>;
iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
@@ -1405,6 +1409,7 @@
<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
mediatek,vpu = <&vpu>;
+ mediatek,vdecsys = <&vdecsys>;
power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
@@ -1463,7 +1468,6 @@
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1480,6 +1484,7 @@
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
};
jpegdec: jpegdec@18004000 {
@@ -1491,7 +1496,6 @@
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
- mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
<&iommu M4U_PORT_JPGDEC_BSDMA>;
};
@@ -1514,7 +1518,7 @@
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
- reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
@@ -1525,13 +1529,13 @@
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
- mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents =
<&topckgen CLK_TOP_VCODECPLL_370P5>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
};
};
};
generated by cgit (git 2.34.1) at 2026-01-05 04:45:11 +0000