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-rw-r--r--arch/arm64/boot/dts/mediatek/mt8188.dtsi2687
1 files changed, 2643 insertions, 44 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index b4315c9214dc..202478407727 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -8,9 +8,14 @@
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
+#include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>
+#include <dt-bindings/reset/mt8188-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8188";
@@ -18,6 +23,39 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ dp-intf0 = &dp_intf0;
+ dp-intf1 = &dp_intf1;
+ dsc0 = &dsc0;
+ ethdr0 = &ethdr0;
+ gce0 = &gce0;
+ gce1 = &gce1;
+ merge0 = &merge0;
+ merge1 = &merge1;
+ merge2 = &merge2;
+ merge3 = &merge3;
+ merge4 = &merge4;
+ merge5 = &merge5;
+ mutex0 = &mutex0;
+ mutex1 = &mutex1;
+ padding0 = &padding0;
+ padding1 = &padding1;
+ padding2 = &padding2;
+ padding3 = &padding3;
+ padding4 = &padding4;
+ padding5 = &padding5;
+ padding6 = &padding6;
+ padding7 = &padding7;
+ vdo1-rdma0 = &vdo1_rdma0;
+ vdo1-rdma1 = &vdo1_rdma1;
+ vdo1-rdma2 = &vdo1_rdma2;
+ vdo1-rdma3 = &vdo1_rdma3;
+ vdo1-rdma4 = &vdo1_rdma4;
+ vdo1-rdma5 = &vdo1_rdma5;
+ vdo1-rdma6 = &vdo1_rdma6;
+ vdo1-rdma7 = &vdo1_rdma7;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -37,6 +75,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -55,6 +94,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -73,6 +113,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -91,6 +132,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -109,6 +151,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -127,6 +170,7 @@
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
+ performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
@@ -145,6 +189,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
#cooling-cells = <2>;
};
@@ -163,6 +208,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
+ performance-domains = <&performance 1>;
#cooling-cells = <2>;
};
@@ -293,6 +339,112 @@
clock-output-names = "clk32k";
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-390000000 {
+ opp-hz = /bits/ 64 <390000000>;
+ opp-microvolt = <575000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-431000000 {
+ opp-hz = /bits/ 64 <431000000>;
+ opp-microvolt = <587500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-473000000 {
+ opp-hz = /bits/ 64 <473000000>;
+ opp-microvolt = <600000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-515000000 {
+ opp-hz = /bits/ 64 <515000000>;
+ opp-microvolt = <612500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-556000000 {
+ opp-hz = /bits/ 64 <556000000>;
+ opp-microvolt = <625000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <637500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-640000000 {
+ opp-hz = /bits/ 64 <640000000>;
+ opp-microvolt = <650000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-microvolt = <662500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <675000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-730000000 {
+ opp-hz = /bits/ 64 <730000000>;
+ opp-microvolt = <687500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-760000000 {
+ opp-hz = /bits/ 64 <760000000>;
+ opp-microvolt = <700000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-790000000 {
+ opp-hz = /bits/ 64 <790000000>;
+ opp-microvolt = <712500>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-835000000 {
+ opp-hz = /bits/ 64 <835000000>;
+ opp-microvolt = <731250>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-880000000 {
+ opp-hz = /bits/ 64 <880000000>;
+ opp-microvolt = <750000>;
+ opp-supported-hw = <0xff>;
+ };
+ opp-915000000 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-microvolt = <775000>;
+ opp-supported-hw = <0x8f>;
+ };
+ opp-915000000-5 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-microvolt = <762500>;
+ opp-supported-hw = <0x30>;
+ };
+ opp-915000000-6 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-microvolt = <750000>;
+ opp-supported-hw = <0x70>;
+ };
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <800000>;
+ opp-supported-hw = <0x8f>;
+ };
+ opp-950000000-5 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <775000>;
+ opp-supported-hw = <0x30>;
+ };
+ opp-950000000-6 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <750000>;
+ opp-supported-hw = <0x70>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
@@ -310,6 +462,455 @@
method = "smc";
};
+ sound: sound {
+ mediatek,platform = <&afe>;
+ status = "disabled";
+ };
+
+ thermal_zones: thermal-zones {
+ cpu-little0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <150>;
+ thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
+
+ trips {
+ cpu_little0_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_little0_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_little0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_little0_cooling_map0: map0 {
+ trip = <&cpu_little0_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-little1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <150>;
+ thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
+
+ trips {
+ cpu_little1_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_little1_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_little1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_little1_cooling_map0: map0 {
+ trip = <&cpu_little1_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-little2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <150>;
+ thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
+
+ trips {
+ cpu_little2_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_little2_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_little2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_little2_cooling_map0: map0 {
+ trip = <&cpu_little2_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-little3-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <150>;
+ thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
+
+ trips {
+ cpu_little3_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_little3_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_little3_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu_little3_cooling_map0: map0 {
+ trip = <&cpu_little3_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-big0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
+
+ trips {
+ cpu_big0_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_big0_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_big0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_big0_alert0>;
+ cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-big1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
+
+ trips {
+ cpu_big1_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_big1_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_big1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_big1_alert0>;
+ cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ apu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_APU>;
+
+ trips {
+ apu_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ apu_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ apu_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
+
+ trips {
+ gpu_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
+
+ trips {
+ gpu1_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu1_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ adsp-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
+
+ trips {
+ soc_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ soc_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ vdo-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
+
+ trips {
+ soc1_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc1_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ soc1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ infra-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
+
+ trips {
+ soc2_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc2_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ soc2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cam1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
+
+ trips {
+ cam1_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cam1_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cam1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cam2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
+
+ trips {
+ cam2_alert0: trip-alert0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cam2_alert1: trip-alert1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cam2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
@@ -324,8 +925,15 @@
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
+ dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
ranges;
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
@@ -357,6 +965,7 @@
compatible = "mediatek,mt8188-infracfg-ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
pericfg: syscon@10003000 {
@@ -383,6 +992,331 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8188-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
+ reg = <MT8188_POWER_DOMAIN_MFG0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
+ reg = <MT8188_POWER_DOMAIN_MFG1>;
+ clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
+ <&topckgen CLK_TOP_MFG_CORE_TMP>;
+ clock-names = "mfg", "alt";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_MFG2 {
+ reg = <MT8188_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_MFG3 {
+ reg = <MT8188_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_MFG4 {
+ reg = <MT8188_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
+ reg = <MT8188_POWER_DOMAIN_VPPSYS0>;
+ clocks = <&topckgen CLK_TOP_VPP>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_IMG>,
+ <&topckgen CLK_TOP_VENC>,
+ <&topckgen CLK_TOP_VDEC>,
+ <&topckgen CLK_TOP_WPE_VPP>,
+ <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>,
+ <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>,
+ <&vppsys0 CLK_VPP0_SMI_IOMMU>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+ <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "top", "cam", "ccu", "img", "venc",
+ "vdec", "wpe", "cfgck", "cfgxo",
+ "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
+ "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
+ "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
+ "ss-sram-rdr", "ss-iommu", "ss-imgcam",
+ "ss-emi", "ss-subcmn-rdr", "ss-rsi",
+ "ss-cmn-l4", "ss-vdec1", "ss-wpe",
+ "ss-cvdo-ve1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
+ reg = <MT8188_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VDO0>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>,
+ <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_IOMMU>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>,
+ <&vdosys0 CLK_VDO0_APB_BUS>;
+ clock-names = "cfgck", "cfgxo", "ss-gals",
+ "ss-cmn", "ss-emi", "ss-iommu",
+ "ss-larb", "ss-rsi", "ss-bus";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
+ reg = <MT8188_POWER_DOMAIN_VPPSYS1>;
+ clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VPP1>,
+ <&vppsys1 CLK_VPP1_GALS5>,
+ <&vppsys1 CLK_VPP1_GALS6>,
+ <&vppsys1 CLK_VPP1_LARB5>,
+ <&vppsys1 CLK_VPP1_LARB6>;
+ clock-names = "cfgck", "cfgxo",
+ "ss-vpp1-g5", "ss-vpp1-g6",
+ "ss-vpp1-l5", "ss-vpp1-l6";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VDEC0 {
+ reg = <MT8188_POWER_DOMAIN_VDEC0>;
+ clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
+ clock-names = "ss-vdec1-soc-l1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_VDEC1 {
+ reg = <MT8188_POWER_DOMAIN_VDEC1>;
+ clocks = <&vdecsys CLK_VDEC2_LARB1>;
+ clock-names = "ss-vdec2-l1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
+ reg = <MT8188_POWER_DOMAIN_CAM_VCORE>;
+ clocks = <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_CCU_AHB>,
+ <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>;
+ clock-names = "cam", "ccu", "bus", "cfgck";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
+ reg = <MT8188_POWER_DOMAIN_CAM_MAIN>;
+ clocks = <&camsys CLK_CAM_MAIN_LARB13>,
+ <&camsys CLK_CAM_MAIN_LARB14>,
+ <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>;
+ clock-names= "ss-cam-l13", "ss-cam-l14",
+ "ss-cam-mm0", "ss-cam-mm1",
+ "ss-camsys";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
+ reg = <MT8188_POWER_DOMAIN_CAM_SUBB>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
+ clock-names = "ss-camb-sub",
+ "ss-camb-raw",
+ "ss-camb-yuv";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
+ reg =<MT8188_POWER_DOMAIN_CAM_SUBA>;
+ clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_yuva CLK_CAM_YUVA_LARBX>;
+ clock-names = "ss-cama-sub",
+ "ss-cama-raw",
+ "ss-cama-yuv";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
+ reg = <MT8188_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>,
+ <&topckgen CLK_TOP_CFGREG_F26M_VDO1>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "cfgck", "cfgxo", "ss-larb2",
+ "ss-larb3", "ss-gals";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
+ reg = <MT8188_POWER_DOMAIN_HDMI_TX>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>,
+ <&topckgen CLK_TOP_HDCP_24M>;
+ clock-names = "bus", "hdcp";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_DP_TX {
+ reg = <MT8188_POWER_DOMAIN_DP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_EDP_TX {
+ reg = <MT8188_POWER_DOMAIN_EDP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_VENC {
+ reg = <MT8188_POWER_DOMAIN_VENC>;
+ clocks = <&vencsys CLK_VENC1_LARB>,
+ <&vencsys CLK_VENC1_VENC>,
+ <&vencsys CLK_VENC1_GALS>,
+ <&vencsys CLK_VENC1_GALS_SRAM>;
+ clock-names = "ss-ve1-larb", "ss-ve1-core",
+ "ss-ve1-gals", "ss-ve1-sram";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_WPE {
+ reg = <MT8188_POWER_DOMAIN_WPE>;
+ clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
+ <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>;
+ clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
+ reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
+ clock-names = "ss-pextp-fmem";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
+ reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>;
+ clocks = <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF1>;
+ clock-names = "seninf0", "seninf1";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
+ reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
+ reg = <MT8188_POWER_DOMAIN_ADSP_AO>;
+ clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_ADSP>;
+ clock-names = "bus", "main";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
+ reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
+ reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>;
+ clocks = <&topckgen CLK_TOP_ASM_H>;
+ clock-names = "asm";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_AUDIO {
+ reg = <MT8188_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>;
+ clock-names = "a1sys", "intbus", "adspck";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_ADSP {
+ reg = <MT8188_POWER_DOMAIN_ADSP>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8188_POWER_DOMAIN_ETHER {
+ reg = <MT8188_POWER_DOMAIN_ETHER>;
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ clock-names = "ethermac";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8188-wdt";
reg = <0 0x10007000 0 0x100>;
@@ -413,12 +1347,156 @@
clock-names = "spi", "wrap";
};
- scp: scp@10500000 {
- compatible = "mediatek,mt8188-scp";
- reg = <0 0x10500000 0 0x100000>,
- <0 0x10720000 0 0xe0000>;
- reg-names = "sram", "cfg";
- interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
+ reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>;
+ reg-names = "pmif", "spmimst";
+ assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_M_MST>;
+ clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
+ };
+
+ infra_iommu: iommu@10315000 {
+ compatible = "mediatek,mt8188-iommu-infra";
+ reg = <0 0x10315000 0 0x1000>;
+ interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ };
+
+ gce0: mailbox@10320000 {
+ compatible = "mediatek,mt8188-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ };
+
+ gce1: mailbox@10330000 {
+ compatible = "mediatek,mt8188-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ };
+
+ scp_cluster: scp@10720000 {
+ compatible = "mediatek,mt8188-scp-dual";
+ reg = <0 0x10720000 0 0xe0000>;
+ reg-names = "cfg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x10500000 0x100000>;
+ status = "disabled";
+
+ scp_c0: scp@0 {
+ compatible = "mediatek,scp-core";
+ reg = <0x0 0xd0000>;
+ reg-names = "sram";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ scp_c1: scp@d0000 {
+ compatible = "mediatek,scp-core";
+ reg = <0xd0000 0x2f000>;
+ reg-names = "sram";
+ interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+ };
+
+ afe: audio-controller@10b10000 {
+ compatible = "mediatek,mt8188-afe";
+ reg = <0 0x10b10000 0 0x10000>;
+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
+ assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
+ clocks = <&clk26m>,
+ <&apmixedsys CLK_APMIXED_APLL1>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV0>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV1>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV2>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV3>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV9>,
+ <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_AUDIO_H>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_DPTX>,
+ <&topckgen CLK_TOP_I2SO1>,
+ <&topckgen CLK_TOP_I2SO2>,
+ <&topckgen CLK_TOP_I2SI1>,
+ <&topckgen CLK_TOP_I2SI2>,
+ <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>,
+ <&topckgen CLK_TOP_APLL1_D4>,
+ <&topckgen CLK_TOP_APLL2_D4>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV4>,
+ <&topckgen CLK_TOP_A2SYS>,
+ <&topckgen CLK_TOP_AUD_IEC>;
+ clock-names = "clk26m",
+ "apll1",
+ "apll2",
+ "apll12_div0",
+ "apll12_div1",
+ "apll12_div2",
+ "apll12_div3",
+ "apll12_div9",
+ "top_a1sys_hp",
+ "top_aud_intbus",
+ "top_audio_h",
+ "top_audio_local_bus",
+ "top_dptx",
+ "top_i2so1",
+ "top_i2so2",
+ "top_i2si1",
+ "top_i2si2",
+ "adsp_audio_26m",
+ "apll1_d4",
+ "apll2_d4",
+ "apll12_div4",
+ "top_a2sys",
+ "top_aud_iec";
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
+ resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ mediatek,infracfg = <&infracfg_ao>;
+ mediatek,topckgen = <&topckgen>;
+ status = "disabled";
+ };
+
+ adsp: adsp@10b80000 {
+ compatible = "mediatek,mt8188-dsp";
+ reg = <0 0x10b80000 0 0x2000>,
+ <0 0x10d00000 0 0x80000>,
+ <0 0x10b8b000 0 0x100>,
+ <0 0x10b8f000 0 0x1000>;
+ reg-names = "cfg", "sram", "sec", "bus";
+ assigned-clocks = <&topckgen CLK_TOP_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
+ clock-names = "audiodsp", "adsp_bus";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ mbox-names = "rx", "tx";
+ power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
+ status = "disabled";
+ };
+
+ adsp_mailbox0: mailbox@10b86100 {
+ compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
+ reg = <0 0x10b86100 0 0x1000>;
+ interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <0>;
+ };
+
+ adsp_mailbox1: mailbox@10b87100 {
+ compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
+ reg = <0 0x10b87100 0 0x1000>;
+ interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <0>;
};
adsp_audio26m: clock-controller@10b91100 {
@@ -491,6 +1569,39 @@
status = "disabled";
};
+ lvts_ap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8188-lvts-ap";
+ reg = <0 0x1100b000 0 0xc00>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>;
+ nvmem-cells = <&lvts_efuse_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
+ disp_pwm0: pwm@1100e000 {
+ compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100e000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM0>,
+ <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
+ clock-names = "main", "mm";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ disp_pwm1: pwm@1100f000 {
+ compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
+ reg = <0 0x1100f000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_DISP_PWM1>,
+ <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
+ clock-names = "main", "mm";
+ interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
spi1: spi@11010000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
@@ -556,25 +1667,133 @@
status = "disabled";
};
- xhci1: usb@11200000 {
- compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
- reg = <0 0x11200000 0 0x1000>,
- <0 0x11203e00 0 0x0100>;
+ ssusb1: usb@11201000 {
+ compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port1 PHY_TYPE_USB2>,
- <&u3port1 PHY_TYPE_USB3>;
- assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
- <&topckgen CLK_TOP_SSUSB_XHCI>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x11200000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
- mediatek,syscon-wakeup = <&pericfg 0x468 2>;
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x468 2>;
status = "disabled";
+
+ xhci1: usb@0 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
+ };
+
+ eth: ethernet@11021000 {
+ compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
+ "snps,dwmac-5.10a";
+ reg = <0 0x11021000 0 0x4000>;
+ interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "macirq";
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
+ <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
+ <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ clock-names = "axi", "apb", "mac_main", "ptp_ref",
+ "rmii_internal", "mac_cg";
+ assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
+ <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+ <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
+ <&topckgen CLK_TOP_ETHPLL_D8>,
+ <&topckgen CLK_TOP_ETHPLL_D10>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>;
+ mediatek,pericfg = <&infracfg_ao>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ snps,txpbl = <16>;
+ snps,rxpbl = <16>;
+ snps,clk-csr = <0>;
+ status = "disabled";
+
+ eth_mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,wr_osr_lmt = <0x7>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <4>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <4>;
+ snps,tx-sched-wrr;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,priority = <0x0>;
+ snps,weight = <0x10>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,priority = <0x1>;
+ snps,weight = <0x11>;
+ };
+
+ queue2 {
+ snps,dcb-algorithm;
+ snps,priority = <0x2>;
+ snps,weight = <0x12>;
+ };
+
+ queue3 {
+ snps,dcb-algorithm;
+ snps,priority = <0x3>;
+ snps,weight = <0x13>;
+ };
+ };
};
mmc0: mmc@11230000 {
@@ -604,6 +1823,31 @@
status = "disabled";
};
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_2>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC2>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC30_2>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ lvts_mcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8188-lvts-mcu";
+ reg = <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
+ resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>;
+ nvmem-cells = <&lvts_efuse_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
i2c0: i2c@11280000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11280000 0 0x1000>,
@@ -652,42 +1896,116 @@
#clock-cells = <1>;
};
- xhci2: usb@112a0000 {
- compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
- reg = <0 0x112a0000 0 0x1000>,
- <0 0x112a3e00 0 0x0100>;
+ ssusb2: usb@112a1000 {
+ compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+ reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port2 PHY_TYPE_USB2>;
- assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
- <&topckgen CLK_TOP_USB_TOP_3P>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x112a0000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x470 2>;
status = "disabled";
+
+ xhci2: usb@0 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
};
- xhci0: usb@112b0000 {
- compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
- reg = <0 0x112b0000 0 0x1000>,
- <0 0x112b3e00 0 0x0100>;
+ ssusb0: usb@112b1000 {
+ compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+ reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port0 PHY_TYPE_USB2>;
- assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
- <&topckgen CLK_TOP_USB_TOP_2P>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x112b0000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
- mediatek,syscon-wakeup = <&pericfg 0x460 2>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x460 2>;
status = "disabled";
+
+ xhci0: usb@0 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
+ };
+
+ pcie: pcie@112f0000 {
+ compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
+ reg = <0 0x112f0000 0 0x2000>;
+ reg-names = "pcie-mac";
+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>;
+ bus-range = <0 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+ <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+ <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
+ clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
+ "peri_26m", "peri_mem";
+
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+
+ iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
+ iommu-map-mask = <0>;
+
+ phys = <&pcieport PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+
+ power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
+
+ resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>;
+ reset-names = "mac";
+
+ status = "disabled";
+
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
};
nor_flash: spi@1132c000 {
@@ -699,6 +2017,44 @@
clock-names = "spi", "sf", "axi";
assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pciephy: t-phy@11c20700 {
+ compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
+ ranges = <0 0 0x11c20700 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
+ status = "disabled";
+
+ pcieport: pcie-phy@0 {
+ reg = <0 0x700>;
+ clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ mipi_tx_config0: dsi-phy@11c80000 {
+ compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c80000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx_config1: dsi-phy@11c90000 {
+ compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c90000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
status = "disabled";
};
@@ -773,7 +2129,6 @@
<&clk26m>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
- status = "disabled";
};
};
@@ -827,18 +2182,387 @@
#clock-cells = <1>;
};
+ efuse: efuse@11f20000 {
+ compatible = "mediatek,mt8188-efuse", "mediatek,efuse";
+ reg = <0 0x11f20000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dp_calib_data: dp-calib@1a0 {
+ reg = <0x1a0 0xc>;
+ };
+
+ lvts_efuse_data1: lvts1-calib@1ac {
+ reg = <0x1ac 0x40>;
+ };
+
+ gpu_speedbin: gpu-speedbin@581 {
+ reg = <0x581 0x1>;
+ bits = <0 3>;
+ };
+
+ socinfo-data1@7a0 {
+ reg = <0x7a0 0x4>;
+ };
+
+ socinfo-data2@7e0 {
+ reg = <0x7e0 0x4>;
+ };
+ };
+
+ gpu: gpu@13000000 {
+ compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
+ reg = <0 0x13000000 0 0x4000>;
+
+ clocks = <&mfgcfg CLK_MFGCFG_BG3D>;
+ interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ nvmem-cells = <&gpu_speedbin>;
+ nvmem-cell-names = "speed-bin";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
+ <&spm MT8188_POWER_DOMAIN_MFG3>,
+ <&spm MT8188_POWER_DOMAIN_MFG4>;
+ power-domain-names = "core0", "core1", "core2";
+ #cooling-cells = <2>;
+ status = "disabled";
+ };
+
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8188-mfgcfg";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
- vppsys0: clock-controller@14000000 {
- compatible = "mediatek,mt8188-vppsys0";
+ vppsys0: syscon@14000000 {
+ compatible = "mediatek,mt8188-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
+ dma-controller@14001000 {
+ compatible = "mediatek,mt8188-mdp3-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
+ mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
+ <&gce0 14 CMDQ_THR_PRIO_1>,
+ <&gce0 16 CMDQ_THR_PRIO_1>,
+ <&gce0 21 CMDQ_THR_PRIO_1>,
+ <&gce0 22 CMDQ_THR_PRIO_1>;
+ iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
+ mediatek,scp = <&scp_c0>;
+ };
+
+ display@14002000 {
+ compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ };
+
+ display@14004000 {
+ compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14004000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ };
+
+ display@14005000 {
+ compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+ };
+
+ display@14006000 {
+ compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
+ };
+
+ display@14007000 {
+ compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ };
+
+ display@14008000 {
+ compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+ };
+
+ display@14009000 {
+ compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+ iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
+ };
+
+ display@1400a000 {
+ compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x1400a000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+ };
+
+ display@1400b000 {
+ compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ };
+
+ display@1400c000 {
+ compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x1400c000 0 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
+ };
+
+ mutex@1400f000 {
+ compatible = "mediatek,mt8188-vpp-mutex";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+ };
+
+ vpp_smi_common: smi@14012000 {
+ compatible = "mediatek,mt8188-smi-common-vpp";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ larb4: smi@14013000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x14013000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ mediatek,larb-id = <SMI_L4_ID>;
+ mediatek,smi = <&vpp_smi_common>;
+ };
+
+ vpp_iommu: iommu@14018000 {
+ compatible = "mediatek,mt8188-iommu-vpp";
+ reg = <0 0x14018000 0 0x5000>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
+ clock-names = "bclk";
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
+ #iommu-cells = <1>;
+ mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>;
+ };
+
+ dma-controller@14f09000 {
+ compatible = "mediatek,mt8188-mdp3-rdma";
+ reg = <0 0x14f09000 0 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
+ iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_RDMA>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
+ };
+
+ dma-controller@14f0a000 {
+ compatible = "mediatek,mt8188-mdp3-rdma";
+ reg = <0 0x14f0a000 0 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
+ iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_RDMA>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
+ };
+
+ display@14f0c000 {
+ compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0c000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ };
+
+ display@14f0d000 {
+ compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0d000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ };
+
+ display@14f0f000 {
+ compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0f000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ };
+
+ display@14f10000 {
+ compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f10000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+ };
+
+ display@14f12000 {
+ compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f12000 0 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ };
+
+ display@14f13000 {
+ compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f13000 0 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ };
+
+ display@14f15000 {
+ compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f15000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
+ };
+
+ display@14f16000 {
+ compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f16000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
+ };
+
+ display@14f18000 {
+ compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f18000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ };
+
+ display@14f19000 {
+ compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f19000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ };
+
+ display@14f1a000 {
+ compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1a000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ };
+
+ display@14f1b000 {
+ compatible = "mediatek,mt8188-mdp3-merge", "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1b000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ };
+
+ display@14f1d000 {
+ compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1d000 0 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ };
+
+ display@14f1e000 {
+ compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1e000 0 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ };
+
+ display@14f21000 {
+ compatible = "mediatek,mt8188-mdp3-padding",
+ "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x14f21000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ };
+
+ display@14f22000 {
+ compatible = "mediatek,mt8188-mdp3-padding",
+ "mediatek,mt8195-mdp3-padding";
+ reg = <0 0x14f22000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ };
+
+ display@14f24000 {
+ compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f24000 0 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ iommus = <&vdo_iommu M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
+ };
+
+ display@14f25000 {
+ compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f25000 0 0x1000>;
+ #dma-cells = <1>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ iommus = <&vpp_iommu M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8188-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -851,12 +2575,54 @@
#clock-cells = <1>;
};
- vppsys1: clock-controller@14f00000 {
- compatible = "mediatek,mt8188-vppsys1";
+ larb7: smi@14e04000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x14e04000 0 0x1000>;
+ clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
+ <&wpesys CLK_WPE_TOP_SMI_LARB7>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_WPE>;
+ mediatek,larb-id = <SMI_L7_ID>;
+ mediatek,smi = <&vpp_smi_common>;
+ };
+
+ vppsys1: syscon@14f00000 {
+ compatible = "mediatek,mt8188-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
};
+ mutex@14f01000 {
+ compatible = "mediatek,mt8188-vpp-mutex";
+ reg = <0 0x14f01000 0 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+ };
+
+ larb5: smi@14f02000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x14f02000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_GALS5>,
+ <&vppsys1 CLK_VPP1_LARB5>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,larb-id = <SMI_L5_ID>;
+ mediatek,smi = <&vdo_smi_common>;
+ };
+
+ larb6: smi@14f03000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x14f03000 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_GALS6>,
+ <&vppsys1 CLK_VPP1_LARB6>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>;
+ mediatek,larb-id = <SMI_L6_ID>;
+ mediatek,smi = <&vpp_smi_common>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8188-imgsys";
reg = <0 0x15000000 0 0x1000>;
@@ -867,36 +2633,42 @@
compatible = "mediatek,mt8188-imgsys1-dip-top";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8188-imgsys1-dip-nr";
reg = <0 0x15130000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys_wpe1: clock-controller@15220000 {
compatible = "mediatek,mt8188-imgsys-wpe1";
reg = <0 0x15220000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8188-ipesys";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys_wpe2: clock-controller@15520000 {
compatible = "mediatek,mt8188-imgsys-wpe2";
reg = <0 0x15520000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
imgsys_wpe3: clock-controller@15620000 {
compatible = "mediatek,mt8188-imgsys-wpe3";
reg = <0 0x15620000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys: clock-controller@16000000 {
@@ -909,24 +2681,28 @@
compatible = "mediatek,mt8188-camsys-rawa";
reg = <0 0x1604f000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys_yuva: clock-controller@1606f000 {
compatible = "mediatek,mt8188-camsys-yuva";
reg = <0 0x1606f000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys_rawb: clock-controller@1608f000 {
compatible = "mediatek,mt8188-camsys-rawb";
reg = <0 0x1608f000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
camsys_yuvb: clock-controller@160af000 {
compatible = "mediatek,mt8188-camsys-yuvb";
reg = <0 0x160af000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
ccusys: clock-controller@17200000 {
@@ -935,12 +2711,92 @@
#clock-cells = <1>;
};
+ video_decoder: video-decoder@18000000 {
+ compatible = "mediatek,mt8188-vcodec-dec";
+ reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>;
+ ranges = <0 0 0 0x18000000 0 0x26000>;
+ iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ mediatek,scp = <&scp_c0>;
+
+ video-codec@10000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0 0x10000 0 0x800>;
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys_soc CLK_VDEC1_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC1_SOC_LAT>,
+ <&topckgen CLK_TOP_UNIVPLL_D6>;
+ clock-names = "sel", "vdec", "lat", "top";
+ interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>,
+ <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
+ };
+
+ video-codec@25000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x25000 0 0x1000>;
+ assigned-clocks = <&topckgen CLK_TOP_VDEC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ clocks = <&topckgen CLK_TOP_VDEC>,
+ <&vdecsys CLK_VDEC2_VDEC>,
+ <&vdecsys CLK_VDEC2_LAT>,
+ <&topckgen CLK_TOP_UNIVPLL_D6>;
+ clock-names = "sel", "vdec", "lat", "top";
+ interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>,
+ <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
+ };
+ };
+
+ larb23: smi@1800d000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1800d000 0 0x1000>;
+ clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
+ mediatek,larb-id = <SMI_L23_ID>;
+ mediatek,smi = <&vpp_smi_common>;
+ };
+
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8188-vdecsys-soc";
reg = <0 0x1800f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb21: smi@1802e000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1802e000 0 0x1000>;
+ clocks = <&vdecsys CLK_VDEC2_LARB1>,
+ <&vdecsys CLK_VDEC2_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>;
+ mediatek,larb-id = <SMI_L21_ID>;
+ mediatek,smi = <&vdo_smi_common>;
+ };
+
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8188-vdecsys";
reg = <0 0x1802f000 0 0x1000>;
@@ -952,5 +2808,748 @@
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb19: smi@1a010000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ clocks = <&vencsys CLK_VENC1_VENC>,
+ <&vencsys CLK_VENC1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
+ mediatek,larb-id = <SMI_L19_ID>;
+ mediatek,smi = <&vdo_smi_common>;
+ };
+
+ video_encoder: video-encoder@1a020000 {
+ compatible = "mediatek,mt8188-vcodec-enc";
+ reg = <0 0x1a020000 0 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ assigned-clocks = <&topckgen CLK_TOP_VENC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
+ clocks = <&vencsys CLK_VENC1_VENC>;
+ clock-names = "venc_sel";
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>,
+ <&vdo_iommu M4U_PORT_L19_VENC_REC>,
+ <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>,
+ <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>,
+ <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>,
+ <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>,
+ <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>,
+ <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>,
+ <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>,
+ <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>,
+ <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
+ mediatek,scp = <&scp_c0>;
+ };
+
+ jpeg_encoder: jpeg-encoder@1a030000 {
+ compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc";
+ reg = <0 0x1a030000 0 0x10000>;
+ clocks = <&vencsys CLK_VENC1_JPGENC>;
+ clock-names = "jpgenc";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>,
+ <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>,
+ <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>,
+ <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VENC>;
+ };
+
+ jpeg_decoder: jpeg-decoder@1a040000 {
+ compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec";
+ reg = <0 0x1a040000 0 0x10000>;
+ clocks = <&vencsys CLK_VENC1_LARB>,
+ <&vencsys CLK_VENC1_JPGDEC>;
+ clock-names = "jpgdec-smi", "jpgdec";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>,
+ <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>,
+ <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>,
+ <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>,
+ <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>,
+ <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>;
+ };
+
+ ovl0: ovl@1c000000 {
+ compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ovl0_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ ovl0_out: endpoint {
+ remote-endpoint = <&rdma0_in>;
+ };
+ };
+ };
+ };
+
+ rdma0: rdma@1c002000 {
+ compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L1_DISP_RDMA0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rdma0_in: endpoint {
+ remote-endpoint = <&ovl0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ rdma0_out: endpoint {
+ remote-endpoint = <&color0_in>;
+ };
+ };
+ };
+ };
+
+ color0: color@1c003000 {
+ compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ color0_in: endpoint {
+ remote-endpoint = <&rdma0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ color0_out: endpoint {
+ remote-endpoint = <&ccorr0_in>;
+ };
+ };
+ };
+ };
+
+ ccorr0: ccorr@1c004000 {
+ compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ccorr0_in: endpoint {
+ remote-endpoint = <&color0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ccorr0_out: endpoint {
+ remote-endpoint = <&aal0_in>;
+ };
+ };
+ };
+ };
+
+ aal0: aal@1c005000 {
+ compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ aal0_in: endpoint {
+ remote-endpoint = <&ccorr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ aal0_out: endpoint {
+ remote-endpoint = <&gamma0_in>;
+ };
+ };
+ };
+ };
+
+ gamma0: gamma@1c006000 {
+ compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ gamma0_in: endpoint {
+ remote-endpoint = <&aal0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ gamma0_out: endpoint { };
+ };
+ };
+ };
+
+ dither0: dither@1c007000 {
+ compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dither0_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ dither0_out: endpoint { };
+ };
+ };
+ };
+
+ disp_dsi0: dsi@1c008000 {
+ compatible = "mediatek,mt8188-dsi";
+ reg = <0 0x1c008000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DSI0>,
+ <&vdosys0 CLK_VDO0_DSI0_DSI>,
+ <&mipi_tx_config0>;
+ clock-names = "engine", "digital", "hs";
+ interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&mipi_tx_config0>;
+ phy-names = "dphy";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ resets = <&vdosys0 MT8188_VDO0_RST_DSI0>;
+ status = "disabled";
+ };
+
+ dsc0: dsc@1c009000 {
+ compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ disp_dsi1: dsi@1c012000 {
+ compatible = "mediatek,mt8188-dsi";
+ reg = <0 0x1c012000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DSI1>,
+ <&vdosys0 CLK_VDO0_DSI1_DSI>,
+ <&mipi_tx_config1>;
+ clock-names = "engine", "digital", "hs";
+ interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&mipi_tx_config1>;
+ phy-names = "dphy";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ resets = <&vdosys0 MT8188_VDO0_RST_DSI1>;
+ status = "disabled";
+ };
+
+ merge0: merge0@1c014000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ dp_intf0: dp-intf@1c015000 {
+ compatible = "mediatek,mt8188-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "pixel", "engine", "pll";
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ status = "disabled";
+ };
+
+ mutex0: mutex@1c016000 {
+ compatible = "mediatek,mt8188-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
+ postmask0: postmask@1c01a000 {
+ compatible = "mediatek,mt8188-disp-postmask",
+ "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1c01a000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>;
+ interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ postmask0_in: endpoint { };
+ };
+
+ port@1 {
+ reg = <1>;
+ postmask0_out: endpoint { };
+ };
+ };
+ };
+
+ vdosys0: syscon@1c01d000 {
+ compatible = "mediatek,mt8188-vdosys0", "syscon";
+ reg = <0 0x1c01d000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>;
+ };
+
+ larb0: smi@1c022000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1c022000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,larb-id = <SMI_L0_ID>;
+ mediatek,smi = <&vdo_smi_common>;
+ };
+
+ larb1: smi@1c023000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1c023000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ mediatek,larb-id = <SMI_L1_ID>;
+ mediatek,smi = <&vpp_smi_common>;
+ };
+
+ vdo_smi_common: smi@1c024000 {
+ compatible = "mediatek,mt8188-smi-common-vdo";
+ reg = <0 0x1c024000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ vdo_iommu: iommu@1c028000 {
+ compatible = "mediatek,mt8188-iommu-vdo";
+ reg = <0 0x1c028000 0 0x5000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
+ clock-names = "bclk";
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
+ #iommu-cells = <1>;
+ mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>;
+ };
+
+ vdosys1: syscon@1c100000 {
+ compatible = "mediatek,mt8188-vdosys1", "syscon";
+ reg = <0 0x1c100000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>;
+ };
+
+ mutex1: mutex@1c101000 {
+ compatible = "mediatek,mt8188-disp-mutex";
+ reg = <0 0x1c101000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
+ interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
+ };
+
+ larb2: smi@1c102000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1c102000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,larb-id = <SMI_L2_ID>;
+ mediatek,smi = <&vdo_smi_common>;
+ };
+
+ larb3: smi@1c103000 {
+ compatible = "mediatek,mt8188-smi-larb";
+ reg = <0 0x1c103000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_SMI_LARB3>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,larb-id = <SMI_L3_ID>;
+ mediatek,smi = <&vpp_smi_common>;
+ };
+
+ vdo1_rdma0: rdma@1c104000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c104000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ vdo1_rdma1: rdma@1c105000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c105000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
+ interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
+ };
+
+ vdo1_rdma2: rdma@1c106000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c106000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
+ interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
+ };
+
+ vdo1_rdma3: rdma@1c107000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c107000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
+ interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
+ };
+
+ vdo1_rdma4: rdma@1c108000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c108000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
+ interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
+ };
+
+ vdo1_rdma5: rdma@1c109000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c109000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
+ interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
+ };
+
+ vdo1_rdma6: rdma@1c10a000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10a000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
+ interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
+ };
+
+ vdo1_rdma7: rdma@1c10b000 {
+ compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma";
+ reg = <0 0x1c10b000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
+ interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ #dma-cells = <1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
+ };
+
+ merge1: merge@1c10c000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ mediatek,merge-mute;
+ };
+
+ merge2: merge@1c10d000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10d000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
+ mediatek,merge-mute;
+ };
+
+ merge3: merge@1c10e000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10e000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
+ mediatek,merge-mute;
+ };
+
+ merge4: merge@1c10f000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c10f000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
+ mediatek,merge-mute;
+ };
+
+ merge5: merge@1c110000 {
+ compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge", "merge_async";
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en;
+ };
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8188-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DPINTF>,
+ <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "pixel", "engine", "pll";
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ status = "disabled";
+ };
+
+ ethdr0: ethdr@1c114000 {
+ compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11a000 0 0x1000>,
+ <0 0x1c11b000 0 0x1000>,
+ <0 0x1c11c000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top";
+
+ interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>,
+ <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>;
+
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
+ };
+
+ padding0: padding@1c11d000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c11d000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING0>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>;
+ };
+
+ padding1: padding@1c11e000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c11e000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING1>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>;
+ };
+
+ padding2: padding@1c11f000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c11f000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING2>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>;
+ };
+
+ padding3: padding@1c120000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c120000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING3>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>;
+ };
+
+ padding4: padding@1c121000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c121000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING4>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>;
+ };
+
+ padding5: padding@1c122000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c122000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING5>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>;
+ };
+
+ padding6: padding@1c123000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c123000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING6>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>;
+ };
+
+ padding7: padding@1c124000 {
+ compatible = "mediatek,mt8188-disp-padding";
+ reg = <0 0x1c124000 0 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_PADDING7>;
+ power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>;
+ };
+
+ edp_tx: edp-tx@1c500000 {
+ compatible = "mediatek,mt8188-edp-tx";
+ reg = <0 0x1c500000 0 0x8000>;
+ interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+ nvmem-cells = <&dp_calib_data>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>;
+ max-linkrate-mhz = <8100>;
+ status = "disabled";
+ };
+
+ dp_tx: dp-tx@1c600000 {
+ compatible = "mediatek,mt8188-dp-tx";
+ reg = <0 0x1c600000 0 0x8000>;
+ interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+ nvmem-cells = <&dp_calib_data>;
+ nvmem-cell-names = "dp_calibration_data";
+ power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>;
+ max-linkrate-mhz = <5400>;
+ status = "disabled";
+ };
};
};
generated by cgit (git 2.34.1) at 2025-07-23 13:26:19 +0000