diff options
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8195.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 292fcb1fa9aa..bdeaa332a3cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -39,6 +39,12 @@ clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -52,6 +58,12 @@ clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -65,6 +77,12 @@ clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -78,6 +96,12 @@ clock-frequency = <1701000000>; capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; }; @@ -91,6 +115,12 @@ clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -104,6 +134,12 @@ clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -117,6 +153,12 @@ clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -130,6 +172,12 @@ clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; }; @@ -215,18 +263,28 @@ l2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <512>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-size = <2097152>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; }; }; |