summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts284
1 files changed, 258 insertions, 26 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index 1558649f633c..be5e5f339e81 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -91,13 +91,12 @@
};
};
- backlight_lcd0: backlight-lcd0 {
+ backlight_lcm0: backlight-lcm0 {
compatible = "pwm-backlight";
- pwms = <&disp_pwm0 0 500000>;
- enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 1023>;
- num-interpolated-steps = <1023>;
default-brightness-level = <576>;
+ num-interpolated-steps = <1023>;
+ pwms = <&disp_pwm0 0 500000>;
};
backlight_lcd1: backlight-lcd1 {
@@ -107,6 +106,7 @@
brightness-levels = <0 1023>;
num-interpolated-steps = <1023>;
default-brightness-level = <576>;
+ status = "disabled";
};
can_clk: can-clk {
@@ -150,6 +150,24 @@
};
};
+ lcm0_iovcc: regulator-vio18-lcm0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vio18_lcm0";
+ enable-active-high;
+ gpio = <&pio 47 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dsi0_vreg_en_pins>;
+ vin-supply = <&mt6360_ldo2>;
+ };
+
+ lcm0_vddp: regulator-vsys-lcm0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_lcm0";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&mt6360_ldo1>;
+ };
+
wifi_fixed_3v3: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "wifi_3v3";
@@ -163,14 +181,65 @@
&disp_pwm0 {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_default_pins>;
+ pinctrl-0 = <&disp_pwm0_pins>;
status = "okay";
};
+&dither0_in {
+ remote-endpoint = <&gamma0_out>;
+};
+
+&dither0_out {
+ remote-endpoint = <&dsi0_in>;
+};
+
&dmic_codec {
wakeup-delay-ms = <200>;
};
+&dsi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "startek,kd070fhfid078", "himax,hx8279";
+ reg = <0>;
+ backlight = <&backlight_lcm0>;
+ enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>;
+ iovcc-supply = <&lcm0_iovcc>;
+ vdd-supply = <&lcm0_vddp>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_default_pins>;
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dither0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+};
+
&eth {
phy-mode ="rgmii-rxid";
phy-handle = <&eth_phy0>;
@@ -187,13 +256,22 @@
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
- eth_phy0: eth-phy0@1 {
+ eth_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
};
};
};
+&gamma0_out {
+ remote-endpoint = <&dither0_in>;
+};
+
+&gpu {
+ mali-supply = <&mt6315_7_vbuck1>;
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
@@ -224,6 +302,21 @@
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
+
+ typec-mux@48 {
+ compatible = "ite,it5205";
+ reg = <0x48>;
+ vcc-supply = <&mt6359_vibr_ldo_reg>;
+ mode-switch;
+ orientation-switch;
+ status = "okay";
+
+ port {
+ it5205_sbu_ep: endpoint {
+ remote-endpoint = <&mt6360_ssusb_sbu_ep>;
+ };
+ };
+ };
};
&i2c6 {
@@ -330,6 +423,63 @@
regulator-always-on;
};
};
+
+ tcpc {
+ compatible = "mediatek,mt6360-tcpc";
+ interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "PD_IRQB";
+
+ connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ op-sink-microwatt = <10000000>;
+ power-role = "dual";
+ try-power-role = "sink";
+
+ source-pdos = <PDO_FIXED(5000, 1000,
+ PDO_FIXED_DUAL_ROLE |
+ PDO_FIXED_DATA_SWAP)>;
+ sink-pdos = <PDO_FIXED(5000, 2000,
+ PDO_FIXED_DUAL_ROLE |
+ PDO_FIXED_DATA_SWAP)>;
+
+ pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>;
+
+ altmodes {
+ displayport {
+ svid = /bits/ 16 <0xff01>;
+ vdo = <0x00001c46>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ typec_con_hs: endpoint {
+ remote-endpoint = <&mtu3_hs0_role_sw>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&mtu3_ss0_role_sw>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ mt6360_ssusb_sbu_ep: endpoint {
+ remote-endpoint = <&it5205_sbu_ep>;
+ };
+ };
+ };
+ };
+ };
};
};
@@ -337,6 +487,14 @@
domain-supply = <&mt6315_7_vbuck1>;
};
+&mfg1 {
+ domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
+&mipi_tx0 {
+ status = "okay";
+};
+
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
@@ -407,12 +565,22 @@
regulator-always-on;
};
+/* for GPU SRAM */
+&mt6359_vsram_others_ldo_reg {
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+};
+
&mt6359codec {
mediatek,mic-type-0 = <1>; /* ACC */
mediatek,mic-type-1 = <3>; /* DCC */
mediatek,mic-type-2 = <1>; /* ACC */
};
+&ovl0_in {
+ remote-endpoint = <&vdosys0_ep_main>;
+};
+
&pcie0 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&pcie0_default_pins>;
@@ -475,7 +643,7 @@
<PINMUX_GPIO86__FUNC_GBE_RXC>,
<PINMUX_GPIO87__FUNC_GBE_RXDV>,
<PINMUX_GPIO88__FUNC_GBE_TXEN>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
pins-mdio {
@@ -502,7 +670,7 @@
<PINMUX_GPIO78__FUNC_GBE_TXD2>,
<PINMUX_GPIO79__FUNC_GBE_TXD1>,
<PINMUX_GPIO80__FUNC_GBE_TXD0>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
};
};
@@ -567,7 +735,7 @@
pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
<PINMUX_GPIO13__FUNC_SCL2>;
bias-pull-up = <MTK_PULL_SET_RSEL_111>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
};
};
@@ -582,7 +750,7 @@
mmc0_default_pins: mmc0-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -597,13 +765,13 @@
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_6mA>;
+ drive-strength = <6>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -611,7 +779,7 @@
mmc0_uhs_pins: mmc0-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -626,19 +794,19 @@
<PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
<PINMUX_GPIO121__FUNC_MSDC0_CMD>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
pins-ds {
pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
pins-rst {
pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -646,7 +814,7 @@
mmc1_default_pins: mmc1-default-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -657,7 +825,7 @@
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -665,7 +833,7 @@
mmc1_uhs_pins: mmc1-uhs-pins {
pins-clk {
pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
@@ -676,7 +844,7 @@
<PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
<PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
input-enable;
- drive-strength = <MTK_DRIVE_8mA>;
+ drive-strength = <8>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
@@ -690,6 +858,25 @@
};
};
+ dsi0_vreg_en_pins: dsi0-vreg-en-pins {
+ pins-pwr-en {
+ pinmux = <PINMUX_GPIO47__FUNC_GPIO47>;
+ output-low;
+ };
+ };
+
+ panel_default_pins: panel-default-pins {
+ pins-rst {
+ pinmux = <PINMUX_GPIO108__FUNC_GPIO108>;
+ output-high;
+ };
+
+ pins-en {
+ pinmux = <PINMUX_GPIO48__FUNC_GPIO48>;
+ output-low;
+ };
+ };
+
pcie0_default_pins: pcie0-default-pins {
pins {
pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
@@ -716,8 +903,8 @@
};
};
- pwm0_default_pins: pwm0-default-pins {
- pins-cmd-dat {
+ disp_pwm0_pins: disp-pwm0-pins {
+ pins-disp-pwm {
pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>;
};
};
@@ -755,6 +942,13 @@
};
};
+ u3_p0_vbus: u3-p0-vbus-default-pins {
+ pins-vbus {
+ pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
+ input-enable;
+ };
+ };
+
uart0_pins: uart0-pins {
pins {
pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
@@ -778,6 +972,7 @@
&scp {
memory-region = <&scp_mem>;
+ firmware-name = "mediatek/mt8195/scp.img";
status = "okay";
};
@@ -820,7 +1015,6 @@
regulators {
mt6315_6_vbuck1: vbuck1 {
- regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
@@ -837,10 +1031,9 @@
regulators {
mt6315_7_vbuck1: vbuck1 {
- regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
- regulator-min-microvolt = <300000>;
- regulator-max-microvolt = <1193750>;
+ regulator-min-microvolt = <546000>;
+ regulator-max-microvolt = <787000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
};
@@ -854,6 +1047,10 @@
&u3phy1 {
status = "okay";
+
+ u3port1: usb-phy@700 {
+ mediatek,force-mode;
+ };
};
&u3phy2 {
@@ -881,8 +1078,31 @@
};
&ssusb0 {
+ dr_mode = "otg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&u3_p0_vbus>;
+ usb-role-switch;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mtu3_hs0_role_sw: endpoint {
+ remote-endpoint = <&typec_con_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mtu3_ss0_role_sw: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+ };
};
&ssusb2 {
@@ -895,6 +1115,18 @@
status = "okay";
};
+&vdosys0 {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdosys0_ep_main: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_in>;
+ };
+ };
+};
+
&xhci0 {
status = "okay";
};
generated by cgit (git 2.34.1) at 2025-08-04 00:32:23 +0000