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Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq8074.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/ipq8074.dtsi326
1 files changed, 200 insertions, 126 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 00ed71936b47..256e12cf6d54 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -32,39 +32,39 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -101,7 +101,7 @@
reg = <0x0 0x4ab00000 0x0 0x100000>;
no-map;
- hwlocks = <&tcsr_mutex 0>;
+ hwlocks = <&tcsr_mutex 3>;
};
memory@4ac00000 {
@@ -125,32 +125,26 @@
ssphy_1: phy@58000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00058000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00058000 0x1000>;
clocks = <&gcc GCC_USB1_AUX_CLK>,
- <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB1_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3phy_1_cc_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB1_PHY_BCR>,
- <&gcc GCC_USB3PHY_1_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
+ <&gcc GCC_USB3PHY_1_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb1_ssphy: phy@58200 {
- reg = <0x00058200 0x130>, /* Tx */
- <0x00058400 0x200>, /* Rx */
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_1_cc_pipe_clk";
- };
+ status = "disabled";
};
qusb_phy_1: phy@59000 {
@@ -168,32 +162,26 @@
ssphy_0: phy@78000 {
compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00078000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00078000 0x1000>;
clocks = <&gcc GCC_USB0_AUX_CLK>,
- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&xo>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3phy_0_cc_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB0_PHY_BCR>,
- <&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- usb0_ssphy: phy@78200 {
- reg = <0x00078200 0x130>, /* Tx */
- <0x00078400 0x200>, /* Rx */
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc */
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_0_cc_pipe_clk";
- };
+ status = "disabled";
};
qusb_phy_0: phy@79000 {
@@ -211,59 +199,48 @@
pcie_qmp0: phy@84000 {
compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
- reg = <0x00084000 0x1bc>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00084000 0x1000>;
clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe";
+
+ clock-output-names = "pcie20_phy0_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
resets = <&gcc GCC_PCIE0_PHY_BCR>,
- <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
-
- pcie_phy0: phy@84200 {
- reg = <0x84200 0x16c>,
- <0x84400 0x200>,
- <0x84800 0x1f0>,
- <0x84c00 0xf4>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie20_phy0_pipe_clk";
- };
};
pcie_qmp1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x0008e000 0x1000>;
clocks = <&gcc GCC_PCIE1_AUX_CLK>,
- <&gcc GCC_PCIE1_AHB_CLK>;
- clock-names = "aux", "cfg_ahb";
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "pipe";
+
+ clock-output-names = "pcie20_phy1_pipe_clk";
+ #clock-cells = <0>;
+
+ #phy-cells = <0>;
+
resets = <&gcc GCC_PCIE1_PHY_BCR>,
- <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
status = "disabled";
-
- pcie_phy1: phy@8e200 {
- reg = <0x8e200 0x130>,
- <0x8e400 0x200>,
- <0x8e800 0x1f8>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie20_phy1_pipe_clk";
- };
};
mdio: mdio@90000 {
@@ -275,6 +252,8 @@
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
+ clock-frequency = <6250000>;
+
status = "disabled";
};
@@ -344,6 +323,13 @@
bias-disable;
};
+ serial_5_pins: serial5-state {
+ pins = "gpio9", "gpio16";
+ function = "blsp5_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
i2c_0_pins: i2c-0-state {
pins = "gpio42", "gpio43";
function = "blsp1_i2c";
@@ -370,18 +356,24 @@
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14",
- "gpio15", "gpio16", "gpio17";
+ "gpio15", "gpio17";
function = "qpic";
drive-strength = <8>;
bias-disable;
};
};
- gcc: gcc@1800000 {
+ gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq8074";
reg = <0x01800000 0x80000>;
- clocks = <&xo>, <&sleep_clk>;
- clock-names = "xo", "sleep_clk";
+ clocks = <&xo>,
+ <&sleep_clk>,
+ <&pcie_qmp0>,
+ <&pcie_qmp1>;
+ clock-names = "xo",
+ "sleep_clk",
+ "pcie0_pipe",
+ "pcie1_pipe";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
@@ -417,7 +409,7 @@
};
sdhc_1: mmc@7824900 {
- compatible = "qcom,sdhci-msm-v4";
+ compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg-names = "hc", "core";
@@ -486,6 +478,18 @@
status = "disabled";
};
+ blsp1_uart6: serial@78b4000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b4000 0x200>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-0 = <&serial_5_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
blsp1_spi1: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
#address-cells = <1>;
@@ -534,6 +538,20 @@
status = "disabled";
};
+ blsp1_spi4: spi@78b8000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 18>, <&blsp_dma 19>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
blsp1_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
@@ -630,6 +648,13 @@
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
@@ -639,8 +664,9 @@
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
@@ -672,6 +698,13 @@
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB1_GDSC>;
resets = <&gcc GCC_USB1_BCR>;
@@ -681,8 +714,9 @@
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&qusb_phy_1>, <&usb1_ssphy>;
+ phys = <&qusb_phy_1>, <&ssphy_1>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,parkmode-disable-ss-quirk;
snps,is-utmi-l1-suspend;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
@@ -719,8 +753,8 @@
compatible = "qcom,ipq8074-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
- clocks = <&a53pll>, <&xo>;
- clock-names = "pll", "xo";
+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+ clock-names = "pll", "xo", "gpll0";
#clock-cells = <1>;
#mbox-cells = <1>;
@@ -792,7 +826,7 @@
};
};
- pcie1: pci@10000000 {
+ pcie1: pcie@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
@@ -807,23 +841,39 @@
#address-cells = <3>;
#size-cells = <2>;
- phys = <&pcie_phy1>;
+ phys = <&pcie_qmp1>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 142
+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 143
+ <0 0 0 2 &intc 0 GIC_SPI 143
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 144
+ <0 0 0 3 &intc 0 GIC_SPI 144
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 145
+ <0 0 0 4 &intc 0 GIC_SPI 145
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
@@ -851,9 +901,19 @@
"ahb",
"axi_m_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
- pcie0: pci@20000000 {
+ pcie0: pcie@20000000 {
compatible = "qcom,pcie-ipq8074-gen3";
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
@@ -869,23 +929,39 @@
#address-cells = <3>;
#size-cells = <2>;
- phys = <&pcie_phy0>;
+ phys = <&pcie_qmp0>;
phy-names = "pciephy";
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 75
+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75
IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 78
+ <0 0 0 2 &intc 0 GIC_SPI 78
IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 79
+ <0 0 0 3 &intc 0 GIC_SPI 79
IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 83
+ <0 0 0 4 &intc 0 GIC_SPI 83
IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
@@ -916,6 +992,16 @@
"axi_m_sticky",
"axi_s_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
@@ -930,7 +1016,6 @@
thermal-zones {
nss-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@@ -945,7 +1030,6 @@
nss0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -960,7 +1044,6 @@
nss1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 6>;
@@ -975,7 +1058,6 @@
wcss-phya0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 7>;
@@ -990,7 +1072,6 @@
wcss-phya1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 8>;
@@ -1005,7 +1086,6 @@
cpu0_thermal: cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 9>;
@@ -1020,7 +1100,6 @@
cpu1_thermal: cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 10>;
@@ -1035,7 +1114,6 @@
cpu2_thermal: cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 11>;
@@ -1050,7 +1128,6 @@
cpu3_thermal: cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 12>;
@@ -1065,7 +1142,6 @@
cluster_thermal: cluster-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 13>;
@@ -1080,7 +1156,6 @@
wcss-phyb0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 14>;
@@ -1095,7 +1170,6 @@
wcss-phyb1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 15>;
generated by cgit (git 2.34.1) at 2026-01-01 17:16:10 +0000