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Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8916.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi1008
1 files changed, 828 insertions, 180 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 2ca8e977fc2a..d3a25a837488 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -4,12 +4,14 @@
*/
#include <dt-bindings/arm/coresight-cti-dt.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
+#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -18,11 +20,6 @@
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- mmc0 = &sdhc_1; /* SDC1 eMMC slot */
- mmc1 = &sdhc_2; /* SDC2 SD card slot */
- };
-
chosen { };
memory@80000000 {
@@ -79,23 +76,43 @@
};
mpss_mem: mpss@86800000 {
- reg = <0x0 0x86800000 0x0 0x2b00000>;
+ /*
+ * The memory region for the mpss firmware is generally
+ * relocatable and could be allocated dynamically.
+ * However, many firmware versions tend to fail when
+ * loaded to some special addresses, so it is hard to
+ * define reliable alloc-ranges.
+ *
+ * alignment = <0x0 0x400000>;
+ * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
+ */
+ reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
no-map;
+ status = "disabled";
};
- wcnss_mem: wcnss@89300000 {
- reg = <0x0 0x89300000 0x0 0x600000>;
+ wcnss_mem: wcnss {
+ size = <0x0 0x600000>;
+ alignment = <0x0 0x100000>;
+ alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
no-map;
+ status = "disabled";
};
- venus_mem: venus@89900000 {
- reg = <0x0 0x89900000 0x0 0x600000>;
+ venus_mem: venus {
+ size = <0x0 0x500000>;
+ alignment = <0x0 0x100000>;
+ alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
no-map;
+ status = "disabled";
};
- mba_mem: mba@8ea00000 {
+ mba_mem: mba {
+ size = <0x0 0x100000>;
+ alignment = <0x0 0x100000>;
+ alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
no-map;
- reg = <0 0x8ea00000 0 0x100000>;
+ status = "disabled";
};
};
@@ -109,7 +126,7 @@
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <32768>;
+ clock-frequency = <32764>;
};
};
@@ -117,75 +134,76 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- power-domains = <&CPU_PD0>;
+ power-domains = <&cpu_pd0>;
power-domain-names = "psci";
qcom,acc = <&cpu0_acc>;
qcom,saw = <&cpu0_saw>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- power-domains = <&CPU_PD1>;
+ power-domains = <&cpu_pd1>;
power-domain-names = "psci";
qcom,acc = <&cpu1_acc>;
qcom,saw = <&cpu1_saw>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- power-domains = <&CPU_PD2>;
+ power-domains = <&cpu_pd2>;
power-domain-names = "psci";
qcom,acc = <&cpu2_acc>;
qcom,saw = <&cpu2_saw>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
enable-method = "psci";
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
- power-domains = <&CPU_PD3>;
+ power-domains = <&cpu_pd3>;
power-domain-names = "psci";
qcom,acc = <&cpu3_acc>;
qcom,saw = <&cpu3_saw>;
};
- L2_0: l2-cache {
+ l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
+ cache-unified;
};
idle-states {
entry-method = "psci";
- CPU_SLEEP_0: cpu-sleep-0 {
+ cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x40000002>;
@@ -198,7 +216,7 @@
domain-idle-states {
- CLUSTER_RET: cluster-retention {
+ cluster_ret: cluster-retention {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000012>;
entry-latency-us = <500>;
@@ -206,7 +224,7 @@
min-residency-us = <2000>;
};
- CLUSTER_PWRDN: cluster-gdhs {
+ cluster_pwrdn: cluster-gdhs {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000032>;
entry-latency-us = <2000>;
@@ -256,46 +274,46 @@
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: power-domain-cpu0 {
+ cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cpu_sleep_0>;
};
- CPU_PD1: power-domain-cpu1 {
+ cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cpu_sleep_0>;
};
- CPU_PD2: power-domain-cpu2 {
+ cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cpu_sleep_0>;
};
- CPU_PD3: power-domain-cpu3 {
+ cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
- domain-idle-states = <&CPU_SLEEP_0>;
+ power-domains = <&cluster_pd>;
+ domain-idle-states = <&cpu_sleep_0>;
};
- CLUSTER_PD: power-domain-cluster {
+ cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
- domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
+ domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>;
};
};
- smd {
- compatible = "qcom,smd";
+ rpm: remoteproc {
+ compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
- rpm {
+ smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8916";
+ compatible = "qcom,rpm-msm8916", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
@@ -343,7 +361,7 @@
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -368,7 +386,7 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
@@ -393,8 +411,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 13>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -442,11 +459,70 @@
reg = <0x0005c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- tsens_caldata: caldata@d0 {
- reg = <0xd0 0x8>;
+
+ tsens_base1: base1@d0 {
+ reg = <0xd0 0x1>;
+ bits = <0 7>;
+ };
+
+ tsens_s0_p1: s0-p1@d0 {
+ reg = <0xd0 0x2>;
+ bits = <7 5>;
+ };
+
+ tsens_s0_p2: s0-p2@d1 {
+ reg = <0xd1 0x2>;
+ bits = <4 5>;
+ };
+
+ tsens_s1_p1: s1-p1@d2 {
+ reg = <0xd2 0x1>;
+ bits = <1 5>;
};
- tsens_calsel: calsel@ec {
- reg = <0xec 0x4>;
+ tsens_s1_p2: s1-p2@d2 {
+ reg = <0xd2 0x2>;
+ bits = <6 5>;
+ };
+ tsens_s2_p1: s2-p1@d3 {
+ reg = <0xd3 0x1>;
+ bits = <3 5>;
+ };
+
+ tsens_s2_p2: s2-p2@d4 {
+ reg = <0xd4 0x1>;
+ bits = <0 5>;
+ };
+
+ // no tsens with hw_id 3
+
+ tsens_s4_p1: s4-p1@d4 {
+ reg = <0xd4 0x2>;
+ bits = <5 5>;
+ };
+
+ tsens_s4_p2: s4-p2@d5 {
+ reg = <0xd5 0x1>;
+ bits = <2 5>;
+ };
+
+ tsens_s5_p1: s5-p1@d5 {
+ reg = <0xd5 0x2>;
+ bits = <7 5>;
+ };
+
+ tsens_s5_p2: s5-p2@d6 {
+ reg = <0xd6 0x2>;
+ bits = <4 5>;
+ };
+
+ tsens_base2: base2@d7 {
+ reg = <0xd7 0x1>;
+ bits = <1 7>;
+ };
+
+ tsens_mode: mode@ef {
+ reg = <0xef 0x1>;
+ bits = <5 3>;
};
};
@@ -464,17 +540,28 @@
compatible = "qcom,msm8916-bimc";
reg = <0x00400000 0x62000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
tsens: thermal-sensor@4a9000 {
compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
- nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
- nvmem-cell-names = "calib", "calib_sel";
+
+ // no hw_id 3
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s4_p1>, <&tsens_s4_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s4_p1", "s4_p2",
+ "s5_p1", "s5_p2";
#qcom,sensors = <5>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
@@ -485,18 +572,12 @@
compatible = "qcom,msm8916-pcnoc";
reg = <0x00500000 0x11000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
snoc: interconnect@580000 {
compatible = "qcom,msm8916-snoc";
reg = <0x00580000 0x14000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
stm: stm@802000 {
@@ -743,7 +824,7 @@
reg = <0x00850000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
status = "disabled";
};
@@ -752,7 +833,7 @@
reg = <0x00852000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
status = "disabled";
};
@@ -761,7 +842,7 @@
reg = <0x00854000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
status = "disabled";
};
@@ -770,7 +851,7 @@
reg = <0x00856000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
status = "disabled";
};
@@ -784,7 +865,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
arm,cs-dev-assoc = <&etm0>;
status = "disabled";
@@ -799,7 +880,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
arm,cs-dev-assoc = <&etm1>;
status = "disabled";
@@ -814,7 +895,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
arm,cs-dev-assoc = <&etm2>;
status = "disabled";
@@ -829,7 +910,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
arm,cs-dev-assoc = <&etm3>;
status = "disabled";
@@ -843,7 +924,7 @@
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
status = "disabled";
@@ -864,7 +945,7 @@
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
status = "disabled";
@@ -885,7 +966,7 @@
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
status = "disabled";
@@ -906,7 +987,7 @@
clock-names = "apb_pclk", "atclk";
arm,coresight-loses-context-with-cpu;
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
status = "disabled";
@@ -919,15 +1000,515 @@
};
};
- msmgpio: pinctrl@1000000 {
+ tlmm: pinctrl@1000000 {
compatible = "qcom,msm8916-pinctrl";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&msmgpio 0 0 122>;
+ gpio-ranges = <&tlmm 0 0 122>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ blsp_i2c1_default: blsp-i2c1-default-state {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c1_sleep: blsp-i2c1-sleep-state {
+ pins = "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c2_default: blsp-i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c2_sleep: blsp-i2c2-sleep-state {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c3_default: blsp-i2c3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c3_sleep: blsp-i2c3-sleep-state {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c4_default: blsp-i2c4-default-state {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c4_sleep: blsp-i2c4-sleep-state {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c5_default: blsp-i2c5-default-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c5_sleep: blsp-i2c5-sleep-state {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c6_default: blsp-i2c6-default-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_i2c6_sleep: blsp-i2c6-sleep-state {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp_spi1_default: blsp-spi1-default-state {
+ spi-pins {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi1_sleep: blsp-spi1-sleep-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi2_default: blsp-spi2-default-state {
+ spi-pins {
+ pins = "gpio4", "gpio5", "gpio7";
+ function = "blsp_spi2";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi2_sleep: blsp-spi2-sleep-state {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi3_default: blsp-spi3-default-state {
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi3_sleep: blsp-spi3-sleep-state {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi4_default: blsp-spi4-default-state {
+ spi-pins {
+ pins = "gpio12", "gpio13", "gpio15";
+ function = "blsp_spi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio14";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi4_sleep: blsp-spi4-sleep-state {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi5_default: blsp-spi5-default-state {
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi5_sleep: blsp-spi5-sleep-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_spi6_default: blsp-spi6-default-state {
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ cs-pins {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp_spi6_sleep: blsp-spi6-sleep-state {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_uart1_console_default: blsp-uart1-console-default-state {
+ tx-pins {
+ pins = "gpio0";
+ function = "blsp_uart1";
+ drive-strength = <16>;
+ bias-disable;
+ bootph-all;
+ };
+
+ rx-pins {
+ pins = "gpio1";
+ function = "blsp_uart1";
+ drive-strength = <16>;
+ bias-pull-up;
+ bootph-all;
+ };
+ };
+
+ blsp_uart1_console_sleep: blsp-uart1-console-sleep-state {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp_uart2_console_default: blsp-uart2-console-default-state {
+ tx-pins {
+ pins = "gpio4";
+ function = "blsp_uart2";
+ drive-strength = <16>;
+ bias-disable;
+ bootph-all;
+ };
+
+ rx-pins {
+ pins = "gpio5";
+ function = "blsp_uart2";
+ drive-strength = <16>;
+ bias-pull-up;
+ bootph-all;
+ };
+ };
+
+ blsp_uart2_console_sleep: blsp-uart2-console-sleep-state {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ camera_front_default: camera-front-default-state {
+ pwdn-pins {
+ pins = "gpio33";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ rst-pins {
+ pins = "gpio28";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ mclk1-pins {
+ pins = "gpio27";
+ function = "cam_mclk1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera-rear-default-state {
+ pwdn-pins {
+ pins = "gpio34";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ rst-pins {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ mclk0-pins {
+ pins = "gpio26";
+ function = "cam_mclk0";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci0_default: cci0-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cdc_dmic_default: cdc-dmic-default-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
+ drive-strength = <8>;
+ };
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_dmic_sleep: cdc-dmic-sleep-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cdc_pdm_default: cdc-pdm-default-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cdc_pdm_sleep: cdc-pdm-sleep-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ pri_mi2s_default: mi2s-pri-default-state {
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pri_mi2s_sleep: mi2s-pri-sleep-state {
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
+ pins = "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
+ pins = "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pri_mi2s_ws_default: mi2s-pri-ws-default-state {
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sec_mi2s_default: mi2s-sec-default-state {
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ sec_mi2s_sleep: mi2s-sec-sleep-state {
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc1_default: sdc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc1_sleep: sdc1-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ wcss_wlan_default: wcss-wlan-default-state {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "wcss_wlan";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
};
gcc: clock-controller@1800000 {
@@ -938,8 +1519,8 @@
reg = <0x01800000 0x80000>;
clocks = <&xo_board>,
<&sleep_clk>,
- <&dsi_phy0 1>,
- <&dsi_phy0 0>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<0>,
<0>,
<0>;
@@ -963,7 +1544,7 @@
reg = <0x01937000 0x30000>;
};
- mdss: mdss@1a00000 {
+ mdss: display-subsystem@1a00000 {
status = "disabled";
compatible = "qcom,mdss";
reg = <0x01a00000 0x1000>,
@@ -981,6 +1562,8 @@
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&gcc GCC_MDSS_BCR>;
+
interrupt-controller;
#interrupt-cells = <1>;
@@ -988,8 +1571,8 @@
#size-cells = <1>;
ranges;
- mdp: mdp@1a01000 {
- compatible = "qcom,mdp5";
+ mdss_mdp: display-controller@1a01000 {
+ compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
@@ -1013,15 +1596,16 @@
port@0 {
reg = <0>;
- mdp5_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ mdss_mdp_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
};
};
- dsi0: dsi@1a98000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ mdss_dsi0: dsi@1a98000 {
+ compatible = "qcom,msm8916-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0x01a98000 0x25c>;
reg-names = "dsi_ctrl";
@@ -1030,8 +1614,8 @@
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi_phy0 0>,
- <&dsi_phy0 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
@@ -1045,7 +1629,7 @@
"byte",
"pixel",
"core";
- phys = <&dsi_phy0>;
+ phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1056,20 +1640,20 @@
port@0 {
reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&mdp5_intf1_out>;
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&mdss_mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
- dsi_phy0: phy@1a98300 {
+ mdss_dsi0_phy: phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x01a98300 0xd4>,
<0x01a98500 0x280>,
@@ -1087,7 +1671,7 @@
};
};
- camss: camss@1b00000 {
+ camss: camss@1b0ac00 {
compatible = "qcom,msm8916-camss";
reg = <0x01b0ac00 0x200>,
<0x01b00030 0x4>,
@@ -1163,11 +1747,19 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
};
};
cci: cci@1b0c000 {
- compatible = "qcom,msm8916-cci";
+ compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01b0c000 0x1000>;
@@ -1193,7 +1785,7 @@
};
};
- gpu@1c00000 {
+ gpu: gpu@1c00000 {
compatible = "qcom,adreno-306.0", "qcom,adreno";
reg = <0x01c00000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
@@ -1216,6 +1808,9 @@
power-domains = <&gcc OXILI_GDSC>;
operating-points-v2 = <&gpu_opp_table>;
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ #cooling-cells = <2>;
+
+ status = "disabled";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1240,15 +1835,7 @@
clock-names = "core", "iface", "bus";
iommus = <&apps_iommu 5>;
memory-region = <&venus_mem>;
- status = "okay";
-
- video-decoder {
- compatible = "venus-decoder";
- };
-
- video-encoder {
- compatible = "venus-encoder";
- };
+ status = "disabled";
};
apps_iommu: iommu@1ef0000 {
@@ -1256,7 +1843,7 @@
#size-cells = <1>;
#iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
- ranges = <0 0x01e20000 0x40000>;
+ ranges = <0 0x01e20000 0x20000>;
reg = <0x01ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>;
@@ -1406,11 +1993,59 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
- qcom,ipc = <&apcs 8 12>;
+ mboxes = <&apcs 12>;
qcom,remote-pid = <1>;
label = "hexagon";
+ apr: apr {
+ compatible = "qcom,apr-v2";
+ qcom,smd-channels = "apr_audio_svc";
+ qcom,domain = <APR_DOMAIN_ADSP>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ q6core: service@3 {
+ compatible = "qcom,q6core";
+ reg = <APR_SVC_ADSP_CORE>;
+ };
+
+ q6afe: service@4 {
+ compatible = "qcom,q6afe";
+ reg = <APR_SVC_AFE>;
+
+ q6afedai: dais {
+ compatible = "qcom,q6afe-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6asm: service@7 {
+ compatible = "qcom,q6asm";
+ reg = <APR_SVC_ASM>;
+
+ q6asmdai: dais {
+ compatible = "qcom,q6asm-dais";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ };
+ };
+
+ q6adm: service@8 {
+ compatible = "qcom,q6adm";
+ reg = <APR_SVC_ADM>;
+
+ q6routing: routing {
+ compatible = "qcom,q6adm-routing";
+ #sound-dai-cells = <0>;
+ };
+ };
+ };
+
fastrpc {
compatible = "qcom,fastrpc";
qcom,smd-channels = "fastrpcsmd-apps-dsp";
@@ -1445,20 +2080,20 @@
* Primary/Secondary MI2S both use the PRI_I2S_CLK.
*/
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
- <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
- <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
- <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
+ <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
+ <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
clock-names = "ahbix-clk",
- "pcnoc-mport-clk",
- "pcnoc-sway-clk",
"mi2s-bit-clk0",
"mi2s-bit-clk1",
"mi2s-bit-clk2",
- "mi2s-bit-clk3";
+ "mi2s-bit-clk3",
+ "pcnoc-mport-clk",
+ "pcnoc-sway-clk";
#sound-dai-cells = <1>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
@@ -1477,9 +2112,10 @@
<&gcc GCC_CODEC_DIGCODEC_CLK>;
clock-names = "ahbix-clk", "mclk";
#sound-dai-cells = <1>;
+ status = "disabled";
};
- sdhc_1: mmc@7824000 {
+ sdhc_1: mmc@7824900 {
compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
reg-names = "hc", "core";
@@ -1491,13 +2127,17 @@
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
+ pinctrl-0 = <&sdc1_default>;
+ pinctrl-1 = <&sdc1_sleep>;
+ pinctrl-names = "default", "sleep";
mmc-ddr-1_8v;
bus-width = <8>;
non-removable;
status = "disabled";
};
- sdhc_2: mmc@7864000 {
+ sdhc_2: mmc@7864900 {
compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc", "core";
@@ -1509,6 +2149,10 @@
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
+ pinctrl-0 = <&sdc2_default>;
+ pinctrl-1 = <&sdc2_sleep>;
+ pinctrl-names = "default", "sleep";
bus-width = <4>;
status = "disabled";
};
@@ -1521,10 +2165,10 @@
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
- status = "disabled";
+ qcom,controlled-remotely;
};
- blsp1_uart1: serial@78af000 {
+ blsp_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
@@ -1532,13 +2176,10 @@
clock-names = "core", "iface";
dmas = <&blsp_dma 0>, <&blsp_dma 1>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart1_default>;
- pinctrl-1 = <&blsp1_uart1_sleep>;
status = "disabled";
};
- blsp1_uart2: serial@78b0000 {
+ blsp_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
@@ -1546,9 +2187,6 @@
clock-names = "core", "iface";
dmas = <&blsp_dma 2>, <&blsp_dma 3>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart2_default>;
- pinctrl-1 = <&blsp1_uart2_sleep>;
status = "disabled";
};
@@ -1559,9 +2197,11 @@
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c1_default>;
- pinctrl-1 = <&i2c1_sleep>;
+ pinctrl-0 = <&blsp_i2c1_default>;
+ pinctrl-1 = <&blsp_i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1577,8 +2217,8 @@
dmas = <&blsp_dma 4>, <&blsp_dma 5>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi1_default>;
- pinctrl-1 = <&spi1_sleep>;
+ pinctrl-0 = <&blsp_spi1_default>;
+ pinctrl-1 = <&blsp_spi1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1591,9 +2231,11 @@
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c2_default>;
- pinctrl-1 = <&i2c2_sleep>;
+ pinctrl-0 = <&blsp_i2c2_default>;
+ pinctrl-1 = <&blsp_i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1609,8 +2251,8 @@
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi2_default>;
- pinctrl-1 = <&spi2_sleep>;
+ pinctrl-0 = <&blsp_spi2_default>;
+ pinctrl-1 = <&blsp_spi2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1623,9 +2265,11 @@
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c3_default>;
- pinctrl-1 = <&i2c3_sleep>;
+ pinctrl-0 = <&blsp_i2c3_default>;
+ pinctrl-1 = <&blsp_i2c3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1641,8 +2285,8 @@
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi3_default>;
- pinctrl-1 = <&spi3_sleep>;
+ pinctrl-0 = <&blsp_spi3_default>;
+ pinctrl-1 = <&blsp_spi3_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1655,9 +2299,11 @@
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c4_default>;
- pinctrl-1 = <&i2c4_sleep>;
+ pinctrl-0 = <&blsp_i2c4_default>;
+ pinctrl-1 = <&blsp_i2c4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1673,8 +2319,8 @@
dmas = <&blsp_dma 10>, <&blsp_dma 11>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi4_default>;
- pinctrl-1 = <&spi4_sleep>;
+ pinctrl-0 = <&blsp_spi4_default>;
+ pinctrl-1 = <&blsp_spi4_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1687,9 +2333,11 @@
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c5_default>;
- pinctrl-1 = <&i2c5_sleep>;
+ pinctrl-0 = <&blsp_i2c5_default>;
+ pinctrl-1 = <&blsp_i2c5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1705,8 +2353,8 @@
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi5_default>;
- pinctrl-1 = <&spi5_sleep>;
+ pinctrl-0 = <&blsp_spi5_default>;
+ pinctrl-1 = <&blsp_spi5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1719,9 +2367,11 @@
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&i2c6_default>;
- pinctrl-1 = <&i2c6_sleep>;
+ pinctrl-0 = <&blsp_i2c6_default>;
+ pinctrl-1 = <&blsp_i2c6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1737,8 +2387,8 @@
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi6_default>;
- pinctrl-1 = <&spi6_sleep>;
+ pinctrl-0 = <&blsp_spi6_default>;
+ pinctrl-1 = <&blsp_spi6_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1785,7 +2435,7 @@
};
};
- pronto: remoteproc@a21b000 {
+ wcnss: remoteproc@a204000 {
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
@@ -1807,13 +2457,12 @@
qcom,smem-state-names = "stop";
pinctrl-names = "default";
- pinctrl-0 = <&wcnss_pin_a>;
+ pinctrl-0 = <&wcss_wlan_default>;
status = "disabled";
- iris {
- compatible = "qcom,wcn3620";
-
+ wcnss_iris: iris {
+ /* Separate chip, compatible is board-specific */
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
clock-names = "xo";
};
@@ -1821,7 +2470,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 17>;
+ mboxes = <&apcs 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
@@ -1831,13 +2480,13 @@
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
- qcom,mmio = <&pronto>;
+ qcom,mmio = <&wcnss>;
- bluetooth {
+ wcnss_bt: bluetooth {
compatible = "qcom,wcnss-bt";
};
- wifi {
+ wcnss_wifi: wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
@@ -1988,7 +2637,6 @@
thermal-zones {
cpu0-1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 5>;
@@ -1998,7 +2646,7 @@
hysteresis = <2000>;
type = "passive";
};
- cpu0_1_crit: cpu_crit {
+ cpu0_1_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -2008,17 +2656,16 @@
cooling-maps {
map0 {
trip = <&cpu0_1_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
@@ -2028,7 +2675,7 @@
hysteresis = <2000>;
type = "passive";
};
- cpu2_3_crit: cpu_crit {
+ cpu2_3_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -2038,27 +2685,33 @@
cooling-maps {
map0 {
trip = <&cpu2_3_alert0>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
gpu_alert0: trip-point0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
- gpu_crit: gpu_crit {
+ gpu_crit: gpu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -2068,7 +2721,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 1>;
@@ -2083,7 +2735,6 @@
modem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens 0>;
@@ -2095,7 +2746,6 @@
};
};
};
-
};
timer {
@@ -2106,5 +2756,3 @@
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};
-
-#include "msm8916-pins.dtsi"
generated by cgit (git 2.34.1) at 2025-12-28 20:39:22 +0000