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Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8953.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8953.dtsi414
1 files changed, 326 insertions, 88 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 5d818fe057dd..76317c578349 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -1,9 +1,12 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,msm8953.h>
+#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
@@ -38,125 +41,141 @@
#address-cells = <1>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_0>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_0>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
- CPU2: cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_0>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
- CPU3: cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_0>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
- CPU4: cpu@100 {
+ cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_1>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
- CPU5: cpu@101 {
+ cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_1>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
- CPU6: cpu@102 {
+ cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_1>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
- CPU7: cpu@103 {
+ cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&L2_1>;
+ interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &bimc SLV_EBI RPM_ACTIVE_TAG>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
core1 {
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
core2 {
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
core3 {
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
};
cluster1 {
core0 {
- cpu = <&CPU4>;
+ cpu = <&cpu4>;
};
core1 {
- cpu = <&CPU5>;
+ cpu = <&cpu5>;
};
core2 {
- cpu = <&CPU6>;
+ cpu = <&cpu6>;
};
core3 {
- cpu = <&CPU7>;
+ cpu = <&cpu7>;
};
};
};
- L2_0: l2-cache-0 {
+ l2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
- L2_1: l2-cache-1 {
+ l2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -195,11 +214,11 @@
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 0>;
+ mboxes = <&apcs 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8953";
+ compatible = "qcom,rpm-msm8953", "qcom,smd-rpm";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
@@ -361,7 +380,7 @@
interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 14>;
+ mboxes = <&apcs 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -386,7 +405,7 @@
interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 18>;
+ mboxes = <&apcs 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
@@ -411,8 +430,7 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 8 13>;
- qcom,ipc-3 = <&apcs 8 19>;
+ mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>;
apps_smsm: apps@0 {
reg = <0>;
@@ -471,6 +489,13 @@
clock-names = "core";
};
+ bimc: interconnect@400000 {
+ compatible = "qcom,msm8953-bimc";
+ reg = <0x00400000 0x5a000>;
+
+ #interconnect-cells = <2>;
+ };
+
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
reg = <0x004a9000 0x1000>, /* TM */
@@ -487,6 +512,29 @@
reg = <0x004ab000 0x4>;
};
+ pcnoc: interconnect@500000 {
+ compatible = "qcom,msm8953-pcnoc";
+ reg = <0x00500000 0x12080>;
+
+ clocks = <&gcc GCC_PCNOC_USB3_AXI_CLK>;
+ clock-names = "pcnoc_usb3_axi";
+
+ #interconnect-cells = <2>;
+ };
+
+ snoc: interconnect@580000 {
+ compatible = "qcom,msm8953-snoc";
+ reg = <0x00580000 0x16080>;
+
+ #interconnect-cells = <2>;
+
+ snoc_mm: interconnect-snoc {
+ compatible = "qcom,msm8953-snoc-mm";
+
+ #interconnect-cells = <2>;
+ };
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8953-pinctrl";
reg = <0x01000000 0x300000>;
@@ -727,42 +775,142 @@
};
spi_3_default: spi-3-default-state {
- pins = "gpio10", "gpio11";
- function = "blsp_spi3";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio10";
+ function = "blsp_spi3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ drive-strength = <12>;
+ bias-disable;
+ };
};
spi_3_sleep: spi-3-sleep-state {
- pins = "gpio10", "gpio11";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
spi_5_default: spi-5-default-state {
- pins = "gpio18", "gpio19";
- function = "blsp_spi5";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio18";
+ function = "blsp_spi5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
+ drive-strength = <12>;
+ bias-disable;
+ };
};
spi_5_sleep: spi-5-sleep-state {
- pins = "gpio18", "gpio19";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
};
spi_6_default: spi-6-default-state {
- pins = "gpio22", "gpio23";
- function = "blsp_spi6";
- drive-strength = <2>;
- bias-disable;
+ cs-pins {
+ pins = "gpio22";
+ function = "blsp_spi6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ drive-strength = <12>;
+ bias-disable;
+ };
};
spi_6_sleep: spi-6-sleep-state {
- pins = "gpio22", "gpio23";
+ cs-pins {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ spi_7_default: spi-7-default-state {
+ cs-pins {
+ pins = "gpio136";
+ function = "blsp_spi7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio135", "gpio137", "gpio138";
+ function = "blsp_spi7";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
+
+ spi_7_sleep: spi-7-sleep-state {
+ cs-pins {
+ pins = "gpio136";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ spi-pins {
+ pins = "gpio135", "gpio137", "gpio138";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ uart_5_default: uart-5-default-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "blsp_uart5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ uart_5_sleep: uart-5-sleep-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-disable;
@@ -808,10 +956,10 @@
#power-domain-cells = <1>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
- <&mdss_dsi0_phy 1>,
- <&mdss_dsi0_phy 0>,
- <&mdss_dsi1_phy 1>,
- <&mdss_dsi1_phy 0>;
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>;
clock-names = "xo",
"sleep",
"dsi0pll",
@@ -850,6 +998,13 @@
interrupt-controller;
#interrupt-cells = <1>;
+ interconnects = <&snoc_mm MAS_MDP RPM_ALWAYS_TAG
+ &bimc SLV_EBI RPM_ALWAYS_TAG>,
+ <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &pcnoc SLV_DISP_SS_CFG RPM_ACTIVE_TAG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>,
@@ -918,8 +1073,8 @@
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi0_phy 0>,
- <&mdss_dsi0_phy 1>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
@@ -988,8 +1143,8 @@
assigned-clocks = <&gcc BYTE1_CLK_SRC>,
<&gcc PCLK1_CLK_SRC>;
- assigned-clock-parents = <&mdss_dsi1_phy 0>,
- <&mdss_dsi1_phy 1>;
+ assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
@@ -1066,6 +1221,11 @@
"alwayson";
power-domains = <&gcc OXILI_GX_GDSC>;
+ interconnects = <&bimc MAS_OXILI RPM_ALWAYS_TAG
+ &bimc SLV_EBI RPM_ALWAYS_TAG>,
+ <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &pcnoc SLV_GPU_CFG RPM_ACTIVE_TAG>;
+
iommus = <&gpu_iommu 0>;
operating-points-v2 = <&gpu_opp_table>;
@@ -1073,7 +1233,7 @@
status = "disabled";
- zap-shader {
+ gpu_zap_shader: zap-shader {
memory-region = <&zap_shader_region>;
};
@@ -1267,7 +1427,7 @@
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
qcom,smd-edge = <0>;
- qcom,ipc = <&apcs 8 12>;
+ mboxes = <&apcs 12>;
qcom,remote-pid = <1>;
label = "modem";
@@ -1303,6 +1463,13 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <133330000>;
+ interconnects = <&pcnoc MAS_USB3 RPM_ALWAYS_TAG
+ &bimc SLV_EBI RPM_ALWAYS_TAG>,
+ <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &pcnoc SLV_USB3 RPM_ACTIVE_TAG>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
power-domains = <&gcc USB30_GDSC>;
qcom,select-utmi-as-pipe-clk;
@@ -1355,6 +1522,13 @@
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
+ interconnects = <&pcnoc MAS_SDCC_1 RPM_ALWAYS_TAG
+ &bimc SLV_EBI RPM_ALWAYS_TAG>,
+ <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &pcnoc SLV_SDCC_1 RPM_ACTIVE_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
power-domains = <&rpmpd MSM8953_VDDCX>;
operating-points-v2 = <&sdhc1_opp_table>;
@@ -1375,26 +1549,36 @@
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
+ opp-peak-kBps = <200000>, <100000>;
+ opp-avg-kBps = <65360>, <32768>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
+ opp-peak-kBps = <400000>, <200000>;
+ opp-avg-kBps = <130718>, <65360>;
required-opps = <&rpmpd_opp_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <400000>, <400000>;
+ opp-avg-kBps = <130718>, <65360>;
required-opps = <&rpmpd_opp_svs>;
};
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
+ opp-peak-kBps = <800000>, <600000>;
+ opp-avg-kBps = <261438>, <130718>;
required-opps = <&rpmpd_opp_nom>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
+ opp-peak-kBps = <800000>, <800000>;
+ opp-avg-kBps = <261438>, <300000>;
required-opps = <&rpmpd_opp_nom>;
};
};
@@ -1415,6 +1599,13 @@
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
+ interconnects = <&pcnoc MAS_SDCC_2 RPM_ALWAYS_TAG
+ &bimc SLV_EBI RPM_ALWAYS_TAG>,
+ <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG
+ &pcnoc SLV_SDCC_2 RPM_ACTIVE_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
power-domains = <&rpmpd MSM8953_VDDCX>;
operating-points-v2 = <&sdhc2_opp_table>;
@@ -1431,26 +1622,36 @@
opp-25000000 {
opp-hz = /bits/ 64 <25000000>;
+ opp-peak-kBps = <200000>, <100000>;
+ opp-avg-kBps = <65360>, <32768>;
required-opps = <&rpmpd_opp_low_svs>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
+ opp-peak-kBps = <400000>, <400000>;
+ opp-avg-kBps = <130718>, <65360>;
required-opps = <&rpmpd_opp_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <800000>, <400000>;
+ opp-avg-kBps = <130718>, <130718>;
required-opps = <&rpmpd_opp_svs>;
};
opp-177770000 {
opp-hz = /bits/ 64 <177770000>;
+ opp-peak-kBps = <600000>, <600000>;
+ opp-avg-kBps = <261438>, <130718>;
required-opps = <&rpmpd_opp_nom>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
+ opp-peak-kBps = <800000>, <800000>;
+ opp-avg-kBps = <261438>, <130718>;
required-opps = <&rpmpd_opp_nom>;
};
};
@@ -1545,7 +1746,7 @@
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
- clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
dma-names = "tx", "rx";
@@ -1593,6 +1794,24 @@
qcom,controlled-remotely;
};
+ uart_5: serial@7aef000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x07aef000 0x200>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core",
+ "iface";
+ dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&uart_5_default>;
+ pinctrl-1 = <&uart_5_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ status = "disabled";
+ };
+
i2c_5: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af5000 0x600>;
@@ -1618,7 +1837,7 @@
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
- clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
dma-names = "tx", "rx";
@@ -1658,7 +1877,7 @@
reg = <0x07af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
- clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
+ clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
dma-names = "tx", "rx";
@@ -1693,6 +1912,26 @@
status = "disabled";
};
+ spi_7: spi@7af7000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x07af7000 0x600>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
+ dma-names = "tx", "rx";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi_7_default>;
+ pinctrl-1 = <&spi_7_sleep>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
i2c_8: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af8000 0x600>;
@@ -1748,7 +1987,7 @@
smd-edge {
interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
- qcom,ipc = <&apcs 8 17>;
+ mboxes = <&apcs 17>;
qcom,smd-edge = <6>;
qcom,remote-pid = <4>;
@@ -1933,19 +2172,19 @@
#sound-dai-cells = <1>;
dai@0 {
- reg = <0>;
+ reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
direction = <Q6ASM_DAI_RX>;
};
dai@1 {
- reg = <1>;
+ reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>;
direction = <Q6ASM_DAI_TX>;
};
dai@2 {
- reg = <2>;
+ reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>;
direction = <Q6ASM_DAI_RX>;
};
dai@3 {
- reg = <3>;
+ reg = <MSM_FRONTEND_DAI_MULTIMEDIA4>;
direction = <Q6ASM_DAI_RX>;
is-compress-dai;
};
@@ -1968,8 +2207,9 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 9>;
+
trips {
cpu0_alert: trip-point0 {
temperature = <80000>;
@@ -1985,14 +2225,15 @@
cooling-maps {
map0 {
trip = <&cpu0_alert>;
- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 10>;
+
trips {
cpu1_alert: trip-point0 {
temperature = <80000>;
@@ -2008,14 +2249,15 @@
cooling-maps {
map0 {
trip = <&cpu1_alert>;
- cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 11>;
+
trips {
cpu2_alert: trip-point0 {
temperature = <80000>;
@@ -2031,14 +2273,15 @@
cooling-maps {
map0 {
trip = <&cpu2_alert>;
- cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
+
thermal-sensors = <&tsens0 12>;
+
trips {
cpu3_alert: trip-point0 {
temperature = <80000>;
@@ -2054,13 +2297,12 @@
cooling-maps {
map0 {
trip = <&cpu3_alert>;
- cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
trips {
cpu4_alert: trip-point0 {
@@ -2077,13 +2319,12 @@
cooling-maps {
map0 {
trip = <&cpu4_alert>;
- cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
trips {
cpu5_alert: trip-point0 {
@@ -2100,13 +2341,12 @@
cooling-maps {
map0 {
trip = <&cpu5_alert>;
- cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
trips {
cpu6_alert: trip-point0 {
@@ -2123,13 +2363,12 @@
cooling-maps {
map0 {
trip = <&cpu6_alert>;
- cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
trips {
cpu7_alert: trip-point0 {
@@ -2146,14 +2385,13 @@
cooling-maps {
map0 {
trip = <&cpu7_alert>;
- cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 15>;
trips {
generated by cgit (git 2.34.1) at 2026-01-01 11:57:06 +0000