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-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi1170
1 files changed, 708 insertions, 462 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0a2baffa49d..9d4ce47578fb 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1,12 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-only
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/*
+ * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,msm8996.h>
+#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
+#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
@@ -40,84 +44,90 @@
#address-cells = <2>;
#size-cells = <0>;
- CPU0: cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
+ interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
- next-level-cache = <&L2_0>;
- L2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
+ next-level-cache = <&l2_0>;
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
- CPU1: cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 0>;
+ interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
- next-level-cache = <&L2_0>;
+ next-level-cache = <&l2_0>;
};
- CPU2: cpu@100 {
+ cpu2: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
+ interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
- next-level-cache = <&L2_1>;
- L2_1: l2-cache {
- compatible = "cache";
- cache-level = <2>;
+ next-level-cache = <&l2_1>;
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
};
};
- CPU3: cpu@101 {
+ cpu3: cpu@101 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
+ cpu-idle-states = <&cpu_sleep_0>;
capacity-dmips-mhz = <1024>;
clocks = <&kryocc 1>;
+ interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
- next-level-cache = <&L2_1>;
+ next-level-cache = <&l2_1>;
};
cpu-map {
cluster0 {
core0 {
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
core1 {
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
};
cluster1 {
core0 {
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
core1 {
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
};
};
@@ -125,7 +135,7 @@
idle-states {
entry-method = "psci";
- CPU_SLEEP_0: cpu-sleep-0 {
+ cpu_sleep_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x00000004>;
@@ -144,83 +154,111 @@
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-422400000 {
opp-hz = /bits/ 64 <422400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <384000>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <460800>;
};
opp-844800000 {
opp-hz = /bits/ 64 <844800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <537600>;
};
opp-960000000 {
opp-hz = /bits/ 64 <960000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <672000>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <672000>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <825600>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <825600>;
};
opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <902400>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xd>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1056000>;
+ };
+ opp-1363200000 {
+ opp-hz = /bits/ 64 <1363200000>;
+ opp-supported-hw = <0x2>;
+ clock-latency-ns = <200000>;
+ opp-peak-kBps = <1132800>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xd>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1132800>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x9>;
+ clock-latency-ns = <200000>;
+ opp-peak-kBps = <1190400>;
+ };
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-supported-hw = <0x04>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1305600>;
};
opp-1593600000 {
opp-hz = /bits/ 64 <1593600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x9>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1382400>;
};
};
@@ -232,128 +270,165 @@
/* Nominal fmax for now */
opp-307200000 {
opp-hz = /bits/ 64 <307200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-403200000 {
opp-hz = /bits/ 64 <403200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-556800000 {
opp-hz = /bits/ 64 <556800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-652800000 {
opp-hz = /bits/ 64 <652800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-729600000 {
opp-hz = /bits/ 64 <729600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <307200>;
};
opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <384000>;
};
opp-883200000 {
opp-hz = /bits/ 64 <883200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <460800>;
};
opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <537600>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <595200>;
};
opp-1113600000 {
opp-hz = /bits/ 64 <1113600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <672000>;
};
opp-1190400000 {
opp-hz = /bits/ 64 <1190400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <672000>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <748800>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <825600>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <902400>;
};
opp-1478400000 {
opp-hz = /bits/ 64 <1478400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <979200>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1056000>;
};
opp-1632000000 {
opp-hz = /bits/ 64 <1632000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1190400>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1228800>;
};
opp-1785600000 {
opp-hz = /bits/ 64 <1785600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ opp-peak-kBps = <1305600>;
+ };
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-supported-hw = <0xe>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1305600>;
};
opp-1824000000 {
opp-hz = /bits/ 64 <1824000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1382400>;
+ };
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-supported-hw = <0x4>;
+ clock-latency-ns = <200000>;
+ opp-peak-kBps = <1305600>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1459200>;
};
opp-1996800000 {
opp-hz = /bits/ 64 <1996800000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1593600>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1593600>;
};
opp-2150400000 {
opp-hz = /bits/ 64 <2150400000>;
- opp-supported-hw = <0x77>;
+ opp-supported-hw = <0x1>;
clock-latency-ns = <200000>;
+ opp-peak-kBps = <1593600>;
};
};
@@ -370,11 +445,81 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
+ etm {
+ compatible = "qcom,coresight-remote-etm";
+
+ out-ports {
+ port {
+ modem_etm_out_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel_in2_in_modem_etm>;
+ };
+ };
+ };
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
+ rpm: remoteproc {
+ compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm";
+ qcom,glink-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,msm8996-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp1: opp1 {
+ opp-level = <1>;
+ };
+
+ rpmpd_opp2: opp2 {
+ opp-level = <2>;
+ };
+
+ rpmpd_opp3: opp3 {
+ opp-level = <3>;
+ };
+
+ rpmpd_opp4: opp4 {
+ opp-level = <4>;
+ };
+
+ rpmpd_opp5: opp5 {
+ opp-level = <5>;
+ };
+
+ rpmpd_opp6: opp6 {
+ opp-level = <6>;
+ };
+ };
+ };
+ };
+ };
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -408,7 +553,7 @@
no-map;
qcom,client-id = <1>;
- qcom,vmid = <15>;
+ qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
};
mpss_mem: mpss@88800000 {
@@ -441,61 +586,11 @@
reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
- };
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
-
- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
-
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
-
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-msm8996";
- qcom,glink-channels = "rpm_requests";
-
- rpmcc: qcom,rpmcc {
- compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
- #clock-cells = <1>;
- clocks = <&xo_board>;
- clock-names = "xo";
- };
-
- rpmpd: power-controller {
- compatible = "qcom,msm8996-rpmpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmpd_opp_table>;
- rpmpd_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- rpmpd_opp1: opp1 {
- opp-level = <1>;
- };
-
- rpmpd_opp2: opp2 {
- opp-level = <2>;
- };
-
- rpmpd_opp3: opp3 {
- opp-level = <3>;
- };
-
- rpmpd_opp4: opp4 {
- opp-level = <4>;
- };
-
- rpmpd_opp5: opp5 {
- opp-level = <5>;
- };
-
- rpmpd_opp6: opp6 {
- opp-level = <6>;
- };
- };
- };
+ mdata_mem: mpss-metadata {
+ alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
+ size = <0x0 0x4000>;
+ no-map;
};
};
@@ -509,7 +604,7 @@
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
- interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
@@ -577,7 +672,7 @@
};
};
- soc: soc {
+ soc: soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
@@ -662,12 +757,12 @@
#address-cells = <1>;
#size-cells = <1>;
- qusb2p_hstx_trim: hstx_trim@24e {
+ qusb2p_hstx_trim: hstx-trim@24e {
reg = <0x24e 0x2>;
bits = <5 4>;
};
- qusb2s_hstx_trim: hstx_trim@24f {
+ qusb2s_hstx_trim: hstx-trim@24f {
reg = <0x24f 0x1>;
bits = <1 4>;
};
@@ -692,14 +787,16 @@
#power-domain-cells = <1>;
reg = <0x00300000 0x90000>;
- clocks = <&rpmcc RPM_SMD_BB_CLK1>,
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
<&sleep_clk>,
<&pciephy_0>,
<&pciephy_1>,
<&pciephy_2>,
- <&ssusb_phy_0>,
- <0>, <0>, <0>;
+ <&usb3phy>,
+ <&ufsphy 0>,
+ <&ufsphy 1>,
+ <&ufsphy 2>;
clock-names = "cxo",
"cxo2",
"sleep_clk",
@@ -716,9 +813,6 @@
compatible = "qcom,msm8996-bimc";
reg = <0x00408000 0x5a000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
- <&rpmcc RPM_SMD_BIMC_A_CLK>;
};
tsens0: thermal-sensor@4a9000 {
@@ -769,18 +863,12 @@
compatible = "qcom,msm8996-cnoc";
reg = <0x00500000 0x1000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
- <&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@524000 {
compatible = "qcom,msm8996-snoc";
reg = <0x00524000 0x1c000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
- <&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a0noc: interconnect@543000 {
@@ -800,37 +888,29 @@
compatible = "qcom,msm8996-a1noc";
reg = <0x00562000 0x5000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
- <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
};
a2noc: interconnect@583000 {
compatible = "qcom,msm8996-a2noc";
reg = <0x00583000 0x7000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
- <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
+ clock-names = "aggre2_ufs_axi", "ufs_axi";
+ clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ <&gcc GCC_UFS_AXI_CLK>;
};
mnoc: interconnect@5a4000 {
compatible = "qcom,msm8996-mnoc";
reg = <0x005a4000 0x1c000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a", "iface";
- clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
- <&rpmcc RPM_SMD_MMAXI_A_CLK>,
- <&mmcc AHB_CLK_SRC>;
+ clock-names = "iface";
+ clocks = <&mmcc AHB_CLK_SRC>;
};
pnoc: interconnect@5c0000 {
compatible = "qcom,msm8996-pnoc";
reg = <0x005c0000 0x3000>;
#interconnect-cells = <1>;
- clock-names = "bus", "bus_a";
- clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
- <&rpmcc RPM_SMD_PCNOC_A_CLK>;
};
tcsr_mutex: hwlock@740000 {
@@ -856,16 +936,16 @@
#power-domain-cells = <1>;
reg = <0x008c0000 0x40000>;
clocks = <&xo_board>,
- <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
<&gcc GPLL0>,
- <&dsi0_phy 1>,
- <&dsi0_phy 0>,
- <0>,
- <0>,
- <0>;
+ <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_hdmi_phy>;
clock-names = "xo",
- "gcc_mmss_noc_cfg_ahb_clk",
"gpll0",
+ "gcc_mmss_noc_cfg_ahb_clk",
"dsi0pll",
"dsi0pllbyte",
"dsi1pll",
@@ -883,7 +963,7 @@
<825000000>;
};
- mdss: mdss@900000 {
+ mdss: display-subsystem@900000 {
compatible = "qcom,mdss";
reg = <0x00900000 0x1000>,
@@ -903,14 +983,16 @@
<&mmcc MDSS_MDP_CLK>;
clock-names = "iface", "core";
+ resets = <&mmcc MDSS_BCR>;
+
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
- mdp: mdp@901000 {
- compatible = "qcom,mdp5";
+ mdp: display-controller@901000 {
+ compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
reg = <0x00901000 0x90000>;
reg-names = "mdp_phys";
@@ -947,28 +1029,29 @@
port@0 {
reg = <0>;
mdp5_intf3_out: endpoint {
- remote-endpoint = <&hdmi_in>;
+ remote-endpoint = <&mdss_hdmi_in>;
};
};
port@1 {
reg = <1>;
mdp5_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
+ remote-endpoint = <&mdss_dsi0_in>;
};
};
port@2 {
reg = <2>;
mdp5_intf2_out: endpoint {
- remote-endpoint = <&dsi1_in>;
+ remote-endpoint = <&mdss_dsi1_in>;
};
};
};
};
- dsi0: dsi@994000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ mdss_dsi0: dsi@994000 {
+ compatible = "qcom,msm8996-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0x00994000 0x400>;
reg-names = "dsi_ctrl";
@@ -989,11 +1072,12 @@
"core_mmss",
"pixel",
"core";
- assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+ assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
+ <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
- phys = <&dsi0_phy>;
- phy-names = "dsi";
+ phys = <&mdss_dsi0_phy>;
status = "disabled";
#address-cells = <1>;
@@ -1005,20 +1089,20 @@
port@0 {
reg = <0>;
- dsi0_in: endpoint {
+ mdss_dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
- dsi0_out: endpoint {
+ mdss_dsi0_out: endpoint {
};
};
};
};
- dsi0_phy: dsi-phy@994400 {
+ mdss_dsi0_phy: phy@994400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00994400 0x100>,
<0x00994500 0x300>,
@@ -1030,18 +1114,19 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
+ clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
- dsi1: dsi@996000 {
- compatible = "qcom,mdss-dsi-ctrl";
+ mdss_dsi1: dsi@996000 {
+ compatible = "qcom,msm8996-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
reg = <0x00996000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
- interrupts = <4>;
+ interrupts = <5>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE1_CLK>,
@@ -1057,11 +1142,12 @@
"core_mmss",
"pixel",
"core";
- assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
- assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
+ assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
+ <&mmcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
- phys = <&dsi1_phy>;
- phy-names = "dsi";
+ phys = <&mdss_dsi1_phy>;
status = "disabled";
#address-cells = <1>;
@@ -1073,20 +1159,20 @@
port@0 {
reg = <0>;
- dsi1_in: endpoint {
+ mdss_dsi1_in: endpoint {
remote-endpoint = <&mdp5_intf2_out>;
};
};
port@1 {
reg = <1>;
- dsi1_out: endpoint {
+ mdss_dsi1_out: endpoint {
};
};
};
};
- dsi1_phy: dsi-phy@996400 {
+ mdss_dsi1_phy: phy@996400 {
compatible = "qcom,dsi-phy-14nm";
reg = <0x00996400 0x100>,
<0x00996500 0x300>,
@@ -1098,16 +1184,16 @@
#clock-cells = <1>;
#phy-cells = <0>;
- clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
+ clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
};
- hdmi: hdmi-tx@9a0000 {
+ mdss_hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
- reg = <0x009a0000 0x50c>,
- <0x00070000 0x6158>,
- <0x009e0000 0xfff>;
+ reg = <0x009a0000 0x50c>,
+ <0x00070000 0x6158>,
+ <0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
@@ -1127,7 +1213,7 @@
"alt_iface",
"extp";
- phys = <&hdmi_phy>;
+ phys = <&mdss_hdmi_phy>;
#sound-dai-cells = <1>;
status = "disabled";
@@ -1138,14 +1224,14 @@
port@0 {
reg = <0>;
- hdmi_in: endpoint {
+ mdss_hdmi_in: endpoint {
remote-endpoint = <&mdp5_intf3_out>;
};
};
};
};
- hdmi_phy: hdmi-phy@9a0600 {
+ mdss_hdmi_phy: phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
@@ -1180,7 +1266,7 @@
reg = <0x00b00000 0x3f000>;
reg-names = "kgsl_3d0_reg_memory";
- interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
<&mmcc GPU_AHB_CLK>,
@@ -1213,41 +1299,41 @@
compatible = "operating-points-v2";
/*
- * 624Mhz and 560Mhz are only available on speed
- * bin (1 << 0). All the rest are available on
- * all bins of the hardware
+ * 624Mhz is only available on speed bins 0 and 3.
+ * 560Mhz is only available on speed bins 0, 2 and 3.
+ * All the rest are available on all bins of the hardware.
*/
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
- opp-supported-hw = <0x01>;
+ opp-supported-hw = <0x09>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
- opp-supported-hw = <0x01>;
+ opp-supported-hw = <0x0d>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
- opp-supported-hw = <0xFF>;
+ opp-supported-hw = <0xff>;
};
opp-401800000 {
opp-hz = /bits/ 64 <401800000>;
- opp-supported-hw = <0xFF>;
+ opp-supported-hw = <0xff>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
- opp-supported-hw = <0xFF>;
+ opp-supported-hw = <0xff>;
};
opp-214000000 {
opp-hz = /bits/ 64 <214000000>;
- opp-supported-hw = <0xFF>;
+ opp-supported-hw = <0xff>;
};
opp-133000000 {
opp-hz = /bits/ 64 <133000000>;
- opp-supported-hw = <0xFF>;
+ opp-supported-hw = <0xff>;
};
};
- zap-shader {
+ gpu_zap_shader: zap-shader {
memory-region = <&gpu_mem>;
};
};
@@ -1262,15 +1348,15 @@
interrupt-controller;
#interrupt-cells = <2>;
- blsp1_spi1_default: blsp1-spi1-default {
- spi {
+ blsp1_spi1_default: blsp1-spi1-default-state {
+ spi-pins {
pins = "gpio0", "gpio1", "gpio3";
function = "blsp_spi1";
drive-strength = <12>;
bias-disable;
};
- cs {
+ cs-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <16>;
@@ -1279,42 +1365,56 @@
};
};
- blsp1_spi1_sleep: blsp1-spi1-sleep {
+ blsp1_spi1_sleep: blsp1-spi1-sleep-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_uart2_2pins_default: blsp2-uart1-2pins {
+ blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
pins = "gpio4", "gpio5";
function = "blsp_uart8";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
+ blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
pins = "gpio4", "gpio5";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c2_default: blsp2-i2c2 {
+ blsp2_i2c2_default: blsp2-i2c2-state {
pins = "gpio6", "gpio7";
function = "blsp_i2c8";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- cci0_default: cci0-default {
+ blsp1_i2c6_default: blsp1-i2c6-state {
+ pins = "gpio27", "gpio28";
+ function = "blsp_i2c6";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_default: cci0-default-state {
pins = "gpio17", "gpio18";
function = "cci_i2c";
drive-strength = <16>;
@@ -1322,22 +1422,22 @@
};
camera0_state_on:
- camera_rear_default: camera-rear-default {
- camera0_mclk: mclk0 {
+ camera_rear_default: camera-rear-default-state {
+ camera0_mclk: mclk0-pins {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- camera0_rst: rst {
+ camera0_rst: rst-pins {
pins = "gpio25";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- camera0_pwdn: pwdn {
+ camera0_pwdn: pwdn-pins {
pins = "gpio26";
function = "gpio";
drive-strength = <16>;
@@ -1345,7 +1445,7 @@
};
};
- cci1_default: cci1-default {
+ cci1_default: cci1-default-state {
pins = "gpio19", "gpio20";
function = "cci_i2c";
drive-strength = <16>;
@@ -1353,22 +1453,22 @@
};
camera1_state_on:
- camera_board_default: camera-board-default {
- mclk1 {
+ camera_board_default: camera-board-default-state {
+ mclk1-pins {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- pwdn {
+ pwdn-pins {
pins = "gpio98";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- rst {
+ rst-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <16>;
@@ -1377,22 +1477,22 @@
};
camera2_state_on:
- camera_front_default: camera-front-default {
- camera2_mclk: mclk2 {
+ camera_front_default: camera-front-default-state {
+ camera2_mclk: mclk2-pins {
pins = "gpio15";
function = "cam_mclk";
drive-strength = <16>;
bias-disable;
};
- camera2_rst: rst {
+ camera2_rst: rst-pins {
pins = "gpio23";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
- pwdn {
+ pwdn-pins {
pins = "gpio133";
function = "gpio";
drive-strength = <16>;
@@ -1400,22 +1500,22 @@
};
};
- pcie0_state_on: pcie0-state-on {
- perst {
+ pcie0_state_on: pcie0-state-on-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -1423,22 +1523,22 @@
};
};
- pcie0_state_off: pcie0-state-off {
- perst {
+ pcie0_state_off: pcie0-state-off-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -1446,85 +1546,84 @@
};
};
- blsp1_uart2_default: blsp1-uart2-default {
+ blsp1_uart2_default: blsp1-uart2-default-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
drive-strength = <16>;
bias-disable;
};
- blsp1_uart2_sleep: blsp1-uart2-sleep {
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp1_i2c3_default: blsp1-i2c2-default {
+ blsp1_i2c3_default: blsp1-i2c3-default-state {
pins = "gpio47", "gpio48";
function = "blsp_i2c3";
drive-strength = <16>;
bias-disable;
};
- blsp1_i2c3_sleep: blsp1-i2c2-sleep {
+ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
pins = "gpio47", "gpio48";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_uart3_4pins_default: blsp2-uart2-4pins {
+ blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <16>;
bias-disable;
};
- blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
+ blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
pins = "gpio49", "gpio50", "gpio51", "gpio52";
function = "blsp_uart9";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c3_default: blsp2-i2c3 {
+ blsp2_i2c3_default: blsp2-i2c3-state-state {
pins = "gpio51", "gpio52";
function = "blsp_i2c9";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c3_sleep: blsp2-i2c3-sleep {
+ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
pins = "gpio51", "gpio52";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wcd_intr_default: wcd-intr-default{
+ wcd_intr_default: wcd-intr-default-state {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
- input-enable;
};
- blsp2_i2c1_default: blsp2-i2c1 {
+ blsp2_i2c1_default: blsp2-i2c1-state {
pins = "gpio55", "gpio56";
function = "blsp_i2c7";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c1_sleep: blsp2-i2c0-sleep {
+ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
pins = "gpio55", "gpio56";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- blsp2_i2c5_default: blsp2-i2c5 {
+ blsp2_i2c5_default: blsp2-i2c5-state {
pins = "gpio60", "gpio61";
function = "blsp_i2c11";
drive-strength = <2>;
@@ -1533,7 +1632,7 @@
/* Sleep state for BLSP2_I2C5 is missing.. */
- cdc_reset_active: cdc-reset-active {
+ cdc_reset_active: cdc-reset-active-state {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
@@ -1541,7 +1640,7 @@
output-high;
};
- cdc_reset_sleep: cdc-reset-sleep {
+ cdc_reset_sleep: cdc-reset-sleep-state {
pins = "gpio64";
function = "gpio";
drive-strength = <16>;
@@ -1549,15 +1648,15 @@
output-low;
};
- blsp2_spi6_default: blsp2-spi5-default {
- spi {
+ blsp2_spi6_default: blsp2-spi6-default-state {
+ spi-pins {
pins = "gpio85", "gpio86", "gpio88";
function = "blsp_spi12";
drive-strength = <12>;
bias-disable;
};
- cs {
+ cs-pins {
pins = "gpio87";
function = "gpio";
drive-strength = <16>;
@@ -1566,43 +1665,43 @@
};
};
- blsp2_spi6_sleep: blsp2-spi5-sleep {
+ blsp2_spi6_sleep: blsp2-spi6-sleep-state {
pins = "gpio85", "gpio86", "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- blsp2_i2c6_default: blsp2-i2c6 {
+ blsp2_i2c6_default: blsp2-i2c6-state {
pins = "gpio87", "gpio88";
function = "blsp_i2c12";
drive-strength = <16>;
bias-disable;
};
- blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
pins = "gpio87", "gpio88";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- pcie1_state_on: pcie1-state-on {
- perst {
+ pcie1_state_on: pcie1-on-state {
+ perst-pins {
pins = "gpio130";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio131";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
@@ -1610,16 +1709,16 @@
};
};
- pcie1_state_off: pcie1-state-off {
+ pcie1_state_off: pcie1-off-state {
/* Perst is missing? */
- clkreq {
+ clkreq-pins {
pins = "gpio131";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio132";
function = "gpio";
drive-strength = <2>;
@@ -1627,22 +1726,22 @@
};
};
- pcie2_state_on: pcie2-state-on {
- perst {
+ pcie2_state_on: pcie2-on-state {
+ perst-pins {
pins = "gpio114";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio115";
function = "pci_e2";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
@@ -1650,16 +1749,16 @@
};
};
- pcie2_state_off: pcie2-state-off {
+ pcie2_state_off: pcie2-off-state {
/* Perst is missing? */
- clkreq {
+ clkreq-pins {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
- wake {
+ wake-pins {
pins = "gpio116";
function = "gpio";
drive-strength = <2>;
@@ -1667,90 +1766,90 @@
};
};
- sdc1_state_on: sdc1-state-on {
- clk {
+ sdc1_state_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_state_off: sdc1-state-off {
- clk {
+ sdc1_state_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_state_on: sdc2-clk-on {
- clk {
+ sdc2_state_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
- sdc2_state_off: sdc2-clk-off {
- clk {
+ sdc2_state_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
@@ -1781,12 +1880,12 @@
#interrupt-cells = <4>;
};
- agnoc@0 {
+ bus@0 {
power-domains = <&gcc AGGRE0_NOC_GDSC>;
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x0 0xffffffff>;
pcie0: pcie@600000 {
compatible = "qcom,pcie-msm8996";
@@ -1806,19 +1905,33 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
- <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
device_type = "pci";
- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_state_on>;
@@ -1838,6 +1951,15 @@
"bus_master",
"bus_slave";
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1: pcie@608000 {
@@ -1860,19 +1982,33 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
- <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
device_type = "pci";
- interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_state_on>;
@@ -1891,6 +2027,16 @@
"cfg",
"bus_master",
"bus_slave";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2: pcie@610000 {
@@ -1911,19 +2057,33 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
- <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
+ ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
+ <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
device_type = "pci";
- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
- <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
- <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
- <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_state_on>;
@@ -1941,6 +2101,16 @@
"cfg",
"bus_master",
"bus_slave";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
@@ -1950,30 +2120,26 @@
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufsphy_lane>;
+ phys = <&ufsphy>;
phy-names = "ufsphy";
power-domains = <&gcc UFS_GDSC>;
clock-names =
- "core_clk_src",
"core_clk",
"bus_clk",
"bus_aggr_clk",
"iface_clk",
- "core_clk_unipro_src",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks =
- <&gcc UFS_AXI_CLK_SRC>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_UFS_AHB_CLK>,
- <&gcc UFS_ICE_CORE_CLK_SRC>,
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_ICE_CORE_CLK>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
@@ -1984,46 +2150,38 @@
<0 0>,
<0 0>,
<0 0>,
- <0 0>,
+ <75000000 150000000>,
<150000000 300000000>,
<0 0>,
<0 0>,
- <0 0>,
- <0 0>,
<0 0>;
+ interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
+ <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
lanes-per-direction = <1>;
#reset-cells = <1>;
status = "disabled";
-
- ufs_variant {
- compatible = "qcom,ufs_variant";
- };
};
ufsphy: phy@627000 {
compatible = "qcom,msm8996-qmp-ufs-phy";
- reg = <0x00627000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x00627000 0x1000>;
- clocks = <&gcc GCC_UFS_CLKREF_CLK>;
- clock-names = "ref";
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>;
+ clock-names = "ref", "qref";
resets = <&ufshc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufsphy_lane: phy@627400 {
- reg = <0x627400 0x12c>,
- <0x627600 0x200>,
- <0x627c00 0x1b4>;
- #phy-cells = <0>;
- };
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
};
- camss: camss@a00000 {
+ camss: camss@a34000 {
compatible = "qcom,msm8996-camss";
reg = <0x00a34000 0x1000>,
<0x00a00030 0x4>,
@@ -2205,9 +2363,9 @@
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc GPU_AHB_CLK>,
- <&gcc GCC_MMSS_BIMC_GFX_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
+ <&mmcc GPU_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc GPU_GDSC>;
};
@@ -2272,9 +2430,9 @@
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- clocks = <&mmcc SMMU_MDP_AHB_CLK>,
- <&mmcc SMMU_MDP_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_MDP_AXI_CLK>,
+ <&mmcc SMMU_MDP_AHB_CLK>;
+ clock-names = "bus", "iface";
power-domains = <&mmcc MDSS_GDSC>;
};
@@ -2292,9 +2450,9 @@
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
- clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
- <&mmcc SMMU_VIDEO_AXI_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
+ <&mmcc SMMU_VIDEO_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
status = "okay";
};
@@ -2308,10 +2466,9 @@
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
- clocks = <&mmcc SMMU_VFE_AHB_CLK>,
- <&mmcc SMMU_VFE_AXI_CLK>;
- clock-names = "iface",
- "bus";
+ clocks = <&mmcc SMMU_VFE_AXI_CLK>,
+ <&mmcc SMMU_VFE_AHB_CLK>;
+ clock-names = "bus", "iface";
#iommu-cells = <1>;
};
@@ -2336,9 +2493,9 @@
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
- <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
- clock-names = "iface", "bus";
+ clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
+ <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
+ clock-names = "bus", "iface";
};
slpi_pil: remoteproc@1c00000 {
@@ -2356,9 +2513,8 @@
"handover",
"stop-ack";
- clocks = <&xo_board>,
- <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
- clock-names = "xo", "aggre2";
+ clocks = <&xo_board>;
+ clock-names = "xo";
memory-region = <&slpi_mem>;
@@ -2370,6 +2526,13 @@
status = "disabled";
+ glink-edge {
+ interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ label = "dsps";
+ qcom,remote-pid = <3>;
+ mboxes = <&apcs_glb 27>;
+ };
+
smd-edge {
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
@@ -2403,10 +2566,15 @@
<&gcc GCC_MSS_GPLL0_DIV_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
- <&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_QDSS_CLK>;
- clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
- "snoc_axi", "mnoc_axi", "pnoc", "qdss";
+ clock-names = "iface",
+ "bus",
+ "mem",
+ "xo",
+ "gpll0_mss",
+ "snoc_axi",
+ "mnoc_axi",
+ "qdss";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
@@ -2430,6 +2598,17 @@
memory-region = <&mpss_mem>;
};
+ metadata {
+ memory-region = <&mdata_mem>;
+ };
+
+ glink-edge {
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 15>;
+ };
+
smd-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
@@ -2543,6 +2722,14 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
+ in-ports {
+ port {
+ funnel_in2_in_modem_etm: endpoint {
+ remote-endpoint =
+ <&modem_etm_out_funnel_in2>;
+ };
+ };
+ };
out-ports {
port {
@@ -2689,7 +2876,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
};
etm@3840000 {
@@ -2699,7 +2886,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU0>;
+ cpu = <&cpu0>;
out-ports {
port {
@@ -2718,7 +2905,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
};
etm@3940000 {
@@ -2728,7 +2915,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU1>;
+ cpu = <&cpu1>;
out-ports {
port {
@@ -2783,7 +2970,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
};
etm@3a40000 {
@@ -2793,7 +2980,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU2>;
+ cpu = <&cpu2>;
out-ports {
port {
@@ -2812,7 +2999,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
};
etm@3b40000 {
@@ -2822,7 +3009,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
- cpu = <&CPU3>;
+ cpu = <&cpu3>;
out-ports {
port {
@@ -2912,8 +3099,8 @@
compatible = "qcom,msm8996-apcc";
reg = <0x06400000 0x90000>;
- clock-names = "xo";
- clocks = <&rpmcc RPM_SMD_BB_CLK1>;
+ clock-names = "xo", "sys_apcs_aux";
+ clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
#clock-cells = <1>;
};
@@ -2925,9 +3112,14 @@
#size-cells = <1>;
ranges;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
@@ -2954,42 +3146,40 @@
usb3_dwc3: usb@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
- interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&hsusb_phy1>, <&ssusb_phy_0>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hsusb_phy1>, <&usb3phy>;
phy-names = "usb2-phy", "usb3-phy";
+ snps,hird-threshold = /bits/ 8 <0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ snps,is-utmi-l1-suspend;
+ snps,parkmode-disable-ss-quirk;
+ tx-fifo-resize;
};
};
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
- reg = <0x07410000 0x1c4>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ reg = <0x07410000 0x1000>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
+ <&gcc GCC_USB3_CLKREF_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "cfg_ahb",
+ "pipe";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
resets = <&gcc GCC_USB3_PHY_BCR>,
- <&gcc GCC_USB3PHY_PHY_BCR>;
- reset-names = "phy", "common";
- status = "disabled";
+ <&gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
- ssusb_phy_0: phy@7410200 {
- reg = <0x07410200 0x200>,
- <0x07410400 0x130>,
- <0x07410600 0x1a8>;
- #phy-cells = <0>;
-
- #clock-cells = <0>;
- clock-output-names = "usb3_phy_pipe_clk_src";
- clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- };
+ status = "disabled";
};
hsusb_phy1: phy@7411000 {
@@ -3032,7 +3222,7 @@
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
- <&rpmcc RPM_SMD_BB_CLK1>;
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
resets = <&gcc GCC_SDCC1_BCR>;
pinctrl-names = "default", "sleep";
@@ -3056,7 +3246,7 @@
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
- <&rpmcc RPM_SMD_BB_CLK1>;
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
resets = <&gcc GCC_SDCC2_BCR>;
pinctrl-names = "default", "sleep";
@@ -3127,6 +3317,23 @@
status = "disabled";
};
+ blsp1_i2c6: i2c@757a000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x757a000 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c6_default>;
+ pinctrl-1 = <&blsp1_i2c6_sleep>;
+ dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp2_dma: dma-controller@7584000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07584000 0x2b000>;
@@ -3243,7 +3450,7 @@
status = "disabled";
};
- blsp2_spi6: spi@75ba000{
+ blsp2_spi6: spi@75ba000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -3267,6 +3474,13 @@
#size-cells = <1>;
ranges;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq";
+
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
@@ -3282,6 +3496,9 @@
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
+ interconnects = <&pnoc MASTER_USB_HS &bimc SLAVE_EBI_CH0>,
+ <&bimc MASTER_AMPSS_M0 &pnoc SLAVE_USB_HS>;
+ interconnect-names = "usb-ddr", "apps-usb";
power-domains = <&gcc USB30_GDSC>;
qcom,select-utmi-as-pipe-clk;
status = "disabled";
@@ -3289,7 +3506,7 @@
usb2_dwc3: usb@7600000 {
compatible = "snps,dwc3";
reg = <0x07600000 0xcc00>;
- interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
@@ -3303,52 +3520,22 @@
qcom,controlled-remotely;
reg = <0x09184000 0x32000>;
num-channels = <31>;
- interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
};
- slim_msm: slim@91c0000 {
+ slim_msm: slim-ngd@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
- reg = <0x091c0000 0x2C000>;
- reg-names = "ctrl";
- interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&slimbam 3>, <&slimbam 4>,
- <&slimbam 5>, <&slimbam 6>;
- dma-names = "rx", "tx", "tx2", "rx2";
+ reg = <0x091c0000 0x2c000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&slimbam 3>, <&slimbam 4>;
+ dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
- ngd@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- tasha_ifd: tas-ifd {
- compatible = "slim217,1a0";
- reg = <0 0>;
- };
-
- wcd9335: codec@1{
- pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
- pinctrl-names = "default";
-
- compatible = "slim217,1a0";
- reg = <1 0>;
-
- interrupt-parent = <&tlmm>;
- interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
- <53 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "intr1", "intr2";
- interrupt-controller;
- #interrupt-cells = <1>;
- reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
-
- slim-ifc-dev = <&tasha_ifd>;
- #sound-dai-cells = <1>;
- };
- };
+ status = "disabled";
};
adsp_pil: remoteproc@9300000 {
@@ -3363,7 +3550,7 @@
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
- clocks = <&rpmcc RPM_SMD_BB_CLK1>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
memory-region = <&adsp_mem>;
@@ -3376,6 +3563,14 @@
status = "disabled";
+ glink-edge {
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ mboxes = <&apcs_glb 9>;
+ };
+
+
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
@@ -3383,8 +3578,7 @@
mboxes = <&apcs_glb 8>;
qcom,smd-edge = <1>;
qcom,remote-pid = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
+
apr {
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
compatible = "qcom,apr-v2";
@@ -3393,12 +3587,12 @@
#address-cells = <1>;
#size-cells = <0>;
- q6core {
+ service@3 {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
- q6afe: q6afe {
+ q6afe: service@4 {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
@@ -3406,13 +3600,13 @@
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
- hdmi@1 {
+ dai@1 {
reg = <1>;
};
};
};
- q6asm: q6asm {
+ q6asm: service@7 {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
@@ -3424,7 +3618,7 @@
};
};
- q6adm: q6adm {
+ q6adm: service@8 {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
@@ -3434,6 +3628,62 @@
};
};
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,smd-channels = "fastrpcsmd-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&lpass_q6_smmu 5>;
+ };
+
+ cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&lpass_q6_smmu 6>;
+ };
+
+ cb@7 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <7>;
+ iommus = <&lpass_q6_smmu 7>;
+ };
+
+ cb@8 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <8>;
+ iommus = <&lpass_q6_smmu 8>;
+ };
+
+ cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&lpass_q6_smmu 9>;
+ };
+
+ cb@10 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <10>;
+ iommus = <&lpass_q6_smmu 10>;
+ };
+
+ cb@11 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <11>;
+ iommus = <&lpass_q6_smmu 11>;
+ };
+
+ cb@12 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <12>;
+ iommus = <&lpass_q6_smmu 12>;
+ };
+ };
};
};
@@ -3442,6 +3692,7 @@
reg = <0x09820000 0x1000>;
#mbox-cells = <1>;
+ #clock-cells = <0>;
};
timer@9840000 {
@@ -3504,12 +3755,21 @@
};
saw3: syscon@9a10000 {
- compatible = "qcom,tcsr-msm8996", "syscon";
+ compatible = "syscon";
reg = <0x09a10000 0x1000>;
};
+ cbf: clock-controller@9a11000 {
+ compatible = "qcom,msm8996-cbf";
+ reg = <0x09a11000 0x10000>;
+ clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
+ #clock-cells = <0>;
+ #interconnect-cells = <1>;
+ };
+
intc: interrupt-controller@9bc0000 {
compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
+ #address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
@@ -3526,7 +3786,6 @@
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
@@ -3537,7 +3796,7 @@
type = "passive";
};
- cpu0_crit: cpu_crit {
+ cpu0_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -3547,7 +3806,6 @@
cpu1-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
@@ -3558,7 +3816,7 @@
type = "passive";
};
- cpu1_crit: cpu_crit {
+ cpu1_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -3568,7 +3826,6 @@
cpu2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
@@ -3579,7 +3836,7 @@
type = "passive";
};
- cpu2_crit: cpu_crit {
+ cpu2_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -3589,7 +3846,6 @@
cpu3-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
@@ -3600,7 +3856,7 @@
type = "passive";
};
- cpu3_crit: cpu_crit {
+ cpu3_crit: cpu-crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
@@ -3610,7 +3866,6 @@
gpu-top-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
@@ -3632,7 +3887,6 @@
gpu-bottom-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
@@ -3654,7 +3908,6 @@
m4m-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
@@ -3669,7 +3922,6 @@
l3-or-venus-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
@@ -3684,7 +3936,6 @@
cluster0-l2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
@@ -3699,7 +3950,6 @@
cluster1-l2-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
@@ -3714,7 +3964,6 @@
camera-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
@@ -3729,7 +3978,6 @@
q6-dsp-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
@@ -3744,7 +3992,6 @@
mem-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
@@ -3759,7 +4006,6 @@
modemtx-thermal {
polling-delay-passive = <250>;
- polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
generated by cgit (git 2.34.1) at 2026-01-01 05:06:59 +0000