diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sa8775p.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1179 |
1 files changed, 939 insertions, 240 deletions
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3394ae2d1300..45f536633f64 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -471,17 +471,17 @@ cluster_0_pd: power-domain-cluster0 { #power-domain-cells = <0>; - power-domains = <&cluster_2_pd>; domain-idle-states = <&cluster_sleep_gold>; + power-domains = <&system_pd>; }; cluster_1_pd: power-domain-cluster1 { #power-domain-cells = <0>; - power-domains = <&cluster_2_pd>; domain-idle-states = <&cluster_sleep_gold>; + power-domains = <&system_pd>; }; - cluster_2_pd: power-domain-cluster2 { + system_pd: power-domain-system { #power-domain-cells = <0>; domain-idle-states = <&cluster_sleep_apss_rsc_pc>; }; @@ -913,6 +913,8 @@ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c14_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -938,6 +940,8 @@ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi14_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -961,6 +965,8 @@ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -978,6 +984,8 @@ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c15_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1003,6 +1011,8 @@ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi15_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1026,6 +1036,8 @@ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart15_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1043,6 +1055,8 @@ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c16_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1066,6 +1080,8 @@ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1091,6 +1107,8 @@ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart16_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1108,6 +1126,8 @@ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c17_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1133,6 +1153,8 @@ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi17_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1156,6 +1178,8 @@ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1171,6 +1195,8 @@ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1198,6 +1224,8 @@ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi18_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1221,6 +1249,8 @@ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart18_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1238,6 +1268,8 @@ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c19_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1263,6 +1295,8 @@ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi19_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1286,6 +1320,8 @@ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart19_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1303,6 +1339,8 @@ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c20_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1328,6 +1366,8 @@ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi20_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1351,6 +1391,8 @@ interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart20_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1404,6 +1446,8 @@ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1429,6 +1473,8 @@ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1452,6 +1498,8 @@ interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1469,6 +1517,8 @@ interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1494,6 +1544,8 @@ interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1517,6 +1569,8 @@ interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1534,6 +1588,8 @@ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1559,6 +1615,8 @@ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1582,6 +1640,8 @@ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1599,6 +1659,8 @@ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1624,6 +1686,8 @@ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1647,6 +1711,8 @@ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1664,6 +1730,8 @@ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1689,6 +1757,8 @@ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi4_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1712,6 +1782,8 @@ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1729,6 +1801,8 @@ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1754,6 +1828,8 @@ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1777,6 +1853,8 @@ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1829,6 +1907,8 @@ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1854,6 +1934,8 @@ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi7_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1877,6 +1959,8 @@ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, @@ -1895,6 +1979,8 @@ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1920,6 +2006,8 @@ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi8_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1943,6 +2031,8 @@ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, @@ -1961,6 +2051,8 @@ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1986,6 +2078,8 @@ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi9_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2009,6 +2103,8 @@ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2026,6 +2122,8 @@ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c10_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2051,6 +2149,8 @@ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi10_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2074,6 +2174,8 @@ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, @@ -2092,6 +2194,8 @@ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2117,6 +2221,8 @@ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi11_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2140,6 +2246,8 @@ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-0 = <&qup_uart11_default>; + pinctrl-names = "default"; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, @@ -2158,6 +2266,8 @@ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c12_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2183,6 +2293,8 @@ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi12_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2206,6 +2318,8 @@ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2223,6 +2337,8 @@ interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c13_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2276,6 +2392,8 @@ interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_i2c21_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2301,6 +2419,8 @@ interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; clock-names = "se"; + pinctrl-0 = <&qup_spi21_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2325,6 +2445,8 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; interconnect-names = "qup-core", "qup-config"; + pinctrl-0 = <&qup_uart21_default>; + pinctrl-names = "default"; interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -2413,20 +2535,40 @@ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; iommus = <&apps_smmu 0x480 0x00>, <&apps_smmu 0x481 0x00>; }; - crypto: crypto@1dfa000 { - compatible = "qcom,sa8775p-qce", "qcom,qce"; - reg = <0x0 0x01dfa000 0x0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x480 0x00>, - <&apps_smmu 0x481 0x00>; - interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "memory"; + ctcu@4001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x0 0x04001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; }; stm: stm@4002000 { @@ -2633,6 +2775,122 @@ }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x04046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc_etr: tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x04048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x0404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -2708,6 +2966,14 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; swao_rep_out1: endpoint { @@ -3815,10 +4081,10 @@ reg-names = "mdss"; /* same path used twice */ - interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, - <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", @@ -3848,7 +4114,7 @@ mdss0_mdp: display-controller@ae01000 { compatible = "qcom,sa8775p-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, @@ -4268,6 +4534,634 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 149>; wakeup-parent = <&pdc>; + + qup_i2c0_default: qup-i2c0-state { + pins = "gpio20", "gpio21"; + function = "qup0_se0"; + }; + + qup_i2c1_default: qup-i2c1-state { + pins = "gpio24", "gpio25"; + function = "qup0_se1"; + }; + + qup_i2c2_default: qup-i2c2-state { + pins = "gpio36", "gpio37"; + function = "qup0_se2"; + }; + + qup_i2c3_default: qup-i2c3-state { + pins = "gpio28", "gpio29"; + function = "qup0_se3"; + }; + + qup_i2c4_default: qup-i2c4-state { + pins = "gpio32", "gpio33"; + function = "qup0_se4"; + }; + + qup_i2c5_default: qup-i2c5-state { + pins = "gpio36", "gpio37"; + function = "qup0_se5"; + }; + + qup_i2c7_default: qup-i2c7-state { + pins = "gpio40", "gpio41"; + function = "qup1_se0"; + }; + + qup_i2c8_default: qup-i2c8-state { + pins = "gpio42", "gpio43"; + function = "qup1_se1"; + }; + + qup_i2c9_default: qup-i2c9-state { + pins = "gpio46", "gpio47"; + function = "qup1_se2"; + }; + + qup_i2c10_default: qup-i2c10-state { + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + }; + + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + }; + + qup_i2c12_default: qup-i2c12-state { + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + }; + + qup_i2c13_default: qup-i2c13-state { + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + }; + + qup_i2c14_default: qup-i2c14-state { + pins = "gpio80", "gpio81"; + function = "qup2_se0"; + }; + + qup_i2c15_default: qup-i2c15-state { + pins = "gpio84", "gpio85"; + function = "qup2_se1"; + }; + + qup_i2c16_default: qup-i2c16-state { + pins = "gpio86", "gpio87"; + function = "qup2_se2"; + }; + + qup_i2c17_default: qup-i2c17-state { + pins = "gpio91", "gpio92"; + function = "qup2_se3"; + }; + + qup_i2c18_default: qup-i2c18-state { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + }; + + qup_i2c19_default: qup-i2c19-state { + pins = "gpio99", "gpio100"; + function = "qup2_se5"; + }; + + qup_i2c20_default: qup-i2c20-state { + pins = "gpio97", "gpio98"; + function = "qup2_se6"; + }; + + qup_i2c21_default: qup-i2c21-state { + pins = "gpio13", "gpio14"; + function = "qup3_se0"; + }; + + qup_spi0_default: qup-spi0-state { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "qup0_se0"; + }; + + qup_spi1_default: qup-spi1-state { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + function = "qup0_se1"; + }; + + qup_spi2_default: qup-spi2-state { + pins = "gpio36", "gpio37", "gpio38", "gpio39"; + function = "qup0_se2"; + }; + + qup_spi3_default: qup-spi3-state { + pins = "gpio28", "gpio29", "gpio30", "gpio31"; + function = "qup0_se3"; + }; + + qup_spi4_default: qup-spi4-state { + pins = "gpio32", "gpio33", "gpio34", "gpio35"; + function = "qup0_se4"; + }; + + qup_spi5_default: qup-spi5-state { + pins = "gpio36", "gpio37", "gpio38", "gpio39"; + function = "qup0_se5"; + }; + + qup_spi7_default: qup-spi7-state { + pins = "gpio40", "gpio41", "gpio42", "gpio43"; + function = "qup1_se0"; + }; + + qup_spi8_default: qup-spi8-state { + pins = "gpio42", "gpio43", "gpio40", "gpio41"; + function = "qup1_se1"; + }; + + qup_spi9_default: qup-spi9-state { + pins = "gpio46", "gpio47", "gpio44", "gpio45"; + function = "qup1_se2"; + }; + + qup_spi10_default: qup-spi10-state { + pins = "gpio44", "gpio45", "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + qup_spi11_default: qup-spi11-state { + pins = "gpio48", "gpio49", "gpio50", "gpio51"; + function = "qup1_se4"; + }; + + qup_spi12_default: qup-spi12-state { + pins = "gpio52", "gpio53", "gpio54", "gpio55"; + function = "qup1_se5"; + }; + + qup_spi14_default: qup-spi14-state { + pins = "gpio80", "gpio81", "gpio82", "gpio83"; + function = "qup2_se0"; + }; + + qup_spi15_default: qup-spi15-state { + pins = "gpio84", "gpio85", "gpio99", "gpio100"; + function = "qup2_se1"; + }; + + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + }; + + qup_spi17_default: qup-spi17-state { + pins = "gpio91", "gpio92", "gpio93", "gpio94"; + function = "qup2_se3"; + }; + + qup_spi18_default: qup-spi18-state { + pins = "gpio95", "gpio96", "gpio97", "gpio98"; + function = "qup2_se4"; + }; + + qup_spi19_default: qup-spi19-state { + pins = "gpio99", "gpio100", "gpio84", "gpio85"; + function = "qup2_se5"; + }; + + qup_spi20_default: qup-spi20-state { + pins = "gpio97", "gpio98", "gpio95", "gpio96"; + function = "qup2_se6"; + }; + + qup_spi21_default: qup-spi21-state { + pins = "gpio13", "gpio14", "gpio15", "gpio16"; + function = "qup3_se0"; + }; + + qup_uart0_default: qup-uart0-state { + qup_uart0_cts: qup-uart0-cts-pins { + pins = "gpio20"; + function = "qup0_se0"; + }; + + qup_uart0_rts: qup-uart0-rts-pins { + pins = "gpio21"; + function = "qup0_se0"; + }; + + qup_uart0_tx: qup-uart0-tx-pins { + pins = "gpio22"; + function = "qup0_se0"; + }; + + qup_uart0_rx: qup-uart0-rx-pins { + pins = "gpio23"; + function = "qup0_se0"; + }; + }; + + qup_uart1_default: qup-uart1-state { + qup_uart1_cts: qup-uart1-cts-pins { + pins = "gpio24"; + function = "qup0_se1"; + }; + + qup_uart1_rts: qup-uart1-rts-pins { + pins = "gpio25"; + function = "qup0_se1"; + }; + + qup_uart1_tx: qup-uart1-tx-pins { + pins = "gpio26"; + function = "qup0_se1"; + }; + + qup_uart1_rx: qup-uart1-rx-pins { + pins = "gpio27"; + function = "qup0_se1"; + }; + }; + + qup_uart2_default: qup-uart2-state { + qup_uart2_cts: qup-uart2-cts-pins { + pins = "gpio36"; + function = "qup0_se2"; + }; + + qup_uart2_rts: qup-uart2-rts-pins { + pins = "gpio37"; + function = "qup0_se2"; + }; + + qup_uart2_tx: qup-uart2-tx-pins { + pins = "gpio38"; + function = "qup0_se2"; + }; + + qup_uart2_rx: qup-uart2-rx-pins { + pins = "gpio39"; + function = "qup0_se2"; + }; + }; + + qup_uart3_default: qup-uart3-state { + qup_uart3_cts: qup-uart3-cts-pins { + pins = "gpio28"; + function = "qup0_se3"; + }; + + qup_uart3_rts: qup-uart3-rts-pins { + pins = "gpio29"; + function = "qup0_se3"; + }; + + qup_uart3_tx: qup-uart3-tx-pins { + pins = "gpio30"; + function = "qup0_se3"; + }; + + qup_uart3_rx: qup-uart3-rx-pins { + pins = "gpio31"; + function = "qup0_se3"; + }; + }; + + qup_uart4_default: qup-uart4-state { + qup_uart4_cts: qup-uart4-cts-pins { + pins = "gpio32"; + function = "qup0_se4"; + }; + + qup_uart4_rts: qup-uart4-rts-pins { + pins = "gpio33"; + function = "qup0_se4"; + }; + + qup_uart4_tx: qup-uart4-tx-pins { + pins = "gpio34"; + function = "qup0_se4"; + }; + + qup_uart4_rx: qup-uart4-rx-pins { + pins = "gpio35"; + function = "qup0_se4"; + }; + }; + + qup_uart5_default: qup-uart5-state { + qup_uart5_cts: qup-uart5-cts-pins { + pins = "gpio36"; + function = "qup0_se5"; + }; + + qup_uart5_rts: qup-uart5-rts-pins { + pins = "gpio37"; + function = "qup0_se5"; + }; + + qup_uart5_tx: qup-uart5-tx-pins { + pins = "gpio38"; + function = "qup0_se5"; + }; + + qup_uart5_rx: qup-uart5-rx-pins { + pins = "gpio39"; + function = "qup0_se5"; + }; + }; + + qup_uart7_default: qup-uart7-state { + qup_uart7_cts: qup-uart7-cts-pins { + pins = "gpio40"; + function = "qup1_se0"; + }; + + qup_uart7_rts: qup-uart7-rts-pins { + pins = "gpio41"; + function = "qup1_se0"; + }; + + qup_uart7_tx: qup-uart7-tx-pins { + pins = "gpio42"; + function = "qup1_se0"; + }; + + qup_uart7_rx: qup-uart7-rx-pins { + pins = "gpio43"; + function = "qup1_se0"; + }; + }; + + qup_uart8_default: qup-uart8-state { + qup_uart8_cts: qup-uart8-cts-pins { + pins = "gpio42"; + function = "qup1_se1"; + }; + + qup_uart8_rts: qup-uart8-rts-pins { + pins = "gpio43"; + function = "qup1_se1"; + }; + + qup_uart8_tx: qup-uart8-tx-pins { + pins = "gpio40"; + function = "qup1_se1"; + }; + + qup_uart8_rx: qup-uart8-rx-pins { + pins = "gpio41"; + function = "qup1_se1"; + }; + }; + + qup_uart9_default: qup-uart9-state { + qup_uart9_cts: qup-uart9-cts-pins { + pins = "gpio46"; + function = "qup1_se2"; + }; + + qup_uart9_rts: qup-uart9-rts-pins { + pins = "gpio47"; + function = "qup1_se2"; + }; + + qup_uart9_tx: qup-uart9-tx-pins { + pins = "gpio44"; + function = "qup1_se2"; + }; + + qup_uart9_rx: qup-uart9-rx-pins { + pins = "gpio45"; + function = "qup1_se2"; + }; + }; + + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + qup_uart11_default: qup-uart11-state { + qup_uart11_cts: qup-uart11-cts-pins { + pins = "gpio48"; + function = "qup1_se4"; + }; + + qup_uart11_rts: qup-uart11-rts-pins { + pins = "gpio49"; + function = "qup1_se4"; + }; + + qup_uart11_tx: qup-uart11-tx-pins { + pins = "gpio50"; + function = "qup1_se4"; + }; + + qup_uart11_rx: qup-uart11-rx-pins { + pins = "gpio51"; + function = "qup1_se4"; + }; + }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins = "gpio52"; + function = "qup1_se5"; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins = "gpio53"; + function = "qup1_se5"; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins = "gpio54"; + function = "qup1_se5"; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins = "gpio55"; + function = "qup1_se5"; + }; + }; + + qup_uart14_default: qup-uart14-state { + qup_uart14_cts: qup-uart14-cts-pins { + pins = "gpio80"; + function = "qup2_se0"; + }; + + qup_uart14_rts: qup-uart14-rts-pins { + pins = "gpio81"; + function = "qup2_se0"; + }; + + qup_uart14_tx: qup-uart14-tx-pins { + pins = "gpio82"; + function = "qup2_se0"; + }; + + qup_uart14_rx: qup-uart14-rx-pins { + pins = "gpio83"; + function = "qup2_se0"; + }; + }; + + qup_uart15_default: qup-uart15-state { + qup_uart15_cts: qup-uart15-cts-pins { + pins = "gpio84"; + function = "qup2_se1"; + }; + + qup_uart15_rts: qup-uart15-rts-pins { + pins = "gpio85"; + function = "qup2_se1"; + }; + + qup_uart15_tx: qup-uart15-tx-pins { + pins = "gpio99"; + function = "qup2_se1"; + }; + + qup_uart15_rx: qup-uart15-rx-pins { + pins = "gpio100"; + function = "qup2_se1"; + }; + }; + + qup_uart16_default: qup-uart16-state { + qup_uart16_cts: qup-uart16-cts-pins { + pins = "gpio86"; + function = "qup2_se2"; + }; + + qup_uart16_rts: qup-uart16-rts-pins { + pins = "gpio87"; + function = "qup2_se2"; + }; + + qup_uart16_tx: qup-uart16-tx-pins { + pins = "gpio88"; + function = "qup2_se2"; + }; + + qup_uart16_rx: qup-uart16-rx-pins { + pins = "gpio89"; + function = "qup2_se2"; + }; + }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins = "gpio91"; + function = "qup2_se3"; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins = "gpio92"; + function = "qup2_se3"; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins = "gpio93"; + function = "qup2_se3"; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins = "gpio94"; + function = "qup2_se3"; + }; + }; + + qup_uart18_default: qup-uart18-state { + qup_uart18_cts: qup-uart18-cts-pins { + pins = "gpio95"; + function = "qup2_se4"; + }; + + qup_uart18_rts: qup-uart18-rts-pins { + pins = "gpio96"; + function = "qup2_se4"; + }; + + qup_uart18_tx: qup-uart18-tx-pins { + pins = "gpio97"; + function = "qup2_se4"; + }; + + qup_uart18_rx: qup-uart18-rx-pins { + pins = "gpio98"; + function = "qup2_se4"; + }; + }; + + qup_uart19_default: qup-uart19-state { + qup_uart19_cts: qup-uart19-cts-pins { + pins = "gpio99"; + function = "qup2_se5"; + }; + + qup_uart19_rts: qup-uart19-rts-pins { + pins = "gpio100"; + function = "qup2_se5"; + }; + + qup_uart19_tx: qup-uart19-tx-pins { + pins = "gpio84"; + function = "qup2_se5"; + }; + + qup_uart19_rx: qup-uart19-rx-pins { + pins = "gpio85"; + function = "qup2_se5"; + }; + }; + + qup_uart20_default: qup-uart20-state { + qup_uart20_cts: qup-uart20-cts-pins { + pins = "gpio97"; + function = "qup2_se6"; + }; + + qup_uart20_rts: qup-uart20-rts-pins { + pins = "gpio98"; + function = "qup2_se6"; + }; + + qup_uart20_tx: qup-uart20-tx-pins { + pins = "gpio95"; + function = "qup2_se6"; + }; + + qup_uart20_rx: qup-uart20-rx-pins { + pins = "gpio96"; + function = "qup2_se6"; + }; + }; + + qup_uart21_default: qup-uart21-state { + qup_uart21_cts: qup-uart21-cts-pins { + pins = "gpio13"; + function = "qup3_se0"; + }; + + qup_uart21_rts: qup-uart21-rts-pins { + pins = "gpio14"; + function = "qup3_se0"; + }; + + qup_uart21_tx: qup-uart21-tx-pins { + pins = "gpio15"; + function = "qup3_se0"; + }; + + qup_uart21_rx: qup-uart21-rx-pins { + pins = "gpio16"; + function = "qup3_se0"; + }; + }; }; sram: sram@146d8000 { @@ -4590,6 +5484,7 @@ <WAKE_TCS 3>, <CONTROL_TCS 0>; label = "apps_rsc"; + power-domains = <&system_pd>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; @@ -4660,6 +5555,10 @@ <0x0 0x18593000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; @@ -4903,15 +5802,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x2141 0x04a0>, - <&apps_smmu 0x2161 0x04a0>, - <&apps_smmu 0x2181 0x0400>, - <&apps_smmu 0x21c1 0x04a0>, - <&apps_smmu 0x21e1 0x04a0>, - <&apps_smmu 0x2541 0x04a0>, - <&apps_smmu 0x2561 0x04a0>, - <&apps_smmu 0x2581 0x0400>, - <&apps_smmu 0x25c1 0x04a0>, - <&apps_smmu 0x25e1 0x04a0>; + <&apps_smmu 0x2181 0x0400>; dma-coherent; }; @@ -4919,15 +5810,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x2142 0x04a0>, - <&apps_smmu 0x2162 0x04a0>, - <&apps_smmu 0x2182 0x0400>, - <&apps_smmu 0x21c2 0x04a0>, - <&apps_smmu 0x21e2 0x04a0>, - <&apps_smmu 0x2542 0x04a0>, - <&apps_smmu 0x2562 0x04a0>, - <&apps_smmu 0x2582 0x0400>, - <&apps_smmu 0x25c2 0x04a0>, - <&apps_smmu 0x25e2 0x04a0>; + <&apps_smmu 0x2182 0x0400>; dma-coherent; }; @@ -4935,15 +5818,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x2143 0x04a0>, - <&apps_smmu 0x2163 0x04a0>, - <&apps_smmu 0x2183 0x0400>, - <&apps_smmu 0x21c3 0x04a0>, - <&apps_smmu 0x21e3 0x04a0>, - <&apps_smmu 0x2543 0x04a0>, - <&apps_smmu 0x2563 0x04a0>, - <&apps_smmu 0x2583 0x0400>, - <&apps_smmu 0x25c3 0x04a0>, - <&apps_smmu 0x25e3 0x04a0>; + <&apps_smmu 0x2183 0x0400>; dma-coherent; }; @@ -4951,15 +5826,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x2144 0x04a0>, - <&apps_smmu 0x2164 0x04a0>, - <&apps_smmu 0x2184 0x0400>, - <&apps_smmu 0x21c4 0x04a0>, - <&apps_smmu 0x21e4 0x04a0>, - <&apps_smmu 0x2544 0x04a0>, - <&apps_smmu 0x2564 0x04a0>, - <&apps_smmu 0x2584 0x0400>, - <&apps_smmu 0x25c4 0x04a0>, - <&apps_smmu 0x25e4 0x04a0>; + <&apps_smmu 0x2184 0x0400>; dma-coherent; }; @@ -4967,15 +5834,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x2145 0x04a0>, - <&apps_smmu 0x2165 0x04a0>, - <&apps_smmu 0x2185 0x0400>, - <&apps_smmu 0x21c5 0x04a0>, - <&apps_smmu 0x21e5 0x04a0>, - <&apps_smmu 0x2545 0x04a0>, - <&apps_smmu 0x2565 0x04a0>, - <&apps_smmu 0x2585 0x0400>, - <&apps_smmu 0x25c5 0x04a0>, - <&apps_smmu 0x25e5 0x04a0>; + <&apps_smmu 0x2185 0x0400>; dma-coherent; }; @@ -4983,15 +5842,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x2146 0x04a0>, - <&apps_smmu 0x2166 0x04a0>, - <&apps_smmu 0x2186 0x0400>, - <&apps_smmu 0x21c6 0x04a0>, - <&apps_smmu 0x21e6 0x04a0>, - <&apps_smmu 0x2546 0x04a0>, - <&apps_smmu 0x2566 0x04a0>, - <&apps_smmu 0x2586 0x0400>, - <&apps_smmu 0x25c6 0x04a0>, - <&apps_smmu 0x25e6 0x04a0>; + <&apps_smmu 0x2186 0x0400>; dma-coherent; }; @@ -4999,15 +5850,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x2147 0x04a0>, - <&apps_smmu 0x2167 0x04a0>, - <&apps_smmu 0x2187 0x0400>, - <&apps_smmu 0x21c7 0x04a0>, - <&apps_smmu 0x21e7 0x04a0>, - <&apps_smmu 0x2547 0x04a0>, - <&apps_smmu 0x2567 0x04a0>, - <&apps_smmu 0x2587 0x0400>, - <&apps_smmu 0x25c7 0x04a0>, - <&apps_smmu 0x25e7 0x04a0>; + <&apps_smmu 0x2187 0x0400>; dma-coherent; }; @@ -5015,15 +5858,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x2148 0x04a0>, - <&apps_smmu 0x2168 0x04a0>, - <&apps_smmu 0x2188 0x0400>, - <&apps_smmu 0x21c8 0x04a0>, - <&apps_smmu 0x21e8 0x04a0>, - <&apps_smmu 0x2548 0x04a0>, - <&apps_smmu 0x2568 0x04a0>, - <&apps_smmu 0x2588 0x0400>, - <&apps_smmu 0x25c8 0x04a0>, - <&apps_smmu 0x25e8 0x04a0>; + <&apps_smmu 0x2188 0x0400>; dma-coherent; }; @@ -5031,31 +5866,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <9>; iommus = <&apps_smmu 0x2149 0x04a0>, - <&apps_smmu 0x2169 0x04a0>, - <&apps_smmu 0x2189 0x0400>, - <&apps_smmu 0x21c9 0x04a0>, - <&apps_smmu 0x21e9 0x04a0>, - <&apps_smmu 0x2549 0x04a0>, - <&apps_smmu 0x2569 0x04a0>, - <&apps_smmu 0x2589 0x0400>, - <&apps_smmu 0x25c9 0x04a0>, - <&apps_smmu 0x25e9 0x04a0>; - dma-coherent; - }; - - compute-cb@10 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <10>; - iommus = <&apps_smmu 0x214a 0x04a0>, - <&apps_smmu 0x216a 0x04a0>, - <&apps_smmu 0x218a 0x0400>, - <&apps_smmu 0x21ca 0x04a0>, - <&apps_smmu 0x21ea 0x04a0>, - <&apps_smmu 0x254a 0x04a0>, - <&apps_smmu 0x256a 0x04a0>, - <&apps_smmu 0x258a 0x0400>, - <&apps_smmu 0x25ca 0x04a0>, - <&apps_smmu 0x25ea 0x04a0>; + <&apps_smmu 0x2189 0x0400>; dma-coherent; }; @@ -5063,15 +5874,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0x214b 0x04a0>, - <&apps_smmu 0x216b 0x04a0>, - <&apps_smmu 0x218b 0x0400>, - <&apps_smmu 0x21cb 0x04a0>, - <&apps_smmu 0x21eb 0x04a0>, - <&apps_smmu 0x254b 0x04a0>, - <&apps_smmu 0x256b 0x04a0>, - <&apps_smmu 0x258b 0x0400>, - <&apps_smmu 0x25cb 0x04a0>, - <&apps_smmu 0x25eb 0x04a0>; + <&apps_smmu 0x218b 0x0400>; dma-coherent; }; }; @@ -5131,15 +5934,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <1>; iommus = <&apps_smmu 0x2941 0x04a0>, - <&apps_smmu 0x2961 0x04a0>, - <&apps_smmu 0x2981 0x0400>, - <&apps_smmu 0x29c1 0x04a0>, - <&apps_smmu 0x29e1 0x04a0>, - <&apps_smmu 0x2d41 0x04a0>, - <&apps_smmu 0x2d61 0x04a0>, - <&apps_smmu 0x2d81 0x0400>, - <&apps_smmu 0x2dc1 0x04a0>, - <&apps_smmu 0x2de1 0x04a0>; + <&apps_smmu 0x2981 0x0400>; dma-coherent; }; @@ -5147,15 +5942,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <2>; iommus = <&apps_smmu 0x2942 0x04a0>, - <&apps_smmu 0x2962 0x04a0>, - <&apps_smmu 0x2982 0x0400>, - <&apps_smmu 0x29c2 0x04a0>, - <&apps_smmu 0x29e2 0x04a0>, - <&apps_smmu 0x2d42 0x04a0>, - <&apps_smmu 0x2d62 0x04a0>, - <&apps_smmu 0x2d82 0x0400>, - <&apps_smmu 0x2dc2 0x04a0>, - <&apps_smmu 0x2de2 0x04a0>; + <&apps_smmu 0x2982 0x0400>; dma-coherent; }; @@ -5163,15 +5950,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <3>; iommus = <&apps_smmu 0x2943 0x04a0>, - <&apps_smmu 0x2963 0x04a0>, - <&apps_smmu 0x2983 0x0400>, - <&apps_smmu 0x29c3 0x04a0>, - <&apps_smmu 0x29e3 0x04a0>, - <&apps_smmu 0x2d43 0x04a0>, - <&apps_smmu 0x2d63 0x04a0>, - <&apps_smmu 0x2d83 0x0400>, - <&apps_smmu 0x2dc3 0x04a0>, - <&apps_smmu 0x2de3 0x04a0>; + <&apps_smmu 0x2983 0x0400>; dma-coherent; }; @@ -5179,15 +5958,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <4>; iommus = <&apps_smmu 0x2944 0x04a0>, - <&apps_smmu 0x2964 0x04a0>, - <&apps_smmu 0x2984 0x0400>, - <&apps_smmu 0x29c4 0x04a0>, - <&apps_smmu 0x29e4 0x04a0>, - <&apps_smmu 0x2d44 0x04a0>, - <&apps_smmu 0x2d64 0x04a0>, - <&apps_smmu 0x2d84 0x0400>, - <&apps_smmu 0x2dc4 0x04a0>, - <&apps_smmu 0x2de4 0x04a0>; + <&apps_smmu 0x2984 0x0400>; dma-coherent; }; @@ -5195,15 +5966,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <5>; iommus = <&apps_smmu 0x2945 0x04a0>, - <&apps_smmu 0x2965 0x04a0>, - <&apps_smmu 0x2985 0x0400>, - <&apps_smmu 0x29c5 0x04a0>, - <&apps_smmu 0x29e5 0x04a0>, - <&apps_smmu 0x2d45 0x04a0>, - <&apps_smmu 0x2d65 0x04a0>, - <&apps_smmu 0x2d85 0x0400>, - <&apps_smmu 0x2dc5 0x04a0>, - <&apps_smmu 0x2de5 0x04a0>; + <&apps_smmu 0x2985 0x0400>; dma-coherent; }; @@ -5211,15 +5974,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <6>; iommus = <&apps_smmu 0x2946 0x04a0>, - <&apps_smmu 0x2966 0x04a0>, - <&apps_smmu 0x2986 0x0400>, - <&apps_smmu 0x29c6 0x04a0>, - <&apps_smmu 0x29e6 0x04a0>, - <&apps_smmu 0x2d46 0x04a0>, - <&apps_smmu 0x2d66 0x04a0>, - <&apps_smmu 0x2d86 0x0400>, - <&apps_smmu 0x2dc6 0x04a0>, - <&apps_smmu 0x2de6 0x04a0>; + <&apps_smmu 0x2986 0x0400>; dma-coherent; }; @@ -5227,15 +5982,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <7>; iommus = <&apps_smmu 0x2947 0x04a0>, - <&apps_smmu 0x2967 0x04a0>, - <&apps_smmu 0x2987 0x0400>, - <&apps_smmu 0x29c7 0x04a0>, - <&apps_smmu 0x29e7 0x04a0>, - <&apps_smmu 0x2d47 0x04a0>, - <&apps_smmu 0x2d67 0x04a0>, - <&apps_smmu 0x2d87 0x0400>, - <&apps_smmu 0x2dc7 0x04a0>, - <&apps_smmu 0x2de7 0x04a0>; + <&apps_smmu 0x2987 0x0400>; dma-coherent; }; @@ -5243,15 +5990,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <8>; iommus = <&apps_smmu 0x2948 0x04a0>, - <&apps_smmu 0x2968 0x04a0>, - <&apps_smmu 0x2988 0x0400>, - <&apps_smmu 0x29c8 0x04a0>, - <&apps_smmu 0x29e8 0x04a0>, - <&apps_smmu 0x2d48 0x04a0>, - <&apps_smmu 0x2d68 0x04a0>, - <&apps_smmu 0x2d88 0x0400>, - <&apps_smmu 0x2dc8 0x04a0>, - <&apps_smmu 0x2de8 0x04a0>; + <&apps_smmu 0x2988 0x0400>; dma-coherent; }; @@ -5259,15 +5998,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <9>; iommus = <&apps_smmu 0x2949 0x04a0>, - <&apps_smmu 0x2969 0x04a0>, - <&apps_smmu 0x2989 0x0400>, - <&apps_smmu 0x29c9 0x04a0>, - <&apps_smmu 0x29e9 0x04a0>, - <&apps_smmu 0x2d49 0x04a0>, - <&apps_smmu 0x2d69 0x04a0>, - <&apps_smmu 0x2d89 0x0400>, - <&apps_smmu 0x2dc9 0x04a0>, - <&apps_smmu 0x2de9 0x04a0>; + <&apps_smmu 0x2989 0x0400>; dma-coherent; }; @@ -5275,15 +6006,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <10>; iommus = <&apps_smmu 0x294a 0x04a0>, - <&apps_smmu 0x296a 0x04a0>, - <&apps_smmu 0x298a 0x0400>, - <&apps_smmu 0x29ca 0x04a0>, - <&apps_smmu 0x29ea 0x04a0>, - <&apps_smmu 0x2d4a 0x04a0>, - <&apps_smmu 0x2d6a 0x04a0>, - <&apps_smmu 0x2d8a 0x0400>, - <&apps_smmu 0x2dca 0x04a0>, - <&apps_smmu 0x2dea 0x04a0>; + <&apps_smmu 0x298a 0x0400>; dma-coherent; }; @@ -5291,15 +6014,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <11>; iommus = <&apps_smmu 0x294b 0x04a0>, - <&apps_smmu 0x296b 0x04a0>, - <&apps_smmu 0x298b 0x0400>, - <&apps_smmu 0x29cb 0x04a0>, - <&apps_smmu 0x29eb 0x04a0>, - <&apps_smmu 0x2d4b 0x04a0>, - <&apps_smmu 0x2d6b 0x04a0>, - <&apps_smmu 0x2d8b 0x0400>, - <&apps_smmu 0x2dcb 0x04a0>, - <&apps_smmu 0x2deb 0x04a0>; + <&apps_smmu 0x298b 0x0400>; dma-coherent; }; @@ -5307,15 +6022,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <12>; iommus = <&apps_smmu 0x294c 0x04a0>, - <&apps_smmu 0x296c 0x04a0>, - <&apps_smmu 0x298c 0x0400>, - <&apps_smmu 0x29cc 0x04a0>, - <&apps_smmu 0x29ec 0x04a0>, - <&apps_smmu 0x2d4c 0x04a0>, - <&apps_smmu 0x2d6c 0x04a0>, - <&apps_smmu 0x2d8c 0x0400>, - <&apps_smmu 0x2dcc 0x04a0>, - <&apps_smmu 0x2dec 0x04a0>; + <&apps_smmu 0x298c 0x0400>; dma-coherent; }; @@ -5323,15 +6030,7 @@ compatible = "qcom,fastrpc-compute-cb"; reg = <13>; iommus = <&apps_smmu 0x294d 0x04a0>, - <&apps_smmu 0x296d 0x04a0>, - <&apps_smmu 0x298d 0x0400>, - <&apps_smmu 0x29Cd 0x04a0>, - <&apps_smmu 0x29ed 0x04a0>, - <&apps_smmu 0x2d4d 0x04a0>, - <&apps_smmu 0x2d6d 0x04a0>, - <&apps_smmu 0x2d8d 0x0400>, - <&apps_smmu 0x2dcd 0x04a0>, - <&apps_smmu 0x2ded 0x04a0>; + <&apps_smmu 0x298d 0x0400>; dma-coherent; }; }; |