1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/qcom/sm4250.dtsi
new file mode 100644
index 000000000000..cd8c8e59976e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
+ */
+
+#include "sm6115.dtsi"
+
+&cpu0 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu1 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu2 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu3 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu4 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu5 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu6 {
+	compatible = "qcom,kryo240";
+};
+
+&cpu7 {
+	compatible = "qcom,kryo240";
+};
+
+&lpass_tlmm {
+	compatible = "qcom,sm4250-lpass-lpi-pinctrl";
+	gpio-ranges = <&lpass_tlmm 0 0 27>;
+
+	lpi_i2s2_active: lpi-i2s2-active-state {
+		sck-pins {
+			pins = "gpio10";
+			function = "i2s2_clk";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		ws-pins {
+			pins = "gpio11";
+			function = "i2s2_ws";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		data-pins {
+			pins = "gpio12";
+			function = "i2s2_data";
+			bias-disable;
+			drive-strength = <8>;
+			output-high;
+		};
+
+		ext-mclk1-pins {
+			pins = "gpio18";
+			function = "ext_mclk1_a";
+			bias-disable;
+			drive-strength = <16>;
+			output-high;
+		};
+	};
+};