diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8650.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8650.dtsi | 4046 |
1 files changed, 3063 insertions, 983 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index eb117866e59f..495ea9bfd008 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3,16 +3,20 @@ * Copyright (c) 2023, Linaro Limited */ +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8650-camcc.h> #include <dt-bindings/clock/qcom,sm8650-dispcc.h> #include <dt-bindings/clock/qcom,sm8650-gcc.h> #include <dt-bindings/clock/qcom,sm8650-gpucc.h> #include <dt-bindings/clock/qcom,sm8650-tcsr.h> +#include <dt-bindings/clock/qcom,sm8650-videocc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> @@ -60,43 +64,47 @@ clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { #address-cells = <2>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a520"; reg = <0 0>; clocks = <&cpufreq_hw 0>; - power-domains = <&CPU_PD0>; + power-domains = <&cpu_pd0>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; - L3_0: l3-cache { + l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; @@ -104,213 +112,283 @@ }; }; - CPU1: cpu@100 { + cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a520"; reg = <0 0x100>; clocks = <&cpufreq_hw 0>; - power-domains = <&CPU_PD1>; + power-domains = <&cpu_pd1>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_0>; + next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; }; - CPU2: cpu@200 { + cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0 0x200>; clocks = <&cpufreq_hw 3>; - power-domains = <&CPU_PD2>; + power-domains = <&cpu_pd2>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_200>; + next-level-cache = <&l2_200>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; + operating-points-v2 = <&cpu2_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; - L2_200: l2-cache { + l2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU3: cpu@300 { + cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0 0x300>; clocks = <&cpufreq_hw 3>; - power-domains = <&CPU_PD3>; + power-domains = <&cpu_pd3>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_200>; + next-level-cache = <&l2_300>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; + operating-points-v2 = <&cpu2_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; - CPU4: cpu@400 { + cpu4: cpu@400 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0 0x400>; clocks = <&cpufreq_hw 3>; - power-domains = <&CPU_PD4>; + power-domains = <&cpu_pd4>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_400>; + next-level-cache = <&l2_400>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; + operating-points-v2 = <&cpu2_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; - L2_400: l2-cache { + l2_400: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU5: cpu@500 { + cpu5: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0 0x500>; clocks = <&cpufreq_hw 1>; - power-domains = <&CPU_PD5>; + power-domains = <&cpu_pd5>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_500>; + next-level-cache = <&l2_500>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu5_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; - L2_500: l2-cache { + l2_500: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU6: cpu@600 { + cpu6: cpu@600 { device_type = "cpu"; compatible = "arm,cortex-a720"; reg = <0 0x600>; clocks = <&cpufreq_hw 1>; - power-domains = <&CPU_PD6>; + power-domains = <&cpu_pd6>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_600>; + next-level-cache = <&l2_600>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu5_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; - L2_600: l2-cache { + l2_600: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; - CPU7: cpu@700 { + cpu7: cpu@700 { device_type = "cpu"; compatible = "arm,cortex-x4"; reg = <0 0x700>; clocks = <&cpufreq_hw 2>; - power-domains = <&CPU_PD7>; + power-domains = <&cpu_pd7>; power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&L2_700>; + next-level-cache = <&l2_700>; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <588>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu7_opp_table>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells = <2>; - L2_700: l2-cache { + l2_700: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; - next-level-cache = <&L3_0>; + next-level-cache = <&l3_0>; }; }; cpu-map { cluster0 { core0 { - cpu = <&CPU0>; + cpu = <&cpu0>; }; core1 { - cpu = <&CPU1>; + cpu = <&cpu1>; }; core2 { - cpu = <&CPU2>; + cpu = <&cpu2>; }; core3 { - cpu = <&CPU3>; + cpu = <&cpu3>; }; core4 { - cpu = <&CPU4>; + cpu = <&cpu4>; }; core5 { - cpu = <&CPU5>; + cpu = <&cpu5>; }; core6 { - cpu = <&CPU6>; + cpu = <&cpu6>; }; core7 { - cpu = <&CPU7>; + cpu = <&cpu7>; }; }; }; @@ -318,7 +396,7 @@ idle-states { entry-method = "psci"; - SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { + silver_cpu_sleep_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -328,7 +406,7 @@ local-timer-stop; }; - GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { + gold_cpu_sleep_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -338,7 +416,7 @@ local-timer-stop; }; - GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { compatible = "arm,idle-state"; idle-state-name = "gold-plus-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -350,7 +428,7 @@ }; domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + cluster_sleep_0: cluster-sleep-0 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <750>; @@ -358,7 +436,7 @@ min-residency-us = <9144>; }; - CLUSTER_SLEEP_1: cluster-sleep-1 { + cluster_sleep_1: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <2800>; @@ -368,9 +446,203 @@ }; }; + ete-0 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu0>; + + out-ports { + port { + ete0_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete0>; + }; + }; + }; + }; + + ete-1 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu1>; + + out-ports { + port { + ete1_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete1>; + }; + }; + }; + }; + + ete-2 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu2>; + + out-ports { + port { + ete2_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete2>; + }; + }; + }; + }; + + ete-3 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu3>; + + out-ports { + port { + ete3_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete3>; + }; + }; + }; + }; + + ete-4 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu4>; + + out-ports { + port { + ete4_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete4>; + }; + }; + }; + }; + + ete-5 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu5>; + + out-ports { + port { + ete5_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete5>; + }; + }; + }; + }; + + ete-6 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu6>; + + out-ports { + port { + ete6_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete6>; + }; + }; + }; + }; + + ete-7 { + compatible = "arm,embedded-trace-extension"; + + cpu = <&cpu7>; + + out-ports { + port { + ete7_out_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_in_ete7>; + }; + }; + }; + }; + + funnel-ete { + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_ete_in_ete0: endpoint { + remote-endpoint = <&ete0_out_funnel_ete>; + }; + }; + + port@1 { + reg = <1>; + + funnel_ete_in_ete1: endpoint { + remote-endpoint = <&ete1_out_funnel_ete>; + }; + }; + + port@2 { + reg = <2>; + + funnel_ete_in_ete2: endpoint { + remote-endpoint = <&ete2_out_funnel_ete>; + }; + }; + + port@3 { + reg = <3>; + + funnel_ete_in_ete3: endpoint { + remote-endpoint = <&ete3_out_funnel_ete>; + }; + }; + + port@4 { + reg = <4>; + + funnel_ete_in_ete4: endpoint { + remote-endpoint = <&ete4_out_funnel_ete>; + }; + }; + + port@5 { + reg = <5>; + + funnel_ete_in_ete5: endpoint { + remote-endpoint = <&ete5_out_funnel_ete>; + }; + }; + + port@6 { + reg = <6>; + + funnel_ete_in_ete6: endpoint { + remote-endpoint = <&ete6_out_funnel_ete>; + }; + }; + + port@7 { + reg = <7>; + + funnel_ete_in_ete7: endpoint { + remote-endpoint = <&ete7_out_funnel_ete>; + }; + }; + }; + + out-ports { + port { + funnel_ete_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_funnel_ete>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm8650", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; @@ -388,73 +660,999 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_128mhz: opp-table-qup128mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_240mhz: opp-table-qup240mhz { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-364800000 { + opp-hz = /bits/ 64 <364800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; + }; + + opp-556800000 { + opp-hz = /bits/ 64 <556800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; + }; + + opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; + }; + + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; + }; + + opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; + }; + + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; + }; + + opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>; + }; + }; + + cpu2_opp_table: opp-table-cpu2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2572800000 { + opp-hz = /bits/ 64 <2572800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2630400000 { + opp-hz = /bits/ 64 <2630400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2764800000 { + opp-hz = /bits/ 64 <2764800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3014400000 { + opp-hz = /bits/ 64 <3014400000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3072000000 { + opp-hz = /bits/ 64 <3072000000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3148800000 { + opp-hz = /bits/ 64 <3148800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + }; + + cpu5_opp_table: opp-table-cpu5 { + compatible = "operating-points-v2"; + opp-shared; + + opp-460800000 { + opp-hz = /bits/ 64 <460800000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1920000000 { + opp-hz = /bits/ 64 <1920000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2572800000 { + opp-hz = /bits/ 64 <2572800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2630400000 { + opp-hz = /bits/ 64 <2630400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2764800000 { + opp-hz = /bits/ 64 <2764800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; + }; + + opp-2841600000 { + opp-hz = /bits/ 64 <2841600000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2956800000 { + opp-hz = /bits/ 64 <2956800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3014400000 { + opp-hz = /bits/ 64 <3014400000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3072000000 { + opp-hz = /bits/ 64 <3072000000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3148800000 { + opp-hz = /bits/ 64 <3148800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible = "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; + }; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1075200000 { + opp-hz = /bits/ 64 <1075200000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; + }; + + opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2246400000 { + opp-hz = /bits/ 64 <2246400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; + }; + + opp-2630400000 { + opp-hz = /bits/ 64 <2630400000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2688000000 { + opp-hz = /bits/ 64 <2688000000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; + }; + + opp-2745600000 { + opp-hz = /bits/ 64 <2745600000>; + opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; + }; + + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2880000000 { + opp-hz = /bits/ 64 <2880000000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2937600000 { + opp-hz = /bits/ 64 <2937600000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3052800000 { + opp-hz = /bits/ 64 <3052800000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; + }; + + opp-3187200000 { + opp-hz = /bits/ 64 <3187200000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + + opp-3302400000 { + opp-hz = /bits/ 64 <3302400000>; + opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; + }; + }; + + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; + }; + + pmu-x4 { + compatible = "arm,cortex-x4-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&SILVER_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>; }; - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&SILVER_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>; }; - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&SILVER_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>; }; - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&GOLD_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>; }; - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&GOLD_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>; }; - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&GOLD_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>; }; - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&GOLD_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>; }; - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_plus_cpu_sleep_0>; }; - CLUSTER_PD: power-domain-cluster { + cluster_pd: power-domain-cluster { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>, - <&CLUSTER_SLEEP_1>; + domain-idle-states = <&cluster_sleep_0>, + <&cluster_sleep_1>; }; }; @@ -485,9 +1683,9 @@ no-map; }; - /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { - reg = <0 0x81c80000 0 0x74000>; + reg = <0 0x81c80000 0 0x75000>; no-map; }; @@ -758,8 +1956,8 @@ <&bi_tcxo_ao_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -774,7 +1972,7 @@ compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; reg = <0 0x00406000 0 0x1000>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-controller; #interrupt-cells = <3>; @@ -785,18 +1983,18 @@ compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00800000 0 0x60000>; - interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; dma-channels = <12>; dma-channel-mask = <0x3f>; @@ -832,21 +2030,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00880000 0 0x4000>; - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -865,21 +2067,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00880000 0 0x4000>; - interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -898,21 +2104,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; - interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -931,21 +2141,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00884000 0 0x4000>; - interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -964,21 +2178,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00888000 0 0x4000>; - interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -997,21 +2215,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00888000 0 0x4000>; - interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -1030,21 +2252,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -1063,21 +2289,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x0088c000 0 0x4000>; - interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -1096,21 +2326,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; - interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -1129,21 +2363,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00890000 0 0x4000>; - interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -1162,21 +2400,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; - interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -1195,21 +2437,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00894000 0 0x4000>; - interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -1228,18 +2474,22 @@ compatible = "qcom,geni-uart"; reg = <0 0x00898000 0 0x4000>; - interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_128mhz>; + pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; pinctrl-names = "default"; @@ -1250,18 +2500,22 @@ compatible = "qcom,geni-debug-uart"; reg = <0 0x0089c000 0 0x4000>; - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + pinctrl-0 = <&qup_uart15_default>; pinctrl-names = "default"; @@ -1286,7 +2540,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00980000 0 0x4000>; - interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1295,11 +2549,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c0_data_clk>; pinctrl-names = "default"; @@ -1313,7 +2571,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00984000 0 0x4000>; - interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1322,11 +2580,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c1_data_clk>; pinctrl-names = "default"; @@ -1340,7 +2602,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00988000 0 0x4000>; - interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1349,11 +2611,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c2_data_clk>; pinctrl-names = "default"; @@ -1367,7 +2633,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0098c000 0 0x4000>; - interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1376,11 +2642,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c3_data_clk>; pinctrl-names = "default"; @@ -1394,7 +2664,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00990000 0 0x4000>; - interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1403,11 +2673,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c4_data_clk>; pinctrl-names = "default"; @@ -1421,7 +2695,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00994000 0 0x4000>; - interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1430,11 +2704,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c5_data_clk>; pinctrl-names = "default"; @@ -1448,7 +2726,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x00998000 0 0x4000>; - interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1457,11 +2735,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c6_data_clk>; pinctrl-names = "default"; @@ -1475,7 +2757,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x0099c000 0 0x4000>; - interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1484,11 +2766,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c7_data_clk>; pinctrl-names = "default"; @@ -1502,7 +2788,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a0000 0 0x4000>; - interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1511,11 +2797,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c8_data_clk>; pinctrl-names = "default"; @@ -1529,7 +2819,7 @@ compatible = "qcom,geni-i2c-master-hub"; reg = <0 0x009a4000 0 0x4000>; - interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, <&gcc GCC_QUPV3_I2C_CORE_CLK>; @@ -1538,11 +2828,15 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + + required-opps = <&rpmhpd_opp_low_svs>; + pinctrl-0 = <&hub_i2c9_data_clk>; pinctrl-names = "default"; @@ -1557,18 +2851,18 @@ compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; dma-channels = <12>; dma-channel-mask = <0xc>; @@ -1607,21 +2901,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -1640,21 +2938,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; - interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -1673,21 +2975,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -1706,21 +3012,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -1739,21 +3049,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_240mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -1772,21 +3086,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; - interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_240mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -1805,21 +3123,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -1838,21 +3160,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -1871,21 +3197,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -1904,21 +3234,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; - interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -1937,21 +3271,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -1970,21 +3308,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -2003,21 +3345,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; - interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", @@ -2036,21 +3382,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; - interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", @@ -2069,21 +3419,25 @@ compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", @@ -2102,21 +3456,25 @@ compatible = "qcom,geni-spi"; reg = <0 0x00a9c000 0 0x4000>; - interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names = "tx", @@ -2208,7 +3566,7 @@ reg = <0 0x010c3000 0 0x1000>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; reg = <0 0x01c00000 0 0x3000>, @@ -2218,14 +3576,15 @@ <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "msi0", "msi1", "msi2", @@ -2233,7 +3592,8 @@ "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2257,20 +3617,22 @@ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; power-domains = <&gcc PCIE_0_GDSC>; + operating-points-v2 = <&pcie0_opp_table>; + iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -2293,6 +3655,55 @@ dma-coherent; status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + }; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2326,7 +3737,7 @@ status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; reg = <0 0x01c08000 0 0x3000>, @@ -2340,14 +3751,15 @@ "atu", "config"; - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "msi0", "msi1", "msi2", @@ -2355,7 +3767,8 @@ "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2384,20 +3797,22 @@ interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; power-domains = <&gcc PCIE_1_GDSC>; + operating-points-v2 = <&pcie1_opp_table>; + iommu-map = <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -2420,6 +3835,62 @@ <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2447,7 +3918,7 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; + #clock-cells = <1>; clock-output-names = "pcie1_pipe_clk"; #phy-cells = <0>; @@ -2459,7 +3930,7 @@ compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x28000>; - interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; @@ -2467,6 +3938,8 @@ <&apps_smmu 0x481 0>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; }; @@ -2507,11 +3980,11 @@ status = "disabled"; }; - ufs_mem_hc: ufs@1d84000 { + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0 0x01d84000 0 0x3000>; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -2529,28 +4002,22 @@ "tx_lane0_sync_clk", "rx_lane0_sync_clk", "rx_lane1_sync_clk"; - freq-table-hz = <100000000 403000000>, - <0 0>, - <0 0>, - <100000000 403000000>, - <100000000 403000000>, - <0 0>, - <0 0>, - <0 0>; resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "ufs-ddr", "cpu-ufs"; power-domains = <&gcc UFS_PHY_GDSC>; required-opps = <&rpmhpd_opp_nom>; + operating-points-v2 = <&ufs_opp_table>; + iommus = <&apps_smmu 0x60 0>; lanes-per-direction = <2>; @@ -2562,12 +4029,52 @@ #reset-cells = <1>; status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; ice: crypto@1d88000 { compatible = "qcom,sm8650-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; @@ -2589,6 +4096,159 @@ #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; + opp-peak-kBps = <2136718>; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136718>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; + opp-peak-kBps = <6074218>; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <8171875>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + opp-peak-kBps = <8171875>; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <8171875>; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + opp-peak-kBps = <10687500>; + }; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <12449218>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <12449218>; + }; + + opp-770000000 { + opp-hz = /bits/ 64 <770000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <12449218>; + }; + + opp-834000000 { + opp-hz = /bits/ 64 <834000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <14398437>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2602,6 +4262,50 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; @@ -2614,8 +4318,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", @@ -2626,8 +4330,10 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "memory", "config"; @@ -2643,9 +4349,9 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8650-mpss-pas"; - reg = <0 0x04080000 0 0x4040>; + reg = <0x0 0x04080000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2694,6 +4400,154 @@ }; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,sm8650-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,fastrpc"; + + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + label = "adsp"; + + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + lpass_wsa2macro: codec@6aa0000 { compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; reg = <0 0x06aa0000 0 0x1000>; @@ -2714,7 +4568,7 @@ swr3: soundwire@6ab0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ab0000 0 0x10000>; - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lpass_wsa2macro>; clock-names = "iface"; label = "WSA2"; @@ -2761,7 +4615,7 @@ swr1: soundwire@6ad0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ad0000 0 0x10000>; - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lpass_rxmacro>; clock-names = "iface"; label = "RX"; @@ -2825,7 +4679,7 @@ swr0: soundwire@6b10000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06b10000 0 0x10000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lpass_wsamacro>; clock-names = "iface"; label = "WSA"; @@ -2855,8 +4709,8 @@ swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; - interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "core", "wakeup"; clocks = <&lpass_txmacro>; clock-names = "iface"; @@ -3047,8 +4901,8 @@ compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "hc_irq", "pwr_irq"; @@ -3061,8 +4915,8 @@ interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; @@ -3108,12 +4962,135 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8650-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + cci0: cci@ac15000 { + compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci0_0_default &cci0_1_default>; + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; + interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci1_0_default &cci1_1_default>; + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac17000 { + compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac17000 0 0x1000>; + interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci2_0_default &cci2_1_default>; + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8650-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8650-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>, @@ -3122,11 +5099,11 @@ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS - &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, - <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", - "mdp1-mem"; + "cpu-cfg"; power-domains = <&dispcc MDSS_GDSC>; @@ -3144,7 +5121,7 @@ mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8650-dpu"; reg = <0 0x0ae01000 0 0x8f000>, - <0 0x0aeb0000 0 0x2008>; + <0 0x0aeb0000 0 0x3000>; reg-names = "mdp", "vbif"; @@ -3244,8 +5221,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -3341,8 +5318,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -3474,6 +5451,7 @@ reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; }; @@ -3488,10 +5466,10 @@ <&bi_tcxo_ao_div2>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ @@ -3507,8 +5485,6 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - - status = "disabled"; }; usb_1_hsphy: phy@88e3000 { @@ -3549,6 +5525,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { @@ -3566,6 +5544,7 @@ reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3573,6 +5552,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3582,14 +5562,16 @@ compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -3610,6 +5592,13 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; @@ -3623,7 +5612,7 @@ compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>; iommus = <&apps_smmu 0x40 0>; @@ -3661,6 +5650,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; @@ -3686,8 +5676,8 @@ reg = <0 0x0c228000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; @@ -3701,8 +5691,8 @@ reg = <0 0x0c229000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; @@ -3716,8 +5706,8 @@ reg = <0 0x0c22a000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ - interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "uplow", "critical"; @@ -3775,7 +5765,7 @@ compatible = "qcom,sm8650-tlmm"; reg = <0 0x0f100000 0 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <2>; @@ -3787,6 +5777,198 @@ wakeup-parent = <&pdc>; + cci0_0_default: cci0-0-default-state { + sda-pins { + pins = "gpio113"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio114"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins = "gpio113"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio114"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins = "gpio115"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio116"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins = "gpio115"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio116"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins = "gpio117"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio118"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins = "gpio117"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio118"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins = "gpio12"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio13"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins = "gpio12"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio13"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins = "gpio112"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio153"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins = "gpio112"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio153"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_1_default: cci2-1-default-state { + sda-pins { + pins = "gpio119"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio120"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci2_1_sleep: cci2-1-sleep-state { + sda-pins { + pins = "gpio119"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio120"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + hub_i2c0_data_clk: hub-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio64", "gpio65"; @@ -4323,107 +6505,239 @@ }; }; + funnel@10042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + + reg = <0x0 0x10042000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + funnel_in1_in_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_out_funnel_in1>; + }; + }; + }; + + out-ports { + port { + funnel_in1_out_funnel_qdss: endpoint { + remote-endpoint = <&funnel_qdss_in_funnel_in1>; + }; + }; + }; + }; + + funnel@10045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + + reg = <0x0 0x10045000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + funnel_qdss_in_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_out_funnel_qdss>; + }; + }; + }; + + out-ports { + port { + funnel_qdss_out_funnel_aoss: endpoint { + remote-endpoint = <&funnel_aoss_in_funnel_qdss>; + }; + }; + }; + }; + + funnel@10b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + + reg = <0x0 0x10b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + funnel_aoss_in_funnel_qdss: endpoint { + remote-endpoint = <&funnel_qdss_out_funnel_aoss>; + }; + }; + }; + + out-ports { + port { + funnel_aoss_out_tmc_etf: endpoint { + remote-endpoint = <&tmc_etf_in_funnel_aoss>; + }; + }; + }; + }; + + tmc@10b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + + reg = <0x0 0x10b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in_funnel_aoss: endpoint { + remote-endpoint = <&funnel_aoss_out_tmc_etf>; + }; + }; + }; + }; + + funnel@13810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + + reg = <0x0 0x13810000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_apss_in_funnel_ete: endpoint { + remote-endpoint = <&funnel_ete_out_funnel_apss>; + }; + }; + }; + + out-ports { + port { + funnel_apss_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_funnel_apss>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -4436,9 +6750,9 @@ reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; @@ -4448,6 +6762,20 @@ #size-cells = <2>; ranges; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity = <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>; @@ -4469,8 +6797,8 @@ reg = <0x17421000 0x1000>, <0x17422000 0x1000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <0>; }; @@ -4478,7 +6806,7 @@ frame@17423000 { reg = <0x17423000 0x1000>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <1>; @@ -4488,7 +6816,7 @@ frame@17425000 { reg = <0x17425000 0x1000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <2>; @@ -4498,7 +6826,7 @@ frame@17427000 { reg = <0x17427000 0x1000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <3>; @@ -4508,7 +6836,7 @@ frame@17429000 { reg = <0x17429000 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <4>; @@ -4518,7 +6846,7 @@ frame@1742b000 { reg = <0x1742b000 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <5>; @@ -4528,7 +6856,7 @@ frame@1742d000 { reg = <0x1742d000 0x1000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; frame-number = <6>; @@ -4546,11 +6874,11 @@ "drv-1", "drv-2"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; - power-domains = <&CLUSTER_PD>; + power-domains = <&cluster_pd>; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; @@ -4645,6 +6973,16 @@ }; }; + epss_l3: interconnect@17d90000 { + compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; + reg = <0 0x17d90000 0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x17d91000 0 0x1000>, @@ -4656,10 +6994,10 @@ "freq-domain2", "freq-domain3"; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2", @@ -4676,7 +7014,7 @@ compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -4728,7 +7066,7 @@ compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b7400 0 0x600>; - interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -4779,160 +7117,16 @@ <0 0x25400000 0 0x200000>, <0 0x25200000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; - - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - }; - - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,sm8650-adsp-pas"; - reg = <0 0x30000000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - - power-domains = <&rpmhpd RPMHPD_LCX>, - <&rpmhpd RPMHPD_LMX>; - power-domain-names = "lcx", - "lmx"; - - memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - qcom,remote-pid = <2>; - - label = "lpass"; - - fastrpc { - compatible = "qcom,fastrpc"; - - qcom,glink-channels = "fastrpcglink-apps-dsp"; - - label = "adsp"; - - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - - iommus = <&apps_smmu 0x1003 0x80>, - <&apps_smmu 0x1043 0x20>; - dma-coherent; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; - iommus = <&apps_smmu 0x1004 0x80>, - <&apps_smmu 0x1044 0x20>; - dma-coherent; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - - iommus = <&apps_smmu 0x1005 0x80>, - <&apps_smmu 0x1045 0x20>; - dma-coherent; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - - iommus = <&apps_smmu 0x1006 0x80>, - <&apps_smmu 0x1046 0x20>; - dma-coherent; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - - iommus = <&apps_smmu 0x1007 0x40>, - <&apps_smmu 0x1067 0x0>, - <&apps_smmu 0x1087 0x0>; - dma-coherent; - }; - }; - - gpr { - compatible = "qcom,gpr"; - qcom,glink-channels = "adsp_apps"; - qcom,domain = <GPR_DOMAIN_ID_ADSP>; - qcom,intents = <512 20>; - #address-cells = <1>; - #size-cells = <0>; - - q6apm: service@1 { - compatible = "qcom,q6apm"; - reg = <GPR_APM_MODULE_IID>; - #sound-dai-cells = <0>; - qcom,protection-domain = "avs/audio", - "msm/adsp/audio_pd"; - - q6apmbedai: bedais { - compatible = "qcom,q6apm-lpass-dais"; - #sound-dai-cells = <1>; - }; - - q6apmdai: dais { - compatible = "qcom,q6apm-dais"; - iommus = <&apps_smmu 0x1001 0x80>, - <&apps_smmu 0x1061 0x0>; - }; - }; - - q6prm: service@2 { - compatible = "qcom,q6prm"; - reg = <GPR_PRM_MODULE_IID>; - qcom,protection-domain = "avs/audio", - "msm/adsp/audio_pd"; - - q6prmcc: clock-controller { - compatible = "qcom,q6prm-lpass-clocks"; - #clock-cells = <2>; - }; - }; - }; - }; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; }; nsp_noc: interconnect@320c0000 { @@ -4946,9 +7140,9 @@ remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,sm8650-cdsp-pas"; - reg = <0 0x32300000 0 0x1400000>; + reg = <0x0 0x32300000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -5000,6 +7194,8 @@ label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; @@ -5082,6 +7278,38 @@ <&apps_smmu 0x19c8 0x0>; dma-coherent; }; + + /* note: secure cb9 in downstream */ + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c0c 0x20>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x20>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@14 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + + iommus = <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x0c0e 0x20>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; }; }; }; @@ -5089,19 +7317,17 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + aoss0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; aoss0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5109,19 +7335,17 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5129,19 +7353,17 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5149,19 +7371,17 @@ }; cpuss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5169,19 +7389,17 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + cpuss3-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; cpuss3-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5189,23 +7407,9 @@ }; cpu2-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2-critical { temperature = <110000>; hysteresis = <1000>; @@ -5215,23 +7419,9 @@ }; cpu2-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu2-critical { temperature = <110000>; hysteresis = <1000>; @@ -5241,23 +7431,9 @@ }; cpu3-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3-critical { temperature = <110000>; hysteresis = <1000>; @@ -5267,23 +7443,9 @@ }; cpu3-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu3-critical { temperature = <110000>; hysteresis = <1000>; @@ -5293,23 +7455,9 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu4-critical { temperature = <110000>; hysteresis = <1000>; @@ -5319,23 +7467,9 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu4-critical { temperature = <110000>; hysteresis = <1000>; @@ -5345,23 +7479,9 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu5-critical { temperature = <110000>; hysteresis = <1000>; @@ -5371,23 +7491,9 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu5-critical { temperature = <110000>; hysteresis = <1000>; @@ -5397,23 +7503,9 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu6-critical { temperature = <110000>; hysteresis = <1000>; @@ -5423,23 +7515,9 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu6-critical { temperature = <110000>; hysteresis = <1000>; @@ -5449,19 +7527,17 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + aoss1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; aoss1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5469,23 +7545,9 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu7-critical { temperature = <110000>; hysteresis = <1000>; @@ -5495,23 +7557,9 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu7-critical { temperature = <110000>; hysteresis = <1000>; @@ -5521,23 +7569,9 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu7-critical { temperature = <110000>; hysteresis = <1000>; @@ -5547,23 +7581,9 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu0-critical { temperature = <110000>; hysteresis = <1000>; @@ -5573,23 +7593,9 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu1-critical { temperature = <110000>; hysteresis = <1000>; @@ -5599,19 +7605,17 @@ }; nsphvx0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 6>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphvx0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; - nsphvx1-critical { - temperature = <110000>; + nsphvx0-critical { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5619,19 +7623,17 @@ }; nsphvx1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 7>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphvx1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphvx1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5639,19 +7641,17 @@ }; nsphmx0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 8>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5659,19 +7659,17 @@ }; nsphmx1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5679,19 +7677,17 @@ }; nsphmx2-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5699,19 +7695,17 @@ }; nsphmx3-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 11>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + nsphmx3-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; nsphmx3-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5719,19 +7713,17 @@ }; video-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 12>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + video-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; video-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5739,19 +7731,17 @@ }; ddr-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 13>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + ddr-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; ddr-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5759,19 +7749,17 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + camera0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; camera0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5779,19 +7767,17 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + camera1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; camera1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5799,19 +7785,17 @@ }; aoss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 0>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + aoss2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; aoss2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5820,18 +7804,31 @@ gpuss0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + cooling-maps { + map0 { + trip = <&gpu0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss0-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5840,18 +7837,31 @@ gpuss1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss1-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5860,18 +7870,31 @@ gpuss2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + cooling-maps { + map0 { + trip = <&gpu2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu2_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss2-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5880,18 +7903,31 @@ gpuss3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + cooling-maps { + map0 { + trip = <&gpu3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu3_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss3-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5900,18 +7936,31 @@ gpuss4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + cooling-maps { + map0 { + trip = <&gpu4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu4_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss4-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5920,18 +7969,31 @@ gpuss5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + cooling-maps { + map0 { + trip = <&gpu5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu5_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss5-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5940,18 +8002,31 @@ gpuss6-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + cooling-maps { + map0 { + trip = <&gpu6_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu6_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss6-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5960,18 +8035,31 @@ gpuss7-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + cooling-maps { + map0 { + trip = <&gpu7_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; + gpu7_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; - gpuss7-critical { + trip-point1 { temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5979,19 +8067,17 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem0-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem0-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -5999,19 +8085,17 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem1-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem1-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6019,19 +8103,17 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 11>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem2-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem2-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6039,19 +8121,17 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 12>; trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; + modem3-hot { + temperature = <110000>; + hysteresis = <1000>; type = "hot"; }; modem3-critical { - temperature = <110000>; + temperature = <115000>; hysteresis = <0>; type = "critical"; }; @@ -6062,9 +8142,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; }; |