diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/x1e80100.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/x1e80100.dtsi | 4885 |
1 files changed, 4599 insertions, 286 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 6b40082bac68..4936fa5b98ff 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4,8 +4,10 @@ */ #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> #include <dt-bindings/clock/qcom,x1e80100-gcc.h> +#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h> @@ -36,7 +38,7 @@ sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; @@ -63,208 +65,208 @@ #address-cells = <2>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x0>; enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd0>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; - L2_0: l2-cache { + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; - CPU1: cpu@100 { + cpu1: cpu@100 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x100>; enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD1>; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd1>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU2: cpu@200 { + cpu2: cpu@200 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x200>; enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD2>; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd2>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU3: cpu@300 { + cpu3: cpu@300 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x300>; enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD3>; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd3>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU4: cpu@10000 { + cpu4: cpu@10000 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x10000>; enable-method = "psci"; - next-level-cache = <&L2_1>; - power-domains = <&CPU_PD4>; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd4>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; - L2_1: l2-cache { + l2_1: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; - CPU5: cpu@10100 { + cpu5: cpu@10100 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x10100>; enable-method = "psci"; - next-level-cache = <&L2_1>; - power-domains = <&CPU_PD5>; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd5>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU6: cpu@10200 { + cpu6: cpu@10200 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x10200>; enable-method = "psci"; - next-level-cache = <&L2_1>; - power-domains = <&CPU_PD6>; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd6>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU7: cpu@10300 { + cpu7: cpu@10300 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x10300>; enable-method = "psci"; - next-level-cache = <&L2_1>; - power-domains = <&CPU_PD7>; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd7>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU8: cpu@20000 { + cpu8: cpu@20000 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x20000>; enable-method = "psci"; - next-level-cache = <&L2_2>; - power-domains = <&CPU_PD8>; + next-level-cache = <&l2_2>; + power-domains = <&cpu_pd8>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; - L2_2: l2-cache { + l2_2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; }; - CPU9: cpu@20100 { + cpu9: cpu@20100 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x20100>; enable-method = "psci"; - next-level-cache = <&L2_2>; - power-domains = <&CPU_PD9>; + next-level-cache = <&l2_2>; + power-domains = <&cpu_pd9>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU10: cpu@20200 { + cpu10: cpu@20200 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x20200>; enable-method = "psci"; - next-level-cache = <&L2_2>; - power-domains = <&CPU_PD10>; + next-level-cache = <&l2_2>; + power-domains = <&cpu_pd10>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; - CPU11: cpu@20300 { + cpu11: cpu@20300 { device_type = "cpu"; compatible = "qcom,oryon"; reg = <0x0 0x20300>; enable-method = "psci"; - next-level-cache = <&L2_2>; - power-domains = <&CPU_PD11>; + next-level-cache = <&l2_2>; + power-domains = <&cpu_pd11>; power-domain-names = "psci"; - cpu-idle-states = <&CLUSTER_C4>; + cpu-idle-states = <&cluster_c4>; }; cpu-map { cluster0 { core0 { - cpu = <&CPU0>; + cpu = <&cpu0>; }; core1 { - cpu = <&CPU1>; + cpu = <&cpu1>; }; core2 { - cpu = <&CPU2>; + cpu = <&cpu2>; }; core3 { - cpu = <&CPU3>; + cpu = <&cpu3>; }; }; cluster1 { core0 { - cpu = <&CPU4>; + cpu = <&cpu4>; }; core1 { - cpu = <&CPU5>; + cpu = <&cpu5>; }; core2 { - cpu = <&CPU6>; + cpu = <&cpu6>; }; core3 { - cpu = <&CPU7>; + cpu = <&cpu7>; }; }; cluster2 { core0 { - cpu = <&CPU8>; + cpu = <&cpu8>; }; core1 { - cpu = <&CPU9>; + cpu = <&cpu9>; }; core2 { - cpu = <&CPU10>; + cpu = <&cpu10>; }; core3 { - cpu = <&CPU11>; + cpu = <&cpu11>; }; }; }; @@ -272,42 +274,53 @@ idle-states { entry-method = "psci"; - CLUSTER_C4: cpu-sleep-0 { + cluster_c4: cpu-sleep-0 { compatible = "arm,idle-state"; idle-state-name = "ret"; arm,psci-suspend-param = <0x00000004>; entry-latency-us = <180>; - exit-latency-us = <320>; - min-residency-us = <1000>; + exit-latency-us = <500>; + min-residency-us = <600>; }; }; domain-idle-states { - CLUSTER_CL4: cluster-sleep-0 { + cluster_cl4: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "l2-ret"; arm,psci-suspend-param = <0x01000044>; entry-latency-us = <350>; exit-latency-us = <500>; min-residency-us = <2500>; }; - CLUSTER_CL5: cluster-sleep-1 { + cluster_cl5: cluster-sleep-1 { compatible = "domain-idle-state"; - idle-state-name = "ret-pll-off"; arm,psci-suspend-param = <0x01000054>; entry-latency-us = <2200>; - exit-latency-us = <2500>; + exit-latency-us = <4000>; min-residency-us = <7000>; }; }; }; + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-x1e80100", "qcom,scm"; interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + qcom,dload-mode = <&tcsr 0x19000>; }; }; @@ -338,85 +351,85 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: power-domain-cpu0 { + cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD0>; + power-domains = <&cluster_pd0>; }; - CPU_PD1: power-domain-cpu1 { + cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD0>; + power-domains = <&cluster_pd0>; }; - CPU_PD2: power-domain-cpu2 { + cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD0>; + power-domains = <&cluster_pd0>; }; - CPU_PD3: power-domain-cpu3 { + cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD0>; + power-domains = <&cluster_pd0>; }; - CPU_PD4: power-domain-cpu4 { + cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD1>; + power-domains = <&cluster_pd1>; }; - CPU_PD5: power-domain-cpu5 { + cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD1>; + power-domains = <&cluster_pd1>; }; - CPU_PD6: power-domain-cpu6 { + cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD1>; + power-domains = <&cluster_pd1>; }; - CPU_PD7: power-domain-cpu7 { + cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD1>; + power-domains = <&cluster_pd1>; }; - CPU_PD8: power-domain-cpu8 { + cpu_pd8: power-domain-cpu8 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD2>; + power-domains = <&cluster_pd2>; }; - CPU_PD9: power-domain-cpu9 { + cpu_pd9: power-domain-cpu9 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD2>; + power-domains = <&cluster_pd2>; }; - CPU_PD10: power-domain-cpu10 { + cpu_pd10: power-domain-cpu10 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD2>; + power-domains = <&cluster_pd2>; }; - CPU_PD11: power-domain-cpu11 { + cpu_pd11: power-domain-cpu11 { #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD2>; + power-domains = <&cluster_pd2>; }; - CLUSTER_PD0: power-domain-cpu-cluster0 { + cluster_pd0: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; - power-domains = <&SYSTEM_PD>; + domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; + power-domains = <&system_pd>; }; - CLUSTER_PD1: power-domain-cpu-cluster1 { + cluster_pd1: power-domain-cpu-cluster1 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; - power-domains = <&SYSTEM_PD>; + domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; + power-domains = <&system_pd>; }; - CLUSTER_PD2: power-domain-cpu-cluster2 { + cluster_pd2: power-domain-cpu-cluster2 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; - power-domains = <&SYSTEM_PD>; + domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; + power-domains = <&system_pd>; }; - SYSTEM_PD: power-domain-system { + system_pd: power-domain-system { #power-domain-cells = <0>; /* TODO: system-wide idle states */ }; @@ -676,6 +689,34 @@ }; }; + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + + qup_opp_table_120mhz: opp-table-qup120mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + smp2p-adsp { compatible = "qcom,smp2p"; @@ -742,9 +783,9 @@ clocks = <&bi_tcxo_div2>, <&sleep_clk>, - <0>, + <&pcie3_phy>, <&pcie4_phy>, - <0>, + <&pcie5_phy>, <&pcie6a_phy>, <0>, <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, @@ -830,6 +871,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -863,6 +907,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -896,6 +943,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -929,6 +979,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -962,6 +1015,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -995,6 +1051,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -1028,6 +1087,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -1061,6 +1123,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -1094,6 +1159,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -1127,6 +1195,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -1160,6 +1231,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -1193,6 +1267,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -1223,6 +1300,9 @@ interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + pinctrl-0 = <&qup_uart21_default>; pinctrl-names = "default"; @@ -1248,6 +1328,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, <&gpi_dma2 1 6 QCOM_GPI_I2C>; dma-names = "tx", @@ -1281,6 +1364,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, <&gpi_dma2 1 6 QCOM_GPI_SPI>; dma-names = "tx", @@ -1314,6 +1400,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, <&gpi_dma2 1 7 QCOM_GPI_I2C>; dma-names = "tx", @@ -1347,6 +1436,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, <&gpi_dma2 1 7 QCOM_GPI_SPI>; dma-names = "tx", @@ -1424,6 +1516,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -1457,6 +1552,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -1490,6 +1588,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -1523,6 +1624,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -1556,6 +1660,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -1589,6 +1696,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -1622,6 +1732,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -1655,6 +1768,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -1688,6 +1804,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -1721,6 +1840,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -1754,6 +1876,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -1787,6 +1912,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -1820,6 +1948,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", @@ -1853,6 +1984,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", @@ -1867,6 +2001,31 @@ status = "disabled"; }; + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a98000 0 0x4000>; + + interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; @@ -1886,6 +2045,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", @@ -1919,6 +2081,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names = "tx", @@ -1978,7 +2143,7 @@ i2c0: i2c@b80000 { compatible = "qcom,geni-i2c"; - reg = <0 0xb80000 0 0x4000>; + reg = <0 0x00b80000 0 0x4000>; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; @@ -1995,6 +2160,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", @@ -2028,6 +2196,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", @@ -2061,6 +2232,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -2094,6 +2268,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", @@ -2127,6 +2304,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -2141,9 +2321,34 @@ status = "disabled"; }; + uart2: serial@b88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00b88000 0 0x4000>; + + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + spi2: spi@b88000 { compatible = "qcom,geni-spi"; - reg = <0 0xb88000 0 0x4000>; + reg = <0 0x00b88000 0 0x4000>; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; @@ -2160,6 +2365,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -2193,6 +2401,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", @@ -2226,6 +2437,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", @@ -2242,7 +2456,7 @@ i2c4: i2c@b90000 { compatible = "qcom,geni-i2c"; - reg = <0 0xb90000 0 0x4000>; + reg = <0 0x00b90000 0 0x4000>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; @@ -2259,6 +2473,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", @@ -2292,6 +2509,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", @@ -2325,6 +2545,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", @@ -2358,6 +2581,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", @@ -2391,6 +2617,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", @@ -2424,6 +2653,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", @@ -2457,6 +2689,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", @@ -2490,6 +2725,9 @@ "qup-config", "qup-memory"; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names = "tx", @@ -2505,6 +2743,66 @@ }; }; + tsens0: thermal-sensor@c271000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c271000 0 0x1000>, + <0 0x0c222000 0 0x1000>; + + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c272000 0 0x1000>, + <0 0x0c223000 0 0x1000>; + + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c273000 0 0x1000>, + <0 0x0c224000 0 0x1000>; + + interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c274000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c274000 0 0x1000>, + <0 0x0c225000 0 0x1000>; + + interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + usb_1_ss0_hsphy: phy@fd3000 { compatible = "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -2542,7 +2840,37 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2582,7 +2910,37 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; + }; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2622,12 +2980,42 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; + }; + }; + }; }; cnoc_main: interconnect@1500000 { compatible = "qcom,x1e80100-cnoc-main"; - reg = <0 0x1500000 0 0x14400>; + reg = <0 0x01500000 0 0x14400>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2636,7 +3024,7 @@ config_noc: interconnect@1600000 { compatible = "qcom,x1e80100-cnoc-cfg"; - reg = <0 0x1600000 0 0x6600>; + reg = <0 0x01600000 0 0x6600>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2645,7 +3033,7 @@ system_noc: interconnect@1680000 { compatible = "qcom,x1e80100-system-noc"; - reg = <0 0x1680000 0 0x1c080>; + reg = <0 0x01680000 0 0x1c080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2654,7 +3042,7 @@ pcie_south_anoc: interconnect@16c0000 { compatible = "qcom,x1e80100-pcie-south-anoc"; - reg = <0 0x16c0000 0 0xd080>; + reg = <0 0x016c0000 0 0xd080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2663,7 +3051,7 @@ pcie_center_anoc: interconnect@16d0000 { compatible = "qcom,x1e80100-pcie-center-anoc"; - reg = <0 0x16d0000 0 0x7000>; + reg = <0 0x016d0000 0 0x7000>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2672,7 +3060,7 @@ aggre1_noc: interconnect@16e0000 { compatible = "qcom,x1e80100-aggre1-noc"; - reg = <0 0x16E0000 0 0x14400>; + reg = <0 0x016e0000 0 0x14400>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2681,7 +3069,7 @@ aggre2_noc: interconnect@1700000 { compatible = "qcom,x1e80100-aggre2-noc"; - reg = <0 0x1700000 0 0x1c400>; + reg = <0 0x01700000 0 0x1c400>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2690,7 +3078,7 @@ pcie_north_anoc: interconnect@1740000 { compatible = "qcom,x1e80100-pcie-north-anoc"; - reg = <0 0x1740000 0 0x9080>; + reg = <0 0x01740000 0 0x9080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2699,7 +3087,7 @@ usb_center_anoc: interconnect@1750000 { compatible = "qcom,x1e80100-usb-center-anoc"; - reg = <0 0x1750000 0 0x8800>; + reg = <0 0x01750000 0 0x8800>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2708,7 +3096,7 @@ usb_north_anoc: interconnect@1760000 { compatible = "qcom,x1e80100-usb-north-anoc"; - reg = <0 0x1760000 0 0x7080>; + reg = <0 0x01760000 0 0x7080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2717,7 +3105,7 @@ usb_south_anoc: interconnect@1770000 { compatible = "qcom,x1e80100-usb-south-anoc"; - reg = <0 0x1770000 0 0xf080>; + reg = <0 0x01770000 0 0xf080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -2726,36 +3114,242 @@ mmss_noc: interconnect@1780000 { compatible = "qcom,x1e80100-mmss-noc"; - reg = <0 0x1780000 0 0x5B800>; + reg = <0 0x01780000 0 0x5B800>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + pcie3: pcie@1bd0000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0x0 0x01bd0000 0x0 0x3000>, + <0x0 0x78000000 0x0 0xf1d>, + <0x0 0x78000f40 0x0 0xa8>, + <0x0 0x78001000 0x0 0x1000>, + <0x0 0x78100000 0x0 0x100000>, + <0x0 0x01bd3000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, + <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <3>; + num-lanes = <8>; + + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3_BCR>, + <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_3_GDSC>; + + phys = <&pcie3_phy>; + phy-names = "pciephy"; + + operating-points-v2 = <&pcie3_opp_table>; + + status = "disabled"; + + pcie3_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 1 x4 and GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 1 x8 and GEN 2 x4 */ + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + }; + + /* GEN 2 x8 */ + opp-40000000 { + opp-hz = /bits/ 64 <40000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <4000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 3 x4 and GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + }; + + /* GEN 3 x8 and GEN 4 x4 */ + opp-64000000 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + }; + + /* GEN 4 x8 */ + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <15753000 1>; + }; + }; + }; + + pcie3_phy: phy@1be0000 { + compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; + reg = <0 0x01be0000 0 0x10000>; + + clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, + <&gcc GCC_PCIE_3_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_8L_CLKREF_EN>, + <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3_PIPE_CLK>, + <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_3_PHY_BCR>, + <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + pcie6a: pci@1bf8000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01bf8000 0 0x3000>, - <0 0x70000000 0 0xf1d>, - <0 0x70000f20 0 0xa8>, + <0 0x70000000 0 0xf20>, + <0 0x70000f40 0 0xa8>, <0 0x70001000 0 0x1000>, - <0 0x70100000 0 0x100000>; + <0 0x70100000 0 0x100000>, + <0 0x01bfb000 0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", - "config"; + "config", + "mhi"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, - <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; - bus-range = <0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; + bus-range = <0x00 0xff>; dma-coherent; - linux,pci-domain = <7>; - num-lanes = <2>; + linux,pci-domain = <6>; + num-lanes = <4>; + + msi-map = <0x0 &gic_its 0xe0000 0x10000>; interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, @@ -2812,6 +3406,7 @@ "link_down"; power-domains = <&gcc GCC_PCIE_6A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie6a_phy>; phy-names = "pciephy"; @@ -2820,19 +3415,22 @@ }; pcie6a_phy: phy@1bfc000 { - compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; - reg = <0 0x01bfc000 0 0x2000>; + compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; + reg = <0 0x01bfc000 0 0x2000>, + <0 0x01bfe000 0 0x2000>; clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_PCIE_4L_CLKREF_EN>, <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_6A_PIPE_CLK>; + <&gcc GCC_PCIE_6A_PIPE_CLK>, + <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + "pipe", + "pipediv2"; resets = <&gcc GCC_PCIE_6A_PHY_BCR>, <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; @@ -2844,6 +3442,8 @@ power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + qcom,4ln-config-sel = <&tcsr 0x1a000 0>; + #clock-cells = <0>; clock-output-names = "pcie6a_pipe_clk"; @@ -2852,6 +3452,128 @@ status = "disabled"; }; + pcie5: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-x1e80100"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x7e000000 0 0xf1d>, + <0 0x7e000f40 0 0xa8>, + <0 0x7e001000 0 0x1000>, + <0 0x7e100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, + <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <2>; + + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, + <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_5_BCR>, + <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_5_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + phys = <&pcie5_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie5_phy: phy@1c06000 { + compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_5_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie5_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + pcie4: pci@1c08000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; @@ -2869,15 +3591,17 @@ "mhi"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, - <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, + <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent; - linux,pci-domain = <5>; + linux,pci-domain = <4>; num-lanes = <2>; + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -2920,7 +3644,7 @@ assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; assigned-clock-rates = <19200000>; - interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; @@ -2933,11 +3657,22 @@ "link_down"; power-domains = <&gcc GCC_PCIE_4_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; status = "disabled"; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c0e000 { @@ -2946,14 +3681,16 @@ clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_4_PIPE_CLK>; + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe"; + "pipe", + "pipediv2"; resets = <&gcc GCC_PCIE_4_PHY_BCR>; reset-names = "phy"; @@ -2985,6 +3722,201 @@ #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050c01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <14398438>; + }; + + opp-925000000 { + opp-hz = /bits/ 64 <925000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <14398438>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <12449219>; + }; + + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <10687500>; + }; + + opp-687000000 { + opp-hz = /bits/ 64 <687000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <8171875>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <6074219>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <3000000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136719>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,x1e80100-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>; @@ -2996,13 +3928,150 @@ nsp_noc: interconnect@320c0000 { compatible = "qcom,x1e80100-nsp-noc"; - reg = <0 0x320C0000 0 0xE080>; + reg = <0 0x320C0000 0 0xe080>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,x1e80100-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, + <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + dma-coherent; + }; + }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + lpass_wsa2macro: codec@6aa0000 { compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; reg = <0 0x06aa0000 0 0x1000>; @@ -3031,6 +4100,8 @@ pinctrl-0 = <&wsa2_swr_active>; pinctrl-names = "default"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; + reset-names = "swr_audio_cgcr"; qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -3079,6 +4150,8 @@ pinctrl-0 = <&rx_swr_active>; pinctrl-names = "default"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; qcom,din-ports = <1>; qcom,dout-ports = <11>; @@ -3088,7 +4161,7 @@ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; @@ -3143,6 +4216,8 @@ pinctrl-0 = <&wsa_swr_active>; pinctrl-names = "default"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -3163,6 +4238,13 @@ status = "disabled"; }; + lpass_audiocc: clock-controller@6b6c000 { + compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; + reg = <0 0x06b6c000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; @@ -3172,6 +4254,8 @@ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "core", "wakeup"; label = "TX"; + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; pinctrl-0 = <&tx_swr_active>; pinctrl-names = "default"; @@ -3328,9 +4412,16 @@ }; }; + lpasscc: clock-controller@6ea0000 { + compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; + reg = <0 0x06ea0000 0 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,x1e80100-lpass-ag-noc"; - reg = <0 0x7e40000 0 0xE080>; + reg = <0 0x07e40000 0 0xe080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -3339,7 +4430,7 @@ lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,x1e80100-lpass-lpiaon-noc"; - reg = <0 0x7400000 0 0x19080>; + reg = <0 0x07400000 0 0x19080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -3348,13 +4439,119 @@ lpass_lpicx_noc: interconnect@7430000 { compatible = "qcom,x1e80100-lpass-lpicx-noc"; - reg = <0 0x7430000 0 0x3A200>; + reg = <0 0x07430000 0 0x3A200>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x520 0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + sdhc_4: mmc@8844000 { + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08844000 0 0x1000>; + + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC4_AHB_CLK>, + <&gcc GCC_SDCC4_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x160 0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc4_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc4_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_2_hsphy: phy@88e0000 { compatible = "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -3369,6 +4566,90 @@ status = "disabled"; }; + usb_mp_hsphy0: phy@88e1000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e1000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_hsphy1: phy@88e2000 { + compatible = "qcom,x1e80100-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e2000 0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_qmpphy0: phy@88e3000 { + compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; + reg = <0 0x088e3000 0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy", + "phy_phy"; + + power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb_mp_phy0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_mp_qmpphy1: phy@88e5000 { + compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; + reg = <0 0x088e5000 0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy", + "phy_phy"; + + power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "usb_mp_phy1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + usb_1_ss2: usb@a0f8800 { compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; reg = <0 0x0a0f8800 0 0x400>; @@ -3442,11 +4723,28 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3482,7 +4780,7 @@ <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <&pdc 50 IRQ_TYPE_EDGE_BOTH>, <&pdc 49 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "pwr_event", @@ -3508,19 +4806,116 @@ usb_2_dwc3: usb@a200000 { compatible = "snps,dwc3"; reg = <0 0x0a200000 0 0xcd00>; - interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x14e0 0x0>; phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - port { - usb_2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; }; }; }; }; + usb_mp: usb@a4f8800 { + compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr", + "noc_aggr_north", + "noc_aggr_south", + "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 52 IRQ_TYPE_EDGE_BOTH>, + <&pdc 51 IRQ_TYPE_EDGE_BOTH>, + <&pdc 54 IRQ_TYPE_EDGE_BOTH>, + <&pdc 53 IRQ_TYPE_EDGE_BOTH>, + <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_1", "pwr_event_2", + "hs_phy_1", "hs_phy_2", + "dp_hs_phy_1", "dm_hs_phy_1", + "dp_hs_phy_2", "dm_hs_phy_2", + "ss_phy_1", "ss_phy_2"; + + power-domains = <&gcc GCC_USB30_MP_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "usb-ddr", + "apps-usb"; + + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_mp_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x1400 0x0>; + + phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; + phy-names = "usb2-0", "usb3-0", + "usb2-1", "usb3-1"; + dr_mode = "host"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; + }; + }; + usb_1_ss0: usb@a6f8800 { compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -3587,11 +4982,28 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3670,11 +5082,28 @@ snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3809,11 +5238,11 @@ mdss_dp0: displayport-controller@ae90000 { compatible = "qcom,x1e80100-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0x600>, + <0 0x0ae91000 0 0x400>, + <0 0x0ae91400 0 0x400>; interrupts-extended = <&mdss 12>; @@ -3860,6 +5289,7 @@ reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; }; }; }; @@ -3891,11 +5321,11 @@ mdss_dp1: displayport-controller@ae98000 { compatible = "qcom,x1e80100-dp"; - reg = <0 0xae98000 0 0x200>, - <0 0xae98200 0 0x200>, - <0 0xae98400 0 0x600>, - <0 0xae99000 0 0x400>, - <0 0xae99400 0 0x400>; + reg = <0 0x0ae98000 0 0x200>, + <0 0x0ae98200 0 0x200>, + <0 0x0ae98400 0 0x600>, + <0 0x0ae99000 0 0x400>, + <0 0x0ae99400 0 0x400>; interrupts-extended = <&mdss 13>; @@ -3942,6 +5372,7 @@ reg = <1>; mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; }; }; }; @@ -3973,11 +5404,11 @@ mdss_dp2: displayport-controller@ae9a000 { compatible = "qcom,x1e80100-dp"; - reg = <0 0xae9a000 0 0x200>, - <0 0xae9a200 0 0x200>, - <0 0xae9a400 0 0x600>, - <0 0xae9b000 0 0x400>, - <0 0xae9b400 0 0x400>; + reg = <0 0x0ae9a000 0 0x200>, + <0 0x0ae9a200 0 0x200>, + <0 0x0ae9a400 0 0x600>, + <0 0x0ae9b000 0 0x400>, + <0 0x0ae9b400 0 0x400>; interrupts-extended = <&mdss 14>; @@ -3994,14 +5425,14 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss_dp2_phy 0>, - <&mdss_dp2_phy 1>; + assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp2_opp_table>; power-domains = <&rpmhpd RPMHPD_MMCX>; - phys = <&mdss_dp2_phy>; + phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -4021,6 +5452,10 @@ port@1 { reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; + }; }; }; @@ -4051,11 +5486,11 @@ mdss_dp3: displayport-controller@aea0000 { compatible = "qcom,x1e80100-dp"; - reg = <0 0xaea0000 0 0x200>, - <0 0xaea0200 0 0x200>, - <0 0xaea0400 0 0x600>, - <0 0xaea1000 0 0x400>, - <0 0xaea1400 0 0x400>; + reg = <0 0x0aea0000 0 0x200>, + <0 0x0aea0200 0 0x200>, + <0 0x0aea0400 0 0x600>, + <0 0x0aea1000 0 0x400>, + <0 0x0aea1400 0 0x400>; interrupts-extended = <&mdss 15>; @@ -4095,8 +5530,6 @@ mdss_dp3_in: endpoint { remote-endpoint = <&mdss_intf5_out>; - - link-frequencies = /bits/ 64 <8100000000>; }; }; @@ -4187,8 +5620,8 @@ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, - <&mdss_dp2_phy 0>, /* dp2 */ - <&mdss_dp2_phy 1>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&mdss_dp3_phy 0>, /* dp3 */ <&mdss_dp3_phy 1>; power-domains = <&rpmhpd RPMHPD_MMCX>; @@ -4221,6 +5654,53 @@ #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi: arbiter@c400000 { + compatible = "qcom,x1e80100-spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x400000>, + <0 0x0c440000 0 0x80000>; + reg-names = "core", "chnls", "obsrvr"; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg = <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c432000 { + reg = <0 0x0c432000 0 0x4000>, + <0 0x0c4d0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + }; tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; @@ -4789,12 +6269,1559 @@ bias-disable; }; + qup_uart2_default: qup-uart2-default-state { + cts-pins { + pins = "gpio8"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio10"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + cts-pins { + pins = "gpio56"; + function = "qup1_se6"; + bias-bus-hold; + }; + + rts-pins { + pins = "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio58"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio59"; + function = "qup1_se6"; + bias-pull-up; + }; + }; + qup_uart21_default: qup-uart21-default-state { - /* TX, RX */ - pins = "gpio86", "gpio87"; - function = "qup2_se5"; - drive-strength = <2>; - bias-disable; + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + tpdm@10003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10003000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + status = "disabled"; + + out-ports { + port { + dcc_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in0>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + qdss_tpda_in0: endpoint { + remote-endpoint = <&dcc_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + qdss_tpda_in1: endpoint { + remote-endpoint = <&qdss_tpdm_out>; + }; + }; + }; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = <&funnel0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qdss_tpdm_out: endpoint { + remote-endpoint = <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + funnel0_in6: endpoint { + remote-endpoint = <&qdss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&qdss_funnel_in0>; + }; + }; + }; + }; + + funnel@10042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10042000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + funnel1_in2: endpoint { + remote-endpoint = <&tmess_funnel_out>; + }; + }; + + port@5 { + reg = <5>; + + funnel1_in5: endpoint { + remote-endpoint = <&dlst_funnel_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel1_in6: endpoint { + remote-endpoint = <&dlct1_funnel_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&qdss_funnel_in1>; + }; + }; + }; + }; + + funnel@10045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10045000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + qdss_funnel_in0: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + + qdss_funnel_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; + + out-ports { + port { + qdss_funnel_out: endpoint { + remote-endpoint = <&aoss_funnel_in7>; + }; + }; + }; + }; + + tpdm@10800000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + mxa_tpdm_out: endpoint { + remote-endpoint = <&dlct2_tpda_in15>; + }; + }; + }; + }; + + tpdm@1082c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1082c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + gcc_tpdm_out: endpoint { + remote-endpoint = <&dlct1_tpda_in21>; + }; + }; + }; + }; + + tpdm@10841000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10841000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + prng_tpdm_out: endpoint { + remote-endpoint = <&dlct1_tpda_in19>; + }; + }; + }; + }; + + tpdm@10844000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10844000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + lpass_cx_tpdm_out: endpoint { + remote-endpoint = <&lpass_cx_funnel_in0>; + }; + }; + }; + }; + + funnel@10846000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10846000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + lpass_cx_funnel_in0: endpoint { + remote-endpoint = <&lpass_cx_tpdm_out>; + }; + }; + }; + + out-ports { + port { + lpass_cx_funnel_out: endpoint { + remote-endpoint = <&dlct1_tpda_in4>; + }; + }; + }; + }; + + cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1098b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@109d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + status = "disabled"; + + out-ports { + port { + qm_tpdm_out: endpoint { + remote-endpoint = <&dlct1_tpda_in20>; + }; + }; + }; + }; + + tpdm@10ac0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10ac0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + status = "disabled"; + + out-ports { + port { + dlst_tpdm0_out: endpoint { + remote-endpoint = <&dlst_tpda_in8>; + }; + }; + }; + }; + + tpdm@10ac1000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10ac1000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + dlst_tpdm1_out: endpoint { + remote-endpoint = <&dlst_tpda_in9>; + }; + }; + }; + }; + + tpda@10ac4000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10ac4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + + dlst_tpda_in8: endpoint { + remote-endpoint = <&dlst_tpdm0_out>; + }; + }; + + port@9 { + reg = <9>; + + dlst_tpda_in9: endpoint { + remote-endpoint = <&dlst_tpdm1_out>; + }; + }; + }; + + out-ports { + port { + dlst_tpda_out: endpoint { + remote-endpoint = <&dlst_funnel_in0>; + }; + }; + }; + }; + + funnel@10ac5000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10ac5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + dlst_funnel_in0: endpoint { + remote-endpoint = <&dlst_tpda_out>; + }; + }; + }; + + out-ports { + port { + dlst_funnel_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; + }; + }; + + funnel@10b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + + aoss_funnel_in3: endpoint { + remote-endpoint = <&ddr_lpi_funnel_out>; + }; + }; + + port@6 { + reg = <6>; + + aoss_funnel_in6: endpoint { + remote-endpoint = <&aoss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + + aoss_funnel_in7: endpoint { + remote-endpoint = <&qdss_funnel_out>; + }; + }; + }; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = <&etf0_in>; + }; + }; + }; + }; + + etf0: tmc@10b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = <&aoss_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = <&swao_rep_in>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10b06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = <&etf0_out>; + }; + }; + }; + + out-ports { + port { + swao_rep_out1: endpoint { + remote-endpoint = <&eud_in>; + }; + }; + }; + }; + + tpda@10b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint = <&aoss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint = <&aoss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint = <&aoss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint = <&aoss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint = <&aoss_tpdm4_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = <&aoss_funnel_in6>; + }; + }; + }; + }; + + tpdm@10b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm0_out: endpoint { + remote-endpoint = <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@10b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm1_out: endpoint { + remote-endpoint = <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@10b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm2_out: endpoint { + remote-endpoint = <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@10b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm3_out: endpoint { + remote-endpoint = <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@10b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm4_out: endpoint { + remote-endpoint = <&aoss_tpda_in4>; + }; + }; + }; + }; + + tpdm@10b20000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b20000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + status = "disabled"; + + out-ports { + port { + lpicc_tpdm_out: endpoint { + remote-endpoint = <&ddr_lpi_tpda_in>; + }; + }; + }; + }; + + tpda@10b23000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10b23000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + ddr_lpi_tpda_in: endpoint { + remote-endpoint = <&lpicc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + ddr_lpi_tpda_out: endpoint { + remote-endpoint = <&ddr_lpi_funnel_in0>; + }; + }; + }; + }; + + funnel@10b24000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10b24000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + ddr_lpi_funnel_in0: endpoint { + remote-endpoint = <&ddr_lpi_tpda_out>; + }; + }; + }; + + out-ports { + port { + ddr_lpi_funnel_out: endpoint { + remote-endpoint = <&aoss_funnel_in3>; + }; + }; + }; + }; + + tpdm@10c08000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10c08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + mm_tpdm_out: endpoint { + remote-endpoint = <&mm_funnel_in4>; + }; + }; + }; + }; + + funnel@10c0b000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10c0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + mm_funnel_in4: endpoint { + remote-endpoint = <&mm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + mm_funnel_out: endpoint { + remote-endpoint = <&dlct2_tpda_in4>; + }; + }; + }; + }; + + tpdm@10c28000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10c28000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + dlct1_tpdm_out: endpoint { + remote-endpoint = <&dlct1_tpda_in26>; + }; + }; + }; + }; + + tpdm@10c29000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10c29000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + ipcc_tpdm_out: endpoint { + remote-endpoint = <&dlct1_tpda_in27>; + }; + }; + }; + }; + + tpda@10c2b000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10c2b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + dlct1_tpda_in4: endpoint { + remote-endpoint = <&lpass_cx_funnel_out>; + }; + }; + + port@13 { + reg = <19>; + + dlct1_tpda_in19: endpoint { + remote-endpoint = <&prng_tpdm_out>; + }; + }; + + port@14 { + reg = <20>; + + dlct1_tpda_in20: endpoint { + remote-endpoint = <&qm_tpdm_out>; + }; + }; + + port@15 { + reg = <21>; + + dlct1_tpda_in21: endpoint { + remote-endpoint = <&gcc_tpdm_out>; + }; + }; + + port@1a { + reg = <26>; + + dlct1_tpda_in26: endpoint { + remote-endpoint = <&dlct1_tpdm_out>; + }; + }; + + port@1b { + reg = <27>; + + dlct1_tpda_in27: endpoint { + remote-endpoint = <&ipcc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + dlct1_tpda_out: endpoint { + remote-endpoint = <&dlct1_funnel_in0>; + }; + }; + }; + }; + + funnel@10c2c000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10c2c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dlct1_funnel_in0: endpoint { + remote-endpoint = <&dlct1_tpda_out>; + }; + }; + + port@4 { + reg = <4>; + + dlct1_funnel_in4: endpoint { + remote-endpoint = <&dlct2_funnel_out>; + }; + }; + + port@5 { + reg = <5>; + + dlct1_funnel_in5: endpoint { + remote-endpoint = <&ddr_funnel0_out>; + }; + }; + }; + + out-ports { + port { + dlct1_funnel_out: endpoint { + remote-endpoint = <&funnel1_in6>; + }; + }; + }; + }; + + tpdm@10c38000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10c38000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + dlct2_tpdm0_out: endpoint { + remote-endpoint = <&dlct2_tpda_in16>; + }; + }; + }; + }; + + tpdm@10c39000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10c39000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + dlct2_tpdm1_out: endpoint { + remote-endpoint = <&dlct2_tpda_in17>; + }; + }; + }; + }; + + tpda@10c3c000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10c3c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + dlct2_tpda_in4: endpoint { + remote-endpoint = <&mm_funnel_out>; + }; + }; + + port@f { + reg = <15>; + + dlct2_tpda_in15: endpoint { + remote-endpoint = <&mxa_tpdm_out>; + }; + }; + + port@10 { + reg = <16>; + + dlct2_tpda_in16: endpoint { + remote-endpoint = <&dlct2_tpdm0_out>; + }; + }; + + port@11 { + reg = <17>; + + dlct2_tpda_in17: endpoint { + remote-endpoint = <&dlct2_tpdm1_out>; + }; + }; + }; + + out-ports { + port { + dlct2_tpda_out: endpoint { + remote-endpoint = <&dlct2_funnel_in0>; + }; + }; + }; + }; + + funnel@10c3d000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10c3d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + dlct2_funnel_in0: endpoint { + remote-endpoint = <&dlct2_tpda_out>; + }; + }; + }; + + out-ports { + port { + dlct2_funnel_out: endpoint { + remote-endpoint = <&dlct1_funnel_in4>; + }; + }; + }; + }; + + tpdm@10cc1000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10cc1000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + status = "disabled"; + + out-ports { + port { + tmess_tpdm1_out: endpoint { + remote-endpoint = <&tmess_tpda_in2>; + }; + }; + }; + }; + + tpda@10cc4000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10cc4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + tmess_tpda_in2: endpoint { + remote-endpoint = <&tmess_tpdm1_out>; + }; + }; + }; + + out-ports { + port { + tmess_tpda_out: endpoint { + remote-endpoint = <&tmess_funnel_in0>; + }; + }; + }; + }; + + funnel@10cc5000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10cc5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmess_funnel_in0: endpoint { + remote-endpoint = <&tmess_tpda_out>; + }; + }; + }; + + out-ports { + port { + tmess_funnel_out: endpoint { + remote-endpoint = <&funnel1_in2>; + }; + }; + }; + }; + + funnel@10d04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10d04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + ddr_funnel0_in6: endpoint { + remote-endpoint = <&ddr_funnel1_out>; + }; + }; + }; + + out-ports { + port { + ddr_funnel0_out: endpoint { + remote-endpoint = <&dlct1_funnel_in5>; + }; + }; + }; + }; + + tpdm@10d08000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc0_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in0>; + }; + }; + }; + }; + + tpdm@10d09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc1_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in1>; + }; + }; + }; + }; + + tpdm@10d0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc2_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in2>; + }; + }; + }; + }; + + tpdm@10d0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc3_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in3>; + }; + }; + }; + }; + + tpdm@10d0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc4_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in4>; + }; + }; + }; + }; + + tpdm@10d0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc5_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in5>; + }; + }; + }; + }; + + tpdm@10d0e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d0e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc6_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in6>; + }; + }; + }; + }; + + tpdm@10d0f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10d0f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + llcc7_tpdm_out: endpoint { + remote-endpoint = <&llcc_tpda_in7>; + }; + }; + }; + }; + + tpda@10d12000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10d12000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + llcc_tpda_in0: endpoint { + remote-endpoint = <&llcc0_tpdm_out>; + }; + }; + + port@1 { + reg = <1>; + + llcc_tpda_in1: endpoint { + remote-endpoint = <&llcc1_tpdm_out>; + }; + }; + + port@2 { + reg = <2>; + + llcc_tpda_in2: endpoint { + remote-endpoint = <&llcc2_tpdm_out>; + }; + }; + + port@3 { + reg = <3>; + + llcc_tpda_in3: endpoint { + remote-endpoint = <&llcc3_tpdm_out>; + }; + }; + + port@4 { + reg = <4>; + + llcc_tpda_in4: endpoint { + remote-endpoint = <&llcc4_tpdm_out>; + }; + }; + + port@5 { + reg = <5>; + + llcc_tpda_in5: endpoint { + remote-endpoint = <&llcc5_tpdm_out>; + }; + }; + + port@6 { + reg = <6>; + + llcc_tpda_in6: endpoint { + remote-endpoint = <&llcc6_tpdm_out>; + }; + }; + + port@7 { + reg = <7>; + + llcc_tpda_in7: endpoint { + remote-endpoint = <&llcc7_tpdm_out>; + }; + }; + }; + + out-ports { + port { + llcc_tpda_out: endpoint { + remote-endpoint = <&ddr_funnel1_in0>; + }; + }; + }; + }; + + funnel@10d13000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10d13000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + ddr_funnel1_in0: endpoint { + remote-endpoint = <&llcc_tpda_out>; + }; + }; + }; + + out-ports { + port { + ddr_funnel1_out: endpoint { + remote-endpoint = <&ddr_funnel0_in6>; + }; + }; }; }; @@ -4902,12 +7929,14 @@ #iommu-cells = <2>; #global-interrupts = <1>; + + dma-coherent; }; intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ - <0 0x17080000 0 0x480000>; /* GICR * 12 */ + <0 0x17080000 0 0x300000>; /* GICR * 12 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; @@ -4927,8 +7956,6 @@ msi-controller; #msi-cells = <1>; - - status = "disabled"; }; }; @@ -4948,7 +7975,7 @@ <WAKE_TCS 2>, <CONTROL_TCS 0>; label = "apps_rsc"; - power-domains = <&SYSTEM_PD>; + power-domains = <&system_pd>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; @@ -5115,120 +8142,157 @@ }; }; - system-cache-controller@25000000 { - compatible = "qcom,x1e80100-llcc"; - reg = <0 0x25000000 0 0x200000>, - <0 0x25200000 0 0x200000>, - <0 0x25400000 0 0x200000>, - <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>, - <0 0x25a00000 0 0x200000>, - <0 0x25c00000 0 0x200000>, - <0 0x25e00000 0 0x200000>, - <0 0x26000000 0 0x200000>; - reg-names = "llcc0_base", - "llcc1_base", - "llcc2_base", - "llcc3_base", - "llcc4_base", - "llcc5_base", - "llcc6_base", - "llcc7_base", - "llcc_broadcast_base"; - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - }; + pmu@24091000 { + compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,x1e80100-adsp-pas"; - reg = <0 0x30000000 0 0x100>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + operating-points-v2 = <&llcc_bwmon_opp_table>; - power-domains = <&rpmhpd RPMHPD_LCX>, - <&rpmhpd RPMHPD_LMX>; - power-domain-names = "lcx", - "lmx"; + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; - interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + opp-0 { + opp-peak-kBps = <800000>; + }; - memory-region = <&adspslpi_mem>, - <&q6_adsp_dtb_mem>; + opp-1 { + opp-peak-kBps = <2188000>; + }; - qcom,qmp = <&aoss_qmp>; + opp-2 { + opp-peak-kBps = <3072000>; + }; - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; + opp-3 { + opp-peak-kBps = <6220800>; + }; - status = "disabled"; + opp-4 { + opp-peak-kBps = <6835200>; + }; - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; + opp-5 { + opp-peak-kBps = <8371200>; + }; - label = "lpass"; - qcom,remote-pid = <2>; + opp-6 { + opp-peak-kBps = <10944000>; + }; - gpr { - compatible = "qcom,gpr"; - qcom,glink-channels = "adsp_apps"; - qcom,domain = <GPR_DOMAIN_ID_ADSP>; - qcom,intents = <512 20>; - #address-cells = <1>; - #size-cells = <0>; + opp-7 { + opp-peak-kBps = <12748800>; + }; - q6apm: service@1 { - compatible = "qcom,q6apm"; - reg = <GPR_APM_MODULE_IID>; - #sound-dai-cells = <0>; - qcom,protection-domain = "avs/audio", - "msm/adsp/audio_pd"; + opp-8 { + opp-peak-kBps = <14745600>; + }; - q6apmbedai: bedais { - compatible = "qcom,q6apm-lpass-dais"; - #sound-dai-cells = <1>; - }; + opp-9 { + opp-peak-kBps = <16896000>; + }; + }; + }; - q6apmdai: dais { - compatible = "qcom,q6apm-dais"; - iommus = <&apps_smmu 0x1001 0x80>, - <&apps_smmu 0x1061 0x0>; - }; - }; + /* cluster0 */ + pmu@240b3400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b3400 0 0x600>; - q6prm: service@2 { - compatible = "qcom,q6prm"; - reg = <GPR_PRM_MODULE_IID>; - qcom,protection-domain = "avs/audio", - "msm/adsp/audio_pd"; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; - q6prmcc: clock-controller { - compatible = "qcom,q6prm-lpass-clocks"; - #clock-cells = <2>; - }; - }; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4800000>; + }; + + opp-1 { + opp-peak-kBps = <7464000>; + }; + + opp-2 { + opp-peak-kBps = <9600000>; + }; + + opp-3 { + opp-peak-kBps = <12896000>; + }; + + opp-4 { + opp-peak-kBps = <14928000>; + }; + + opp-5 { + opp-peak-kBps = <17064000>; }; }; }; + /* cluster2 */ + pmu@240b5400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b5400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + /* cluster1 */ + pmu@240b6400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b6400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + system-cache-controller@25000000 { + compatible = "qcom,x1e80100-llcc"; + reg = <0 0x25000000 0 0x200000>, + <0 0x25200000 0 0x200000>, + <0 0x25400000 0 0x200000>, + <0 0x25600000 0 0x200000>, + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>, + <0 0x25c00000 0 0x200000>, + <0 0x25e00000 0 0x200000>, + <0 0x26000000 0 0x200000>, + <0 0x26200000 0 0x200000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc6_base", + "llcc7_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,x1e80100-cdsp-pas"; - reg = <0 0x32300000 0 0x1400000>; + reg = <0x0 0x32300000 0x0 0x10000>; interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, @@ -5273,6 +8337,101 @@ label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x20>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x20>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0c07 0x20>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0c08 0x20>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x0c0c 0x20>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x0c0d 0x20>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0c0e 0x20>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0c0f 0x20>; + dma-coherent; + }; + }; }; }; }; @@ -5285,4 +8444,1158 @@ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-top-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-btm-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mem-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu1-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-top-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-btm-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu2-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss2-top-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss2-btm-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp2-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp3-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 9>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 10>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 11>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 12>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens3 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + thermal-sensors = <&tsens3 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; |