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Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779a0.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a779a0.dtsi439
1 files changed, 349 insertions, 90 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 41fbb9998cf8..4b101a6dc49d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -13,6 +13,7 @@
compatible = "renesas,r8a779a0";
#address-cells = <2>;
#size-cells = <2>;
+ interrupt-parent = <&gic>;
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
@@ -47,6 +48,7 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
+ bootph-all;
};
extalr_clk: extalr {
@@ -54,11 +56,12 @@
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
+ bootph-all;
};
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
- interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
/* External SCIF clock - to be overridden by boards that provide it */
@@ -70,7 +73,8 @@
soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ bootph-all;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -86,6 +90,16 @@
status = "disabled";
};
+ swdt: watchdog@e6030000 {
+ compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen4-wdt";
+ reg = <0 0xe6030000 0 0x0c>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_OSC>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 1128>;
+ status = "disabled";
+ };
+
pfc: pinctrl@e6050000 {
compatible = "renesas,pfc-r8a779a0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
@@ -93,6 +107,7 @@
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
<0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
<0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
+ bootph-all;
};
gpio0: gpio@e6058180 {
@@ -245,6 +260,14 @@
#interrupt-cells = <2>;
};
+ fuse: fuse@e6078800 {
+ compatible = "renesas,r8a779a0-efuse";
+ reg = <0 0xe6078800 0 0x100>;
+ clocks = <&cpg CPG_MOD 916>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ };
+
cmt0: timer@e60f0000 {
compatible = "renesas,r8a779a0-cmt0",
"renesas,rcar-gen4-cmt0";
@@ -323,11 +346,13 @@
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
+ bootph-all;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779a0-rst";
reg = <0 0xe6160000 0 0x4000>;
+ bootph-all;
};
sysc: system-controller@e6180000 {
@@ -370,6 +395,7 @@
interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -382,7 +408,9 @@
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -395,7 +423,9 @@
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -408,7 +438,9 @@
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -421,7 +453,9 @@
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -606,7 +640,8 @@
};
canfd: can@e6660000 {
- compatible = "renesas,r8a779a0-canfd";
+ compatible = "renesas,r8a779a0-canfd",
+ "renesas,rcar-gen4-canfd";
reg = <0 0xe6660000 0 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -657,7 +692,7 @@
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6800000 0 0x800>;
+ reg = <0 0xe6800000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
@@ -697,6 +732,7 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
+ iommus = <&ipmmu_ds1 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -705,7 +741,7 @@
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen4";
- reg = <0 0xe6810000 0 0x800>;
+ reg = <0 0xe6810000 0 0x1000>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
@@ -745,8 +781,7 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ iommus = <&ipmmu_ds1 1>;
status = "disabled";
};
@@ -793,8 +828,7 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ iommus = <&ipmmu_ds1 2>;
status = "disabled";
};
@@ -841,8 +875,7 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ iommus = <&ipmmu_ds1 3>;
status = "disabled";
};
@@ -889,8 +922,7 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ iommus = <&ipmmu_ds1 4>;
status = "disabled";
};
@@ -937,8 +969,57 @@
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ iommus = <&ipmmu_ds1 11>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@e6e30000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e30000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a779a0", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
status = "disabled";
};
@@ -1108,7 +1189,8 @@
};
vin00: video@e6ef0000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 730>;
@@ -1136,7 +1218,8 @@
};
vin01: video@e6ef1000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 731>;
@@ -1164,7 +1247,8 @@
};
vin02: video@e6ef2000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 800>;
@@ -1192,7 +1276,8 @@
};
vin03: video@e6ef3000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 801>;
@@ -1220,7 +1305,8 @@
};
vin04: video@e6ef4000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef4000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 802>;
@@ -1248,7 +1334,8 @@
};
vin05: video@e6ef5000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef5000 0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 803>;
@@ -1276,7 +1363,8 @@
};
vin06: video@e6ef6000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef6000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 804>;
@@ -1304,7 +1392,8 @@
};
vin07: video@e6ef7000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef7000 0 0x1000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 805>;
@@ -1332,7 +1421,8 @@
};
vin08: video@e6ef8000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef8000 0 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 806>;
@@ -1360,7 +1450,8 @@
};
vin09: video@e6ef9000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ef9000 0 0x1000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 807>;
@@ -1388,7 +1479,8 @@
};
vin10: video@e6efa000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6efa000 0 0x1000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 808>;
@@ -1416,7 +1508,8 @@
};
vin11: video@e6efb000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6efb000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
@@ -1444,7 +1537,8 @@
};
vin12: video@e6efc000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6efc000 0 0x1000>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
@@ -1472,7 +1566,8 @@
};
vin13: video@e6efd000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6efd000 0 0x1000>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
@@ -1500,7 +1595,8 @@
};
vin14: video@e6efe000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6efe000 0 0x1000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
@@ -1528,7 +1624,8 @@
};
vin15: video@e6eff000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6eff000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 813>;
@@ -1556,7 +1653,8 @@
};
vin16: video@e6ed0000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed0000 0 0x1000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 814>;
@@ -1584,7 +1682,8 @@
};
vin17: video@e6ed1000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed1000 0 0x1000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
@@ -1612,7 +1711,8 @@
};
vin18: video@e6ed2000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed2000 0 0x1000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 816>;
@@ -1640,7 +1740,8 @@
};
vin19: video@e6ed3000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed3000 0 0x1000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 817>;
@@ -1668,7 +1769,8 @@
};
vin20: video@e6ed4000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed4000 0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 818>;
@@ -1696,7 +1798,8 @@
};
vin21: video@e6ed5000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed5000 0 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 819>;
@@ -1724,7 +1827,8 @@
};
vin22: video@e6ed6000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed6000 0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 820>;
@@ -1752,7 +1856,8 @@
};
vin23: video@e6ed7000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed7000 0 0x1000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 821>;
@@ -1780,7 +1885,8 @@
};
vin24: video@e6ed8000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed8000 0 0x1000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 822>;
@@ -1808,7 +1914,8 @@
};
vin25: video@e6ed9000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ed9000 0 0x1000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 823>;
@@ -1836,7 +1943,8 @@
};
vin26: video@e6eda000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6eda000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 824>;
@@ -1864,7 +1972,8 @@
};
vin27: video@e6edb000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6edb000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 825>;
@@ -1892,7 +2001,8 @@
};
vin28: video@e6edc000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6edc000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 826>;
@@ -1920,7 +2030,8 @@
};
vin29: video@e6edd000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6edd000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 827>;
@@ -1948,7 +2059,8 @@
};
vin30: video@e6ede000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6ede000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 828>;
@@ -1976,7 +2088,8 @@
};
vin31: video@e6edf000 {
- compatible = "renesas,vin-r8a779a0";
+ compatible = "renesas,vin-r8a779a0",
+ "renesas,rcar-gen4-vin";
reg = <0 0xe6edf000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 829>;
@@ -2036,6 +2149,14 @@
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
+ iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
+ <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
+ <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
+ <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
+ <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
+ <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
+ <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
+ <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
};
dmac2: dma-controller@e7351000 {
@@ -2061,6 +2182,10 @@
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <8>;
+ iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
+ <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
+ <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
+ <&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
};
mmc0: mmc@ee140000 {
@@ -2097,7 +2222,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2106,7 +2231,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 19>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2115,7 +2240,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2124,7 +2249,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 1>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2133,7 +2258,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_A3IR>;
#iommu-cells = <1>;
};
@@ -2142,7 +2267,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2151,7 +2276,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2160,7 +2285,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 15>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2169,7 +2294,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 6>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2178,7 +2303,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 5>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2187,7 +2312,7 @@
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef40000 0 0x20000>;
- renesas,ipmmu-main = <&ipmmu_mm 11>;
+ renesas,ipmmu-main = <&ipmmu_mm>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -2209,8 +2334,24 @@
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpu: gpu@fd000000 {
+ compatible = "renesas,r8a779a0-gpu",
+ "img,img-ge7800",
+ "img,img-rogue";
+ reg = <0 0xfd000000 0 0x40000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
+ <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
+ <&cpg CPG_MOD 0>;
+ clock-names = "core", "mem", "sys";
+ power-domains = <&sysc R8A779A0_PD_3DG_A>,
+ <&sysc R8A779A0_PD_3DG_B>;
+ power-domain-names = "a", "b";
+ resets = <&cpg 0>;
+ status = "disabled";
};
fcpvd0: fcp@fea10000 {
@@ -2219,6 +2360,7 @@
clocks = <&cpg CPG_MOD 508>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 508>;
+ iommus = <&ipmmu_vi1 6>;
};
fcpvd1: fcp@fea11000 {
@@ -2227,6 +2369,43 @@
clocks = <&cpg CPG_MOD 509>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 509>;
+ iommus = <&ipmmu_vi1 7>;
+ };
+
+ fcpvx0: fcp@fedb0000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfedb0000 0 0x200>;
+ clocks = <&cpg CPG_MOD 1100>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP01>;
+ resets = <&cpg 1100>;
+ iommus = <&ipmmu_vi1 24>;
+ };
+
+ fcpvx1: fcp@fedb8000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfedb8000 0 0x200>;
+ clocks = <&cpg CPG_MOD 1101>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP01>;
+ resets = <&cpg 1101>;
+ iommus = <&ipmmu_vi1 25>;
+ };
+
+ fcpvx2: fcp@fedc0000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfedc0000 0 0x200>;
+ clocks = <&cpg CPG_MOD 1102>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP23>;
+ resets = <&cpg 1102>;
+ iommus = <&ipmmu_vi1 26>;
+ };
+
+ fcpvx3: fcp@fedc8000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfedc8000 0 0x200>;
+ clocks = <&cpg CPG_MOD 1103>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP23>;
+ resets = <&cpg 1103>;
+ iommus = <&ipmmu_vi1 27>;
};
vspd0: vsp@fea20000 {
@@ -2251,6 +2430,50 @@
renesas,fcp = <&fcpvd1>;
};
+ vspx0: vsp@fedd0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfedd0000 0 0x8000>;
+ interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1028>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP01>;
+ resets = <&cpg 1028>;
+
+ renesas,fcp = <&fcpvx0>;
+ };
+
+ vspx1: vsp@fedd8000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfedd8000 0 0x8000>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1029>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP01>;
+ resets = <&cpg 1029>;
+
+ renesas,fcp = <&fcpvx1>;
+ };
+
+ vspx2: vsp@fede0000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfede0000 0 0x8000>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1030>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP23>;
+ resets = <&cpg 1030>;
+
+ renesas,fcp = <&fcpvx2>;
+ };
+
+ vspx3: vsp@fede8000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfede8000 0 0x8000>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1031>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP23>;
+ resets = <&cpg 1031>;
+
+ renesas,fcp = <&fcpvx3>;
+ };
+
csi40: csi2@feaa0000 {
compatible = "renesas,r8a779a0-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
@@ -2390,14 +2613,22 @@
};
isp0: isp@fed00000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed00000 0 0x10000>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 612>;
+ compatible = "renesas,r8a779a0-isp",
+ "renesas,rcar-gen4-isp";
+ reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>;
+ reg-names = "cs", "core";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cs", "core";
+ clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>;
+ clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
- resets = <&cpg 612>;
+ resets = <&cpg 612>, <&cpg 16>;
+ reset-names = "cs", "core";
status = "disabled";
+ renesas,vspx = <&vspx0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2473,14 +2704,22 @@
};
isp1: isp@fed20000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed20000 0 0x10000>;
- interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 613>;
+ compatible = "renesas,r8a779a0-isp",
+ "renesas,rcar-gen4-isp";
+ reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>;
+ reg-names = "cs", "core";
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cs", "core";
+ clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>;
+ clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP01>;
- resets = <&cpg 613>;
+ resets = <&cpg 613>, <&cpg 17>;
+ reset-names = "cs", "core";
status = "disabled";
+ renesas,vspx = <&vspx1>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2556,14 +2795,22 @@
};
isp2: isp@fed30000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed30000 0 0x10000>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 614>;
+ compatible = "renesas,r8a779a0-isp",
+ "renesas,rcar-gen4-isp";
+ reg = <0 0xfed30000 0 0x10000>, <0 0xfef00000 0 0x100000>;
+ reg-names = "cs", "core";
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cs", "core";
+ clocks = <&cpg CPG_MOD 614>, <&cpg CPG_MOD 18>;
+ clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
- resets = <&cpg 614>;
+ resets = <&cpg 614>, <&cpg 18>;
+ reset-names = "cs", "core";
status = "disabled";
+ renesas,vspx = <&vspx2>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2639,14 +2886,22 @@
};
isp3: isp@fed40000 {
- compatible = "renesas,r8a779a0-isp";
- reg = <0 0xfed40000 0 0x10000>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 615>;
+ compatible = "renesas,r8a779a0-isp",
+ "renesas,rcar-gen4-isp";
+ reg = <0 0xfed40000 0 0x10000>, <0 0xfe400000 0 0x100000>;
+ reg-names = "cs", "core";
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cs", "core";
+ clocks = <&cpg CPG_MOD 615>, <&cpg CPG_MOD 19>;
+ clock-names = "cs", "core";
power-domains = <&sysc R8A779A0_PD_A3ISP23>;
- resets = <&cpg 615>;
+ resets = <&cpg 615>, <&cpg 19>;
+ reset-names = "cs", "core";
status = "disabled";
+ renesas,vspx = <&vspx3>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2721,7 +2976,7 @@
};
};
- dsi0: dsi-encoder@fed80000 {
+ dsi0: dsi@fed80000 {
compatible = "renesas,r8a779a0-dsi-csi2-tx";
reg = <0 0xfed80000 0 0x10000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -2749,7 +3004,7 @@
};
};
- dsi1: dsi-encoder@fed90000 {
+ dsi1: dsi@fed90000 {
compatible = "renesas,r8a779a0-dsi-csi2-tx";
reg = <0 0xfed90000 0 0x10000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -2780,6 +3035,7 @@
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
+ bootph-all;
};
};
@@ -2857,9 +3113,12 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
+ "hyp-virt";
};
};
generated by cgit (git 2.34.1) at 2025-12-29 20:58:20 +0000