diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r9a09g011.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 47 |
1 files changed, 38 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 46d67b200a66..42462c138dd2 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -12,6 +12,7 @@ compatible = "renesas,r9a09g011"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ extal_clk: extal { @@ -50,7 +51,6 @@ soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -71,7 +71,7 @@ sdhi0: mmc@85000000 { compatible = "renesas,sdhi-r9a09g011", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x85000000 0 0x2000>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; @@ -87,7 +87,7 @@ sdhi1: mmc@85010000 { compatible = "renesas,sdhi-r9a09g011", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x85010000 0 0x2000>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; @@ -103,7 +103,7 @@ emmc: mmc@85020000 { compatible = "renesas,sdhi-r9a09g011", - "renesas,rcar-gen3-sdhi"; + "renesas,rzg2l-sdhi"; reg = <0x0 0x85020000 0 0x2000>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; @@ -163,7 +163,7 @@ }; avb: ethernet@a3300000 { - compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; + compatible = "renesas,etheravb-r9a09g011", "renesas,etheravb-rzv2m"; reg = <0 0xa3300000 0 0x800>; interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ @@ -236,6 +236,34 @@ reg = <0 0xa3f03000 0 0x400>; }; + csi0: spi@a4020000 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020000 0 0x80>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPG_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + csi4: spi@a4020200 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020200 0 0x80>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@a4030000 { #address-cells = <1>; #size-cells = <0>; @@ -340,9 +368,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; |