diff options
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 153 |
1 files changed, 152 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..6b0bb2c441af 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,10 +12,17 @@ / { aliases { i2c0 = &i2c0; - serial0 = &scif0; + serial0 = &scif1; + serial1 = &scif3; + serial3 = &scif0; mmc1 = &sdhi1; }; + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + keys { compatible = "gpio-keys"; @@ -44,6 +51,23 @@ }; }; + snd_rzg3s: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,mclk-fs = <256>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&da7212>; + clocks = <&versa3 1>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -64,13 +88,83 @@ }; }; +&audio_clk2 { + clock-frequency = <12288000>; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <1000000>; + + da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + + clocks = <&versa3 1>; + clock-names = "mclk"; + + #sound-dai-cells = <0>; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDSP-supply = <®_3p3v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_1p8v>; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + power-monitor@44 { + compatible = "renesas,isl28022"; + reg = <0x44>; + shunt-resistor-micro-ohms = <8000>; + renesas,average-samples = <32>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&phyrst { + status = "okay"; }; &pinctrl { + audio_clock_pins: audio-clock { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + key-1-gpio-hog { gpio-hog; gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>; @@ -97,6 +191,11 @@ <RZG2L_PORT_PINMUX(6, 4, 1)>; /* TXD */ }; + scif3_pins: scif3 { + pinmux = <RZG2L_PORT_PINMUX(17, 2, 7)>, /* RXD */ + <RZG2L_PORT_PINMUX(17, 3, 7)>; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -128,6 +227,30 @@ pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */ }; }; + + ssi3_pins: ssi3 { + pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */ + <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */ + <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */ + <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */ + }; + + usb0_pins: usb0 { + peri { + pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */ + <RZG2L_PORT_PINMUX(5, 2, 1)>; /* OVC */ + }; + + otg { + pinmux = <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */ + <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */ + }; }; &scif0 { @@ -136,6 +259,12 @@ status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; @@ -148,3 +277,25 @@ max-frequency = <125000000>; status = "okay"; }; + +&ssi3 { + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, + <&versa3 2>, <&audio_clk2>; + pinctrl-names = "default"; + pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>; + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; |