diff options
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 9137dd76e72c..6d457da6fa03 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -351,8 +351,6 @@ pmugrf: syscon@ff010000 { compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff010000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; pmu_io_domains: io-domains { compatible = "rockchip,px30-pmu-io-voltage-domain"; @@ -453,8 +451,6 @@ grf: syscon@ff140000 { compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; reg = <0x0 0xff140000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; io_domains: io-domains { compatible = "rockchip,px30-io-voltage-domain"; @@ -985,6 +981,12 @@ resets = <&cru SRST_GMAC_A>; reset-names = "stmmaceth"; status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; }; sdmmc: mmc@ff370000 { @@ -1131,8 +1133,6 @@ resets = <&cru SRST_MIPIDSI_HOST_P>; reset-names = "apb"; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; ports { @@ -1241,6 +1241,18 @@ status = "disabled"; }; + cif: video-capture@ff490000 { + compatible = "rockchip,px30-vip"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>; + clock-names = "aclk", "hclk", "pclk"; + power-domains = <&power PX30_PD_VI>; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "axi", "ahb", "pclkin"; + status = "disabled"; + }; + isp: isp@ff4a0000 { compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ reg = <0x0 0xff4a0000 0x0 0x8000>; @@ -1263,10 +1275,8 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + isp_in: port@0 { reg = <0>; - #address-cells = <1>; - #size-cells = <0>; }; }; }; |