diff options
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3576.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1205 |
1 files changed, 1110 insertions, 95 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 436232ffe4d1..a86fc6b4e8c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/power/rockchip,rk3576-power.h> #include <dt-bindings/reset/rockchip,rk3576-cru.h> #include <dt-bindings/soc/rockchip,boot-mode.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "rockchip,rk3576"; @@ -111,11 +112,11 @@ reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <120>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l1: cpu@1 { @@ -124,9 +125,10 @@ reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l2: cpu@2 { @@ -135,9 +137,10 @@ reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l3: cpu@3 { @@ -146,9 +149,10 @@ reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b0: cpu@100 { @@ -157,11 +161,11 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <320>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b1: cpu@101 { @@ -170,9 +174,10 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b2: cpu@102 { @@ -181,9 +186,10 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b3: cpu@103 { @@ -192,9 +198,10 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; idle-states { @@ -269,12 +276,6 @@ opp-microvolt = <900000 900000 950000>; clock-latency-ns = <40000>; }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; cluster1_opp_table: opp-table-cluster1 { @@ -341,12 +342,6 @@ opp-microvolt = <925000 925000 950000>; clock-latency-ns = <40000>; }; - - opp-2304000000 { - opp-hz = /bits/ 64 <2304000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; gpu_opp_table: opp-table-gpu { @@ -393,6 +388,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -408,6 +408,90 @@ }; }; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai6>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3576-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@27320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x27320000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2ae10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2ae20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2ae30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae30000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@2ae40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0x2ae40000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + pmu_a53: pmu-a53 { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -431,6 +515,143 @@ method = "smc"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, @@ -445,6 +666,166 @@ #size-cells = <2>; ranges; + pcie0: pcie@22000000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22000000 0x0 0x00400000>, + <0x0 0x2a200000 0x0 0x00010000>, + <0x0 0x20000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>, + <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>, + <&cru CLK_PCIE0_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_PHP>; + ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000 + 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000 + 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie1: pcie@22400000 { + compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie"; + reg = <0x0 0x22400000 0x0 0x00400000>, + <0x0 0x2a210000 0x0 0x00010000>, + <0x0 0x21000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>, + <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>, + <&cru CLK_PCIE1_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <2>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + num-lanes = <1>; + phys = <&combphy1_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3576_PD_SUBPHP>; + ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000 + 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000 + 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>; + }; + }; + + usb_drd0_dwc3: usb@23000000 { + compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; + reg = <0x0 0x23000000 0x0 0x400000>; + clocks = <&cru CLK_REF_USB3OTG0>, + <&cru CLK_SUSPEND_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + + usb_drd1_dwc3: usb@23400000 { + compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; + reg = <0x0 0x23400000 0x0 0x400000>; + clocks = <&cru CLK_REF_USB3OTG1>, + <&cru CLK_SUSPEND_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_PHP>; + resets = <&cru SRST_A_USB3OTG1>; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + dma-coherent; + status = "disabled"; + }; + sys_grf: syscon@2600a000 { compatible = "rockchip,rk3576-sys-grf", "syscon"; reg = <0x0 0x2600a000 0x0 0x2000>; @@ -515,6 +896,76 @@ reg = <0x0 0x2602c000 0x0 0x2000>; }; + usb2phy_grf: syscon@2602e000 { + compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0x2602e000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3576-usb2phy"; + reg = <0x0 0x10>; + resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_PHY_REF_SRC>, + <&cru ACLK_MMU2>, + <&cru ACLK_SLV_MMU2>; + clock-names = "phyclk", "aclk", "aclk_slv"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", "linestate"; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@2000 { + compatible = "rockchip,rk3576-usb2phy"; + reg = <0x2000 0x10>; + resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_PHY_REF_SRC>, + <&cru ACLK_MMU1>, + <&cru ACLK_SLV_MMU1>; + clock-names = "phyclk", "aclk", "aclk_slv"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", "linestate"; + status = "disabled"; + }; + }; + }; + + hdptxphy_grf: syscon@26032000 { + compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; + reg = <0x0 0x26032000 0x0 0x100>; + }; + + mipidcphy_grf: syscon@26034000 { + compatible = "rockchip,rk3576-dcphy-grf", "syscon"; + reg = <0x0 0x26034000 0x0 0x2000>; + clocks = <&cru PCLK_PMUPHY_ROOT>; + }; + + vo1_grf: syscon@26036000 { + compatible = "rockchip,rk3576-vo1-grf", "syscon"; + reg = <0x0 0x26036000 0x0 0x100>; + clocks = <&cru PCLK_VO1_ROOT>; + }; + sdgmac_grf: syscon@26038000 { compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; reg = <0x0 0x26038000 0x0 0x1000>; @@ -811,7 +1262,7 @@ gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; reg = <0x0 0x27800000 0x0 0x200000>; - assigned-clocks = <&scmi_clk CLK_GPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; clock-names = "core"; @@ -826,6 +1277,226 @@ status = "disabled"; }; + vop: vop@27d00000 { + compatible = "rockchip,rk3576-vop"; + reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", + "vp0", + "vp1", + "vp2"; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VP0>, + <&cru DCLK_VP1>, + <&cru DCLK_VP2>, + <&hdptxphy>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "pll_hdmiphy0"; + iommus = <&vop_mmu>; + power-domains = <&power RK3576_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; + }; + + vop_mmu: iommu@27d07e00 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3576_PD_VOP>; + status = "disabled"; + }; + + sai5: sai@27d40000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27d40000 0x0 0x1000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 3>; + dma-names = "rx"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>; + reset-names = "m", "h"; + rockchip,sai-rx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI5"; + status = "disabled"; + }; + + sai6: sai@27d50000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27d50000 0x0 0x1000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 4>, <&dmac2 5>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>; + reset-names = "m", "h"; + rockchip,sai-rx-route = <0 1 2 3>; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI6"; + status = "disabled"; + }; + + dsi: dsi@27d80000 { + compatible = "rockchip,rk3576-mipi-dsi2"; + reg = <0x0 0x27d80000 0x0 0x10000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + phys = <&mipidcphy PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + }; + + dsi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi: hdmi@27da0000 { + compatible = "rockchip,rk3576-dw-hdmi-qp"; + reg = <0x0 0x27da0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_SAI6_8CH>, + <&cru CLK_HDMITXHDP>, + <&cru HCLK_VO0_ROOT>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; + reset-names = "ref", "hdp"; + rockchip,grf = <&ioc_grf>; + rockchip,vo-grf = <&vo0_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + sai7: sai@27ed0000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27ed0000 0x0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 19>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>; + reset-names = "m", "h"; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI7"; + status = "disabled"; + }; + + sai8: sai@27ee0000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27ee0000 0x0 0x1000>; + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 7>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>; + reset-names = "m", "h"; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI8"; + status = "disabled"; + }; + + sai9: sai@27ef0000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x27ef0000 0x0 0x1000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 26>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>; + reset-names = "m", "h"; + rockchip,sai-tx-route = <0 1 2 3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI9"; + status = "disabled"; + }; + qos_hdcp1: qos@27f02000 { compatible = "rockchip,rk3576-qos", "syscon"; reg = <0x0 0x27f02000 0x0 0x20>; @@ -1110,6 +1781,72 @@ }; }; + sata0: sata@2a240000 { + compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; + reg = <0x0 0x2a240000 0x0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_SUBPHP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + dma-coherent; + status = "disabled"; + }; + + sata1: sata@2a250000 { + compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci"; + reg = <0x0 0x2a250000 0x0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_SUBPHP>; + phys = <&combphy1_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + dma-coherent; + status = "disabled"; + }; + + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + assigned-clocks = <&cru CLK_REF_OSC_MPHY>; + assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_USB>; + pinctrl-0 = <&ufs_refclk>; + pinctrl-names = "default"; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + sfc1: spi@2a300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a300000 0x0 0x4000>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + power-domains = <&power RK3576_PD_SDGMAC>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@2a310000 { compatible = "rockchip,rk3576-dw-mshc"; reg = <0x0 0x2a310000 0x0 0x4000>; @@ -1126,6 +1863,22 @@ status = "disabled"; }; + sdio: mmc@2a320000 { + compatible = "rockchip,rk3576-dw-mshc"; + reg = <0x0 0x2a320000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <200000000>; + pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; + pinctrl-names = "default"; + power-domains = <&power RK3576_PD_SDGMAC>; + resets = <&cru SRST_H_SDIO>; + reset-names = "reset"; + status = "disabled"; + }; + sdhci: mmc@2a330000 { compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; reg = <0x0 0x2a330000 0x0 0x10000>; @@ -1149,6 +1902,203 @@ status = "disabled"; }; + sfc0: spi@2a340000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a340000 0x0 0x4000>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + power-domains = <&power RK3576_PD_NVM>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rng: rng@2a410000 { + compatible = "rockchip,rk3576-rng"; + reg = <0x0 0x2a410000 0x0 0x200>; + clocks = <&cru HCLK_TRNG_NS>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cru SRST_H_TRNG_NS>; + }; + + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names = "otp", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpub_leakage: cpub-leakage@1e { + reg = <0x1e 0x1>; + }; + cpul_leakage: cpul-leakage@1f { + reg = <0x1f 0x1>; + }; + npu_leakage: npu-leakage@20 { + reg = <0x20 0x1>; + }; + gpu_leakage: gpu-leakage@21 { + reg = <0x21 0x1>; + }; + log_leakage: log-leakage@22 { + reg = <0x22 0x1>; + }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; + }; + + sai0: sai@2a600000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a600000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai0m0_lrck + &sai0m0_sclk + &sai0m0_sdi0 + &sai0m0_sdi1 + &sai0m0_sdi2 + &sai0m0_sdi3 + &sai0m0_sdo0 + &sai0m0_sdo1 + &sai0m0_sdo2 + &sai0m0_sdo3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI0"; + status = "disabled"; + }; + + sai1: sai@2a610000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a610000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0 + &sai1m0_sdo1 + &sai1m0_sdo2 + &sai1m0_sdo3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI1"; + status = "disabled"; + }; + + sai2: sai@2a620000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a620000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai2m0_lrck + &sai2m0_sclk + &sai2m0_sdi + &sai2m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI2"; + status = "disabled"; + }; + + sai3: sai@2a630000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a630000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai3m0_lrck + &sai3m0_sclk + &sai3m0_sdi + &sai3m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI3"; + status = "disabled"; + }; + + sai4: sai@2a640000 { + compatible = "rockchip,rk3576-sai"; + reg = <0x0 0x2a640000 0x0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 0>, <&dmac2 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3576_PD_AUDIO>; + resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&sai4m0_lrck + &sai4m0_sclk + &sai4m0_sdi + &sai4m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI4"; + status = "disabled"; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, @@ -1260,7 +2210,6 @@ status = "disabled"; }; - i2c6: i2c@2ac90000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ac90000 0x0 0x1000>; @@ -1314,7 +2263,6 @@ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; clock-names = "tclk", "pclk"; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; }; spi0: spi@2acf0000 { @@ -1544,6 +2492,55 @@ status = "disabled"; }; + tsadc: tsadc@2ae70000 { + compatible = "rockchip,rk3576-tsadc"; + reg = <0x0 0x2ae70000 0x0 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + sensor@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + }; + i2c9: i2c@2ae80000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ae80000 0x0 0x1000>; @@ -1552,8 +2549,6 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&i2c9m0_xfer>; - resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; - reset-names = "i2c", "apb"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1587,6 +2582,94 @@ status = "disabled"; }; + mipidcphy: phy@2b020000 { + compatible = "rockchip,rk3576-mipi-dcphy"; + reg = <0x0 0x2b020000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY>, + <&cru CLK_PHY_REF_SRC>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY>, + <&cru SRST_P_MIPI_DCPHY>, + <&cru SRST_P_DCPHY_GRF>, + <&cru SRST_S_MIPI_DCPHY>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy_grf>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy0_ps: phy@2b050000 { + compatible = "rockchip,rk3576-naneng-combphy"; + reg = <0x0 0x2b050000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PCIE0_PHY>, + <&cru PCLK_PCIE2_COMBOPHY0>, + <&cru PCLK_PCIE0>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PCIE0_PIPE_PHY>, + <&cru SRST_P_PCIE2_COMBOPHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy1_psu: phy@2b060000 { + compatible = "rockchip,rk3576-naneng-combphy"; + reg = <0x0 0x2b060000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PCIE1_PHY>, + <&cru PCLK_PCIE2_COMBOPHY1>, + <&cru PCLK_PCIE1>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PCIE1_PIPE_PHY>, + <&cru SRST_P_PCIE2_COMBOPHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + usbdp_phy: phy@2b010000 { + compatible = "rockchip,rk3576-usbdp-phy"; + reg = <0x0 0x2b010000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_PHY_REF_SRC >, + <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, + <&cru PCLK_USBDPPHY>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, + <&cru SRST_USBDP_COMBO_PHY_CMN>, + <&cru SRST_USBDP_COMBO_PHY_LANE>, + <&cru SRST_USBDP_COMBO_PHY_PCS>, + <&cru SRST_P_USBDPPHY>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy_grf>; + rockchip,vo-grf = <&vo1_grf>; + status = "disabled"; + }; + + hdptxphy: hdmiphy@2b000000 { + compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0x2b000000 0x0 0x2000>; + clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; + clock-names = "ref", "apb"; + #clock-cells = <0>; + resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, + <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + sram: sram@3ff88000 { compatible = "mmio-sram"; reg = <0x0 0x3ff88000 0x0 0x78000>; @@ -1604,74 +2687,6 @@ compatible = "arm,scmi-shmem"; reg = <0x0 0x4010f000 0x0 0x100>; }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3576-pinctrl"; - rockchip,grf = <&ioc_grf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@27320000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x27320000 0x0 0x200>; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@2ae10000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae10000 0x0 0x200>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2ae20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae20000 0x0 0x200>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@2ae30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae30000 0x0 0x200>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@2ae40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0x2ae40000 0x0 0x200>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; }; }; |