diff options
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 140 |
1 files changed, 116 insertions, 24 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 963e880ccc12..08920344a4b8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -4,13 +4,34 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/soc/rockchip,vop2.h> / { chosen { stdout-path = "serial2:1500000n8"; }; - vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + + vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { compatible = "regulator-fixed"; regulator-name = "vcc3v3_pcie2x1l0"; regulator-min-microvolt = <3300000>; @@ -19,33 +40,33 @@ vin-supply = <&vcc_3v3_s3>; }; - vcc3v3_pcie3x2: vcc3v3-pcie3x2-regulator { + vcc3v3_bkey: regulator-vcc3v3-bkey { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */ pinctrl-names = "default"; - pinctrl-0 = <&pcie3x2_vcc3v3_en>; - regulator-name = "vcc3v3_pcie3x2"; + pinctrl-0 = <&pcie_4g_pwen>; + regulator-name = "vcc3v3_bkey"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; vin-supply = <&vcc5v0_sys>; }; - vcc3v3_pcie3x4: vcc3v3-pcie3x4-regulator { + vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */ pinctrl-names = "default"; - pinctrl-0 = <&pcie3x4_vcc3v3_en>; - regulator-name = "vcc3v3_pcie3x4"; + pinctrl-0 = <&pcie30x4_pwren_h>; + regulator-name = "vcc3v3_pcie30"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <5000>; vin-supply = <&vcc5v0_sys>; }; - vcc5v0_host: vcc5v0-host-regulator { + vcc5v0_host: regulator-vcc5v0-host { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; @@ -68,6 +89,30 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -94,24 +139,52 @@ }; &pcie30phy { + data-lanes = <1 1 2 2>; + /* separate clock lines from the clock generator to phy and devices */ + rockchip,rx-common-refclk-mode = <0 0 0 0>; status = "okay"; }; -/* B-Key and E-Key */ +/* M-Key */ &pcie3x2 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>, + <&pcie30_port1_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + num-lanes = <2>; pinctrl-names = "default"; - pinctrl-0 = <&pcie3x2_rst>; - reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ - vpcie3v3-supply = <&vcc3v3_pcie3x2>; + pinctrl-0 = <&pcie30x2_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; }; -/* M-Key */ +/* B-Key and E-Key */ &pcie3x4 { + /* + * The board has a "pcie_refclk" oscillator that needs enabling, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; pinctrl-names = "default"; - pinctrl-0 = <&pcie3x4_rst>; - reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ - vpcie3v3-supply = <&vcc3v3_pcie3x4>; + pinctrl-0 = <&pcie30x4_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_bkey>; status = "okay"; }; @@ -123,20 +196,20 @@ }; pcie3 { - pcie3x2_rst: pcie3x2-rst { - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; - pcie3x2_vcc3v3_en: pcie3x2-vcc3v3-en { - rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + pcie_4g_pwen: pcie-4g-pwen { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; }; - pcie3x4_rst: pcie3x4-rst { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; }; - pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en { - rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + pcie30x4_pwren_h: pcie30x4-pwren-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; }; }; @@ -230,3 +303,22 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = <ROCKCHIP_VOP2_EP_HDMI1>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; |