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Diffstat (limited to 'arch/arm64/boot/dts/sprd/sc9860.dtsi')
-rw-r--r--arch/arm64/boot/dts/sprd/sc9860.dtsi328
1 files changed, 192 insertions, 136 deletions
diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
index 7b7d8cedacda..864ef0a17425 100644
--- a/arch/arm64/boot/dts/sprd/sc9860.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
@@ -1,12 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Spreadtrum SC9860 SoC
*
* Copyright (C) 2016, Spreadtrum Communications Inc.
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
#include "whale2.dtsi"
/ {
@@ -48,7 +49,7 @@
CPU0: cpu@530000 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530000>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -56,7 +57,7 @@
CPU1: cpu@530001 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530001>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -64,7 +65,7 @@
CPU2: cpu@530002 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530002>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -72,7 +73,7 @@
CPU3: cpu@530003 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530003>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -80,7 +81,7 @@
CPU4: cpu@530100 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530100>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -88,7 +89,7 @@
CPU5: cpu@530101 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530101>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -96,7 +97,7 @@
CPU6: cpu@530102 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530102>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
@@ -104,15 +105,15 @@
CPU7: cpu@530103 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x530103>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
};
};
- idle-states{
- entry-method = "arm,psci";
+ idle-states {
+ entry-method = "psci";
CORE_PD: core_pd {
compatible = "arm,idle-state";
@@ -133,18 +134,6 @@
};
};
- gic: interrupt-controller@12001000 {
- compatible = "arm,gic-400";
- reg = <0 0x12001000 0 0x1000>,
- <0 0x12002000 0 0x2000>,
- <0 0x12004000 0 0x2000>,
- <0 0x12006000 0 0x2000>;
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
- | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
psci {
compatible = "arm,psci-0.2";
method = "smc";
@@ -163,7 +152,7 @@
};
pmu {
- compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
+ compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
@@ -183,36 +172,99 @@
};
soc {
+ gic: interrupt-controller@12001000 {
+ compatible = "arm,gic-400";
+ reg = <0 0x12001000 0 0x1000>,
+ <0 0x12002000 0 0x2000>,
+ <0 0x12004000 0 0x2000>,
+ <0 0x12006000 0 0x2000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
+ | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ ap_clk: clock-controller@20000000 {
+ compatible = "sprd,sc9860-ap-clk";
+ reg = <0 0x20000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>,
+ <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+
+ aon_prediv: aon-prediv@402d0000 {
+ compatible = "sprd,sc9860-aon-prediv";
+ reg = <0 0x402d0000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>,
+ <&pmu_gate 0>;
+ #clock-cells = <1>;
+ };
+
+
+ aonsecure_clk: clock-controller@40880000 {
+ compatible = "sprd,sc9860-aonsecure-clk";
+ reg = <0 0x40880000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ gpu_clk: clock-controller@60200000 {
+ compatible = "sprd,sc9860-gpu-clk";
+ reg = <0 0x60200000 0 0x400>;
+ clocks = <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ vsp_clk: clock-controller@61000000 {
+ compatible = "sprd,sc9860-vsp-clk";
+ reg = <0 0x61000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ cam_clk: clock-controller@62000000 {
+ compatible = "sprd,sc9860-cam-clk";
+ reg = <0 0x62000000 0 0x4000>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
+ disp_clk: clock-controller@63000000 {
+ compatible = "sprd,sc9860-disp-clk";
+ reg = <0 0x63000000 0 0x400>;
+ clocks = <&ext_26m>, <&pll 0>;
+ #clock-cells = <1>;
+ };
+
funnel@10001000 { /* SoC Funnel */
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x10001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
soc_funnel_out_port: endpoint {
remote-endpoint = <&etb_in>;
};
};
+ };
- port@1 {
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
soc_funnel_in_port0: endpoint {
- slave-mode;
remote-endpoint =
<&main_funnel_out_port>;
};
};
- port@2 {
+ port@4 {
reg = <4>;
soc_funnel_in_port1: endpoint {
- slave-mode;
- remote-endpioint =
+ remote-endpoint =
<&stm_out_port>;
};
};
@@ -224,11 +276,12 @@
reg = <0 0x10003000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etb_in: endpoint {
- slave-mode;
- remote-endpoint =
- <&soc_funnel_out_port>;
+ out-ports {
+ port {
+ etb_in: endpoint {
+ remote-endpoint =
+ <&soc_funnel_out_port>;
+ };
};
};
};
@@ -240,51 +293,51 @@
reg-names = "stm-base", "stm-stimulus-base";
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- stm_out_port: endpoint {
- remote-endpoint =
- <&soc_funnel_in_port1>;
+ out-ports {
+ port {
+ stm_out_port: endpoint {
+ remote-endpoint =
+ <&soc_funnel_in_port1>;
+ };
};
};
};
funnel@11001000 { /* Cluster0 Funnel */
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x11001000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
cluster0_funnel_out_port: endpoint {
remote-endpoint =
<&cluster0_etf_in>;
};
};
+ };
- port@1 {
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
cluster0_funnel_in_port0: endpoint {
- slave-mode;
remote-endpoint = <&etm0_out>;
};
};
- port@2 {
+ port@1 {
reg = <1>;
cluster0_funnel_in_port1: endpoint {
- slave-mode;
remote-endpoint = <&etm1_out>;
};
};
- port@3 {
+ port@2 {
reg = <2>;
cluster0_funnel_in_port2: endpoint {
- slave-mode;
remote-endpoint = <&etm2_out>;
};
};
@@ -292,7 +345,6 @@
port@4 {
reg = <4>;
cluster0_funnel_in_port3: endpoint {
- slave-mode;
remote-endpoint = <&etm3_out>;
};
};
@@ -300,50 +352,47 @@
};
funnel@11002000 { /* Cluster1 Funnel */
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x11002000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
cluster1_funnel_out_port: endpoint {
remote-endpoint =
<&cluster1_etf_in>;
};
};
+ };
- port@1 {
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
cluster1_funnel_in_port0: endpoint {
- slave-mode;
remote-endpoint = <&etm4_out>;
};
};
- port@2 {
+ port@1 {
reg = <1>;
cluster1_funnel_in_port1: endpoint {
- slave-mode;
remote-endpoint = <&etm5_out>;
};
};
- port@3 {
+ port@2 {
reg = <2>;
cluster1_funnel_in_port2: endpoint {
- slave-mode;
remote-endpoint = <&etm6_out>;
};
};
- port@4 {
+ port@3 {
reg = <3>;
cluster1_funnel_in_port3: endpoint {
- slave-mode;
remote-endpoint = <&etm7_out>;
};
};
@@ -356,22 +405,18 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
cluster0_etf_out: endpoint {
remote-endpoint =
<&main_funnel_in_port0>;
};
};
+ };
- port@1 {
- reg = <0>;
+ in-ports {
+ port {
cluster0_etf_in: endpoint {
- slave-mode;
remote-endpoint =
<&cluster0_funnel_out_port>;
};
@@ -385,22 +430,18 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
cluster1_etf_out: endpoint {
remote-endpoint =
<&main_funnel_in_port1>;
};
};
+ };
- port@1 {
- reg = <0>;
+ in-ports {
+ port {
cluster1_etf_in: endpoint {
- slave-mode;
remote-endpoint =
<&cluster1_funnel_out_port>;
};
@@ -409,36 +450,35 @@
};
funnel@11005000 { /* Main Funnel */
- compatible = "arm,coresight-funnel", "arm,primecell";
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0 0x11005000 0 0x1000>;
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
+ out-ports {
+ port {
main_funnel_out_port: endpoint {
remote-endpoint =
<&soc_funnel_in_port0>;
};
};
+ };
- port@1 {
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
reg = <0>;
main_funnel_in_port0: endpoint {
- slave-mode;
remote-endpoint =
<&cluster0_etf_out>;
};
};
- port@2 {
+ port@1 {
reg = <1>;
main_funnel_in_port1: endpoint {
- slave-mode;
remote-endpoint =
<&cluster1_etf_out>;
};
@@ -453,10 +493,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm0_out: endpoint {
- remote-endpoint =
- <&cluster0_funnel_in_port0>;
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in_port0>;
+ };
};
};
};
@@ -468,10 +510,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm1_out: endpoint {
- remote-endpoint =
- <&cluster0_funnel_in_port1>;
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in_port1>;
+ };
};
};
};
@@ -483,10 +527,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm2_out: endpoint {
- remote-endpoint =
- <&cluster0_funnel_in_port2>;
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in_port2>;
+ };
};
};
};
@@ -498,10 +544,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm3_out: endpoint {
- remote-endpoint =
- <&cluster0_funnel_in_port3>;
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&cluster0_funnel_in_port3>;
+ };
};
};
};
@@ -513,10 +561,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm4_out: endpoint {
- remote-endpoint =
- <&cluster1_funnel_in_port0>;
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in_port0>;
+ };
};
};
};
@@ -528,10 +578,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm5_out: endpoint {
- remote-endpoint =
- <&cluster1_funnel_in_port1>;
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in_port1>;
+ };
};
};
};
@@ -543,10 +595,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm6_out: endpoint {
- remote-endpoint =
- <&cluster1_funnel_in_port2>;
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in_port2>;
+ };
};
};
};
@@ -558,10 +612,12 @@
clocks = <&ext_26m>;
clock-names = "apb_pclk";
- port {
- etm7_out: endpoint {
- remote-endpoint =
- <&cluster1_funnel_in_port3>;
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&cluster1_funnel_in_port3>;
+ };
};
};
};
generated by cgit (git 2.34.1) at 2026-01-04 10:24:38 +0000