diff options
Diffstat (limited to 'arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 362 |
1 files changed, 362 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 7a82896dcbf6..c34cd33cd855 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,195 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + eth1_mdio_pins_a: eth1-mdio-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + st,io-sync = "data on both edges"; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + st,io-sync = "data on both edges"; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth1_rgmii_pins_b: eth1-rgmii-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */ + <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + st,io-sync = "data on both edges"; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('C', 6, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins4 { + pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + st,io-sync = "data on both edges"; + }; + pins5 { + pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('F', 8, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('C', 6, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = <STM32_PINMUX('B', 5, AF9)>, /* I2C2_SCL */ @@ -23,6 +212,124 @@ }; }; + ospi_port1_clk_pins_a: ospi-port1-clk-0 { + pins { + pinmux = <STM32_PINMUX('D', 0, AF10)>; /* OSPI1_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 0, ANALOG)>; /* OSPI1_CLK */ + }; + }; + + ospi_port1_cs0_pins_a: ospi-port1-cs0-0 { + pins { + pinmux = <STM32_PINMUX('D', 3, AF10)>; /* OSPI_NCS0 */ + bias-pull-up; + drive-push-pull; + slew-rate = <0>; + }; + }; + + ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 3, ANALOG)>; /* OSPI_NCS0 */ + }; + }; + + ospi_port1_io03_pins_a: ospi-port1-io03-0 { + pins { + pinmux = <STM32_PINMUX('D', 4, AF10)>, /* OSPI_IO0 */ + <STM32_PINMUX('D', 5, AF10)>, /* OSPI_IO1 */ + <STM32_PINMUX('D', 6, AF10)>, /* OSPI_IO2 */ + <STM32_PINMUX('D', 7, AF10)>; /* OSPI_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* OSPI_IO0 */ + <STM32_PINMUX('D', 5, ANALOG)>, /* OSPI_IO1 */ + <STM32_PINMUX('D', 6, ANALOG)>, /* OSPI_IO2 */ + <STM32_PINMUX('D', 7, ANALOG)>; /* OSPI_IO3 */ + }; + }; + + pcie_pins_a: pcie-0 { + pins { + pinmux = <STM32_PINMUX('J', 0, AF4)>; + bias-disable; + }; + }; + + pcie_init_pins_a: pcie-init-0 { + pins { + pinmux = <STM32_PINMUX('J', 0, GPIO)>; + output-low; + }; + }; + + pcie_sleep_pins_a: pcie-sleep-0 { + pins { + pinmux = <STM32_PINMUX('J', 0, ANALOG)>; + }; + }; + + pwm3_pins_a: pwm3-0 { + pins { + pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 15, ANALOG)>; /* TIM3_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = <STM32_PINMUX('J', 5, AF8)>, /* TIM8_CH1 */ + <STM32_PINMUX('J', 4, AF8)>; /* TIM8_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = <STM32_PINMUX('J', 5, ANALOG)>, /* TIM8_CH1 */ + <STM32_PINMUX('J', 4, ANALOG)>; /* TIM8_CH4 */ + }; + }; + + pwm12_pins_a: pwm12-0 { + pins { + pinmux = <STM32_PINMUX('B', 11, AF9)>; /* TIM12_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm12_sleep_pins_a: pwm12-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 11, ANALOG)>; /* TIM12_CH2 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */ @@ -99,6 +406,20 @@ }; }; + tim10_counter_pins_a: tim10-counter-0 { + pins { + pinmux = <STM32_PINMUX('B', 9, AF9)>; /* TIM10_CH1 */ + bias-disable; + }; + }; + + tim10_counter_sleep_pins_a: tim10-counter-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* TIM10_CH1 */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ @@ -128,6 +449,47 @@ <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ }; }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 13, AF3)>, /* USART6_TX */ + <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 14, AF3)>, /* USART6_RX */ + <STM32_PINMUX('F', 15, AF3)>; /* USART6_CTS_NSS */ + bias-pull-up; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('F', 15, ANALOG)>; /* USART6_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('G', 5, AF3)>; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 14, AF3)>; /* USART6_RX */ + bias-pull-up; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 13, ANALOG)>, /* USART6_TX */ + <STM32_PINMUX('G', 5, ANALOG)>, /* USART6_RTS */ + <STM32_PINMUX('F', 15, ANALOG)>, /* USART6_CTS_NSS */ + <STM32_PINMUX('F', 14, ANALOG)>; /* USART6_RX */ + }; + }; }; &pinctrl_z { |